JPH0917944A - Semiconductor device and hybrid integrated circuit device incorporating the semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To miniaturize a semiconductor device and a hybrid integrated circuit device used for a power control device, and to stabilize thermal characteristics. [Structure] Chips of NPN power transistor Q1 and NPN power transistor Q2 are rotated so that their emitters and bases are opposite to each other, and are formed adjacent to each other. When power is supplied to the composite NPN power transistor chip 11 to operate, heat is generated, and heat distribution states are shown in (b), (c), and (d). Since the NPN power transistors Q1 and Q2 are formed adjacent to each other by rotating 180 degrees, the heat distribution at the center is made uniform as shown in (d), and the heat is not concentrated on one side to operate. A stable operation of the composite NPN power transistor chip 11 can be ensured, and a semiconductor device in which heat concentration is unlikely to occur even when composited can be configured. The semiconductor device having the NPN power transistors Q1 and Q2 as one chip can reduce the heat sink for heat radiation and reduce the mounting area of the hybrid integrated circuit device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device forming a power transistor and a hybrid integrated circuit device incorporating the same.

[0002]

2. Description of the Related Art In recent years, a power control equipment device is a hybrid integrated circuit device including a semiconductor device forming a power transistor, a power block forming the power transistor, and a control block including a circuit for controlling the power block. It is configured by incorporating.

An example of a conventional hybrid integrated circuit device using this type of semiconductor device will be described below with reference to the drawings. FIG. 8 is a simplified internal circuit diagram of a conventional hybrid integrated circuit device for audio power amplifiers. In FIG. 8, Q1 and Q2 are NPN power transistors, Q3 and Q4 are PNP power transistors, and ICs.
Reference numerals 1 and IC2 are ICs for amplifying the input voltage, and R1 and R2 are speakers that are loads.

FIG. 9 is a perspective view showing a conventional hybrid integrated circuit device. In FIG. 9, 1 is a substrate, 2 is a heat sink for heat dissipation, 3 is a lead terminal for connecting to an external circuit, 4
8 is a control IC chip in which IC1 and IC2 shown in FIG. 8 are formed in one chip, 5 is a conductive foil on the substrate 1, 6 and 7 are NPN power transistors which are semiconductor devices of the NPN power transistors Q1 and Q2 shown in FIG. Chips 8 and 9 are shown in FIG.
A PNP power transistor chip, which is a semiconductor device of the PNP power transistors Q3 and Q4 shown in FIG. 10, 10a is a wire connecting the control IC chip 4 and the conductive foil 5, and 10b is N.
The wires connect the PN power transistor chips 6 and 7 and the PNP power transistor chips 8 and 9 and the conductive foil 5.

The audio power amplifier shown in FIG. 8 amplifies a signal input with a small signal by the IC1 and amplifies the output signal, and complements the output signal with an NPN power transistor Q1 and PNP power. The power is amplified by the transistor Q3, and a signal is output from the speaker R1 which is a load. The signal input to the IC2 is output from the NPN power transistor Q2 and the PNP power transistor Q4 to the speaker R2 in the same manner as described above. In the case of an audio amplifier, it is basically composed of two circuits, a left channel and a right channel.

In FIG. 9, a hybrid integrated circuit device for forming the circuit shown in FIG. 8 has a control IC chip 4 on a substrate 1.
Then, the NPN power transistor chips 6 and 7 and the PNP power transistor chips 8 and 9 which are previously die-bonded to the heat sink 2 for heat dissipation are soldered, and the wire 10a is formed.
Connect the control IC chip 4 and the conductive foil 5 with the wire 10b.
Then, the NPN power transistor chips 6 and 7 and the PNP power transistor chips 8 and 9 are connected to the conductive foil 5. Next, the lead terminal 3 connected to the external circuit is soldered to complete the assembly. The shape of the heat sink 2 for heat dissipation is standardized by each company for convenience of equipment and production.

[0007]

However, in an audio power amplifier having such a circuit configuration, it is necessary to mount four semiconductor devices forming power transistors. Further, in the hybrid integrated circuit device, it is difficult to increase the density because a gap is required between the heat sinks for heat dissipation when the heat sinks for heat dissipation are standardized or when the heat sinks are soldered. There is a problem in that it is difficult to downsize the power control device using the.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a semiconductor device used in a power control device, a hybrid integrated circuit device, and a semiconductor device having a stable thermal characteristic. An object is to provide a hybrid integrated circuit device incorporating the same.

[0009]

In order to achieve this object, a semiconductor device of the present invention includes a first chip in which a power transistor or a Darlington-connected power transistor is formed in one chip, and a first chip. And a second chip that is rotated so that the top, bottom, left, and right are reversed, the lower end of the first chip and the upper end of the second chip are adjacent to each other, and a pair of two chips forming a power transistor is formed. It is characterized by comprising a composite power transistor.

Further, it is composed of a first chip in which a power transistor or a power transistor connected by Darlington connection is formed on one chip, and a second chip obtained by rotating the first chip upside down and left and right. , First
And a second chip are alternately adjacent to each other and are formed of a composite power transistor in which at least three power transistor chips are formed as a set.

The hybrid integrated circuit device of the present invention is characterized by comprising a power block formed by die-bonding the semiconductor device to a heat sink for heat dissipation, and a control block for controlling the power block. .

Further, a first chip having a power transistor or a power transistor connected by Darlington connection on one chip is adjacent to a right end of the first chip and a left end of a second chip having the same structure as the first chip. The power block is formed by die-bonding a semiconductor device having a pair of two chips forming a power transistor to a heat sink for heat dissipation, and a control block for controlling the power block. .

Further, a power block formed by dice-bonding a plurality of sets of semiconductor devices each having two chips forming a power transistor as a pair to one heat sink for heat dissipation, and a control block for controlling the power block. It is configured to consist of.

[0014]

According to the above structure, in the semiconductor device, the lower end of the first chip forming the power transistor is adjacent to the upper end of the second chip obtained by rotating the first chip upside down. Then, the heat generation is dispersed by configuring the two chips forming the power transistor as a pair of chips as a composite power transistor.

The semiconductor device has a first chip and a second chip.
The chips are alternately adjacent to each other to constitute a composite power transistor in which at least three power transistor chips are combined to disperse heat.

Further, the hybrid integrated circuit device can be formed by die-bonding the semiconductor device to a heat radiation heat sink, thereby reducing the number of heat radiation heat sinks to be used.

In the hybrid integrated circuit device, a semiconductor having a pair of two chips forming a power transistor is formed by adjoining the left end of a chip having the same structure as the first chip in parallel to the right end of the first chip. By forming the device by die-bonding to the heat dissipation heat sink, the heat dissipation heat sink to be used can be reduced.

Further, in the hybrid integrated circuit device, a plurality of sets of the above semiconductor devices are formed by die-bonding to one heat radiation heat sink, so that the heat radiation heat sink to be used can be reduced.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a composite NPN power transistor chip of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, E1 is the emitter of the NPN power transistor Q1, B1 is the base of the NPN power transistor Q1, and E2 is the NPN power transistor Q2.
, B2 is the base of the NPN power transistor Q2, and C is the common collector of the NPN power transistors Q1 and Q2. 2 (a) is an enlarged top view showing the composite NPN power transistor chip in the first embodiment, FIG. 2 (b) is a view showing heat distribution in the F1-F2 cross section, and FIG. 2 (c) is G1-. Diagram showing heat distribution in G2 cross section, Fig. 2 (d) is H
It is a figure which shows the heat distribution of a 1-H2 cross section.

In FIG. 2 (a), 11 is the NP shown in FIG.
An NPN power transistor chip forming an N power transistor Q1 and an NPN power transistor Q2 having the same structure as that of the NPN power transistor chip is formed into a pair of chips by adjoining a chip obtained by rotating the same NPN power transistor chip by 180 degrees. NPN power transistor chip. FIG. 3 is a schematic cross-sectional view showing a structure of a cross section D1-D2 of the composite NPN power transistor chip of FIG. 2 (a).

Next, the semiconductor device configured as described above will be described. First, as shown in FIG. 8 of the conventional example, in the internal circuit diagram, NPN power transistors Q1, Q
The two collectors are electrically common. Also in the circuit diagram shown in FIG. 1 in which that portion is extracted, the collectors of the NPN power transistors Q1 and Q2 are common, so that FIG.
As shown in FIG. 5, the emitter E1 and the base B1 of the NPN power transistor Q1 are rotated so that their positions are opposite to each other to form a pair of adjacent chips. The rotated NPN power transistor Q1, emitter E1, and base B1 are NPN.
A power transistor Q2, an emitter E2 and a base B2. As a result, the base B1, the emitter E1 of the NPN power transistor Q1 and the NPN power transistor Q1 are
The base 2 and the emitter E2 of 2 can be electrically completely insulated to form a semiconductor device of a composite NPN power transistor chip 11. Similarly to the above, P shown in FIG.
PN power transistors Q3 and Q4 also have composite PN
A semiconductor device of a P power transistor chip can be constructed.

Next, the above-mentioned NPN power transistor Q
When power is supplied to the composite NPN power transistor chip 11 composed of 1 and Q2 and the composite NPN power transistor chip 11 operates, heat is generated. The state of this heat distribution is shown in FIGS. 2 (b), 2 (c), and 2 (d). The emitters E1 and E2 generate more heat than the bases B1 and B2. Here, since the chip of the NPN power transistor Q2 is formed by rotating 180 degrees with respect to the chip of the NPN power transistor Q1, the heat distribution in the central portion of the composite NPN power transistor chip 11 is shown in FIG. 2 (d). It is homogenized as shown and can operate without heat concentration on one side. As a result, more stable operation of the composite NPN power transistor chip 11 can be ensured, and a semiconductor device in which heat concentration does not easily occur even when the power transistor chips are composited can be configured.

In the structure of the semiconductor device described above,
The NPN power transistors Q1 and Q2 forming the composite NPN power transistor chip 11 and the composite PNP power transistor chips and the PNP power transistors Q3 and Q4 are formed as a pair of chips. Power transistor chip, P
Similarly to the first embodiment, the NP power transistor chips can be configured as a set of chips in which three or more are alternately rotated and adjacently formed.

FIG. 4 is a perspective view showing a hybrid integrated circuit device incorporating the semiconductor device of the first embodiment in the second embodiment of the present invention. Further, the same members described in FIG. 9 of the conventional example are denoted by the same reference numerals, and the same applies to the following drawings. In FIG. 4, 1 is a substrate, 2 is a heat sink for heat dissipation, 3 is a lead terminal, and 4 is a control IC.
Chips, 10a and 10b are wires, 11 is a composite NPN power transistor chip, and 12 is a PNP power transistor Q3 or PNP power transistor Q4 shown in FIG. Is a composite PNP power transistor chip.

Next, the hybrid integrated circuit device configured as described above will be described based on the internal circuit diagram of FIG. 8 of the conventional example. As shown in FIG. 8, the collectors of NPN power transistors Q1 and Q2 or the collectors of PNP power transistors Q3 and Q4 are electrically common. In addition, the composite NPN power transistor chip 11 and the composite PN
Since the P power transistor chip 12 has the same configuration, only the composite NPN power transistor chip 11 will be described.

Composite NPN power transistor chip 11
As shown in the schematic cross-sectional view of FIG. 3, the substrate on the back side serves as a common collector, and the hybrid integrated circuit device shown in FIG. 4 is formed by the semiconductor device in which the NPN power transistors Q1 and Q2 are one chip. The NPN power transistors Q1 and Q2 can share the heat sink 2 for heat radiation. As compared with the conventional hybrid integrated circuit device shown in FIG. 9, the heat sink 2 for heat radiation can be reduced and the mounting area of the hybrid integrated circuit device can be reduced. Moreover, since the common collectors of the NPN power transistors Q1 and Q2 are connected by the substrate, the connection between the collectors is unnecessary,
The voltage drop due to the connection resistance can be eliminated.

As described above, the semiconductor device is die-bonded to the heat sink 2 for heat radiation shown in FIG. 4 to form a hybrid integrated circuit device, whereby the packaging density can be increased and the size can be reduced. A hybrid integrated circuit device having stable operation and long thermal fatigue life can be constructed.

FIG. 5 is a perspective view showing a hybrid integrated circuit device according to the third embodiment of the present invention. In FIG. 5, 13 is two N of the NPN power transistor chip 6 and the NPN power transistor chip 7 shown in FIG.
A collective NPN power transistor chip, which is a semiconductor device cut into one chip so as to have a built-in PN power transistor, is a PNP power transistor chip 8 and a PNP power transistor chip 9 shown in FIG. NP which is a semiconductor device cut into one chip so that
N power transistor chip.

Further, FIG. 6 shows the NPN in the third embodiment.
In the top view showing the wafer of the power transistor chip,
15 is an NPN power transistor chip 6, 7 shown in FIG.
It is an NPN power transistor wafer before cutting which constitutes the. Since the set NPN power transistor chip 13 and the set NPN power transistor chip 14 have the same configuration as in the second embodiment, only the set NPN power transistor chip 13 will be described.

Now, NPN power transistor wafer
When cutting 15, cut the NPN power transistor to 2
Each piece is cut into one chip to obtain a collective NPN power transistor chip 13 which is a semiconductor device.
This is die-bonded to the heat dissipation heat sink 2 to form a hybrid integrated circuit device. As a result, the heat radiation heat sink 2 can be reduced as in the second embodiment, and the mounting area of the hybrid integrated circuit device can be reduced.

Considering the set NPN power transistor chip 13 as the NPN power transistor chip 6 in the first embodiment, the set NPN power transistor chip 6 is rotated 180 degrees with respect to one set NPN power transistor chip, and the other set N is adjacent.
It is also possible to form a PN power transistor chip as a pair of chips and perform die bonding to the heat sink 2 for heat dissipation to form a hybrid integrated circuit device. However, in this case, the hybrid integrated circuit device has four NPN power transistors having a common collector incorporated in the circuit configuration.

FIG. 7 is a perspective view showing a hybrid integrated circuit device according to the fourth embodiment. Here, as shown in FIG.
In order to explain based on the internal circuit diagram shown in FIG.
PN power transistor chip. In FIG.
The NPN power transistor chip 6 and the NPN power transistor chip 7 are die-bonded to the same heat sink 2 for heat radiation, and similarly, the PNP power transistor chip 8 and the PNP power transistor chip 9 are also the same heat sink 2 for heat radiation. Is a hybrid integrated circuit device configured by die-bonding to. Second
As in the third embodiment, the heat sink 2 for heat dissipation can be reduced and the mounting area of the hybrid integrated circuit device can be reduced.

Further, the NPN power transistor chips 6 and 7 are the composite NPN power transistor chip 11 described in the first embodiment, and the collective NP described in the second embodiment.
By replacing the N power transistor chip 13 with the heat sink 2 for heat dissipation and forming a hybrid integrated circuit device, the mounting area can be made smaller than that of the hybrid integrated circuit device in which the same number of power transistor chips are mounted. it can.

It is to be noted that an audio amplifier is required for each channel in order to support multi-channels, and the contents of each of the above embodiments have been described with the circuit configuration of 2 channels, but the concept of 3 channels or more is also applicable. Similarly, a high-density hybrid integrated circuit device can be constructed by decoding power transistors of three or more chips.

In the power transistor used in the above description, one power transistor is described as one chip, but it goes without saying that the same result can be obtained by using the Darlington connection power transistor as one chip. Absent.

It should be noted that although the above-mentioned contents are bipolar power transistors, they are MOS type power FETs.
The same can be said for.

[0037]

As described above, according to the present invention,
By rotating one of the two power transistor chips by 180 degrees with respect to the other to form a pair of adjacent chips, it is possible to configure a semiconductor device in which heat concentration does not easily occur even when the power transistor chips are combined. it can.

Alternately, the power transistor chips are alternately
By rotating 180 degrees and adjoining and forming three or more as a set, it is possible to configure a semiconductor device in which heat concentration does not easily occur even when a plurality of power transistor chips are combined.

The semiconductor device eliminates the need for collector connection between the conductive foil of the substrate and the NPN power transistor or between the PNP power transistors, and there is no voltage drop due to the resistance of the conductive foil. By configuring the hybrid integrated circuit device, it is possible to increase the packaging density and reduce the size of the hybrid integrated circuit device to achieve stable operation of characteristics and long thermal fatigue life.

Also, a semiconductor device in which two power transistor chips are adjacently arranged in parallel and formed as a pair of chips is die-bonded to a heat radiation heat sink to reduce the number of heat radiation heat sinks to be used and reduce the number of parts. The packaging density of circuit devices can be increased.

Further, by dicing a plurality of sets of semiconductor devices to one heat sink, the number of heat sinks used can be reduced, the number of components can be reduced, and the packaging density of the hybrid integrated circuit device can be increased. it can.

Further, even if the number of power transistors used in the circuit is increased, it is possible to increase the packaging density and downsize the hybrid integrated circuit device incorporating the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a composite NPN power transistor chip according to a first embodiment of the present invention.

FIG. 2 (a) is a composite NP in the first embodiment of the present invention.
An enlarged top view showing an N power transistor chip, (b) showing heat distribution in the F1-F2 cross section, (c) showing heat distribution in the G1-G2 cross section, (d) showing heat in the H1-H2 cross section. It is a figure which shows distribution.

FIG. 3 is a schematic cross-sectional view showing a structure of a cross section D1-D2 of the composite NPN power transistor chip in the first example of the present invention.

FIG. 4 is a perspective view showing a hybrid integrated circuit device incorporating the semiconductor device of the first embodiment in the second embodiment of the present invention.

FIG. 5 is a perspective view showing a hybrid integrated circuit device according to a third embodiment of the present invention.

FIG. 6 is a top view showing a wafer of NPN power transistor chips according to a third embodiment of the present invention.

FIG. 7 is a perspective view showing a hybrid integrated circuit device according to a fourth embodiment of the present invention.

FIG. 8 is a simplified internal circuit diagram of a conventional hybrid integrated circuit device for an audio power amplifier.

FIG. 9 is a perspective view showing a conventional hybrid integrated circuit device.

[Explanation of symbols]

1 ... Substrate, 2 ... Heat sink for heat dissipation, 3 ... Lead terminal, 4 ... Control IC chip, 5 ... Conductive foil, 6, 7
… PNP power transistor chips, 8, 9… PNP
Power transistor chip, 10a, 10b ... Wire, 11
… Composite NPN power transistor chip, 12… Composite P
NP power transistor chip, 13 ... Assembly NPN power transistor chip, 14 ... Assembly NPN power transistor chip, 15 ... NPN power transistor wafer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumio Hori 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] 1. A first chip in which a power transistor or a power transistor connected to a Darlington connection is formed on one chip, and a second chip obtained by rotating the first chip so that the vertical and horizontal directions are reversed. A semiconductor device comprising a composite power transistor in which a lower end of the first chip and an upper end of the second chip are adjacent to each other and two chips forming a power transistor are paired. 2. A first chip in which a power transistor or a power transistor connected by Darlington connection is formed on one chip, and a second chip obtained by rotating the first chip upside down and leftward and rightward. And a semiconductor device comprising a composite power transistor including at least three power transistor chips formed by alternately adjoining the first chip and the second chip. 3. A hybrid integrated circuit comprising a power block formed by die bonding the semiconductor device according to claim 1 or 2 to a heat sink for heat dissipation, and a control block for controlling the power block. apparatus. 4. A first chip having a power transistor or a Darlington-connected power transistor formed on one chip, and a left end of a second chip having the same structure as the first chip at the right end of the first chip. A power block formed by die-bonding a semiconductor device having two chips forming a power transistor as a pair to a heat sink for heat dissipation, and a control block for controlling the power block. Characteristic hybrid integrated circuit device. 5. A power block formed by dice-bonding a plurality of sets of semiconductor devices each having two chips forming a power transistor as a pair to one heat sink for heat dissipation, and a control block for controlling the power block. And a hybrid integrated circuit device.