JPH09180444A - Word driver circuit and memory circuit using the same - Google Patents

Abstract

(57) Abstract: A sub word driver circuit is simplified to reduce the number of elements and control signals. A word driver circuit includes first and second input terminals, an output terminal connected to a word line, a gate connected to the first input terminal, and one of a source electrode and a drain electrode being the first input terminal. A first P-channel transistor connected to the two input terminals and having the other of the source or drain electrodes connected to the output terminal; and one of the source or drain electrodes having the gate connected to the first input terminal Is connected to the first power supply and the other of the source or drain electrode is connected to the output terminal. The first input terminal is generated by decoding the first address group, and is one of the first potential required to turn on the second transistor and the second potential lower than the first power supply. A first selection signal that becomes a potential is supplied, and a second input terminal has a third potential that is the potential when the word line is in the selected state and a fourth potential that is less than or equal to the potential of the first power supply. A second selection signal that is one of the potentials is supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to improvement of a word driver circuit of the memory circuit.

[0002]

2. Description of the Related Art DRAMs and the like in which a large-capacity memory is formed on a semiconductor substrate have been actively developed, and by increasing the capacity, information devices such as personal computers and the like having higher functions and higher speeds have been realized.

FIG. 6 is a circuit diagram showing a word decoder and a word driver portion of a conventional DRAM. Usually, a plurality of areas called memory banks are provided on a semiconductor chip, and a plurality of memory cell blocks and sense amplifiers are provided in the memory bank area. FIG. 6 shows the memory cell block 3 and the sense amplifier SA adjacent thereto. A plurality of cell matrices 4 are provided in the memory cell block 3. A plurality of word lines WL and a plurality of bit lines (not shown) intersecting with the word lines WL are provided in the cell matrix 4. And at the intersection of those word lines and bit lines,
A memory cell (not shown) is provided.

Due to the increase in the capacity of recent memories, the load capacity applied to the word lines becomes large, and it becomes difficult to collectively drive the word lines in the memory cell block 3 by one word driver as in the conventional case. Has become. As a solution, the word line is divided into a plurality of sub-word lines, and each sub-word line is driven by a sub-word driver SWD provided adjacent to the cell matrix 4. In the example of FIG. 6, for example, 256 word lines are provided in the memory cell block 3, and the main word decoder 5 selects four of these word lines, and the selected word line is selected from the selected four word lines. One is selected by the sub-word decoder 6.

As shown in FIG. 6, the main word decoder 5 outputs inverted and non-inverted main word selection signals MWX0,1, MWZ0,1. In addition, the sub word selection signal SWD is output from the sub word decoder 6.
0-3 is output. In each decoder 5,6,
Address signals 7 and 8 supplied from the predecoder are supplied. Then, the sub-word driver circuit SWD inputs the main word selection signal and the sub-word selection signal to drive each sub-word line in the selected row.

Therefore, as shown in FIG. 6, the sub word driver circuit SWD is provided between and adjacent to the cell matrix 4.
Area is formed in the column direction. As the capacity of the memory increases, the number of sub-word lines increases and the area of the sub-word driver circuit that drives them also increases, which is one of the problems of increasing the capacity.

FIG. 7 details an example of the conventional sub-word driver circuit shown in FIG. FIG. 8 is a table for explaining the operation. The sub-word driver circuit in FIG. 7 is composed of a CMOS circuit including a P-channel type transistor Q1 and N-channel type transistors Q2 and Q3. Then, the sub word driver circuit is connected to the sub word line WL. BL is a bit line, MC
Is an example of a one-transistor type memory cell. The main word selection signal MWX is commonly supplied to the gate electrodes of the transistors Q1 and Q2, and the main word selection signal M which is the inverted signal thereof is supplied to the gate electrode of the transistor Q3.
WZ is supplied. The sub-word selection signal S is supplied to the P-type transistor Q1 and the N-type transistor Q3.
WD0 is supplied.

The operation will be briefly described. First,
When both the main word selection signal and the sub word selection signal are in the selected state, as shown in FIG.
X, MWZ, and SWD0 are Vss (ground level), Vcc (power supply level), and SVc (higher than the power supply), respectively. As a result, the transistors Q1 and Q3 are both turned on, the transistor Q2 is turned off, and the word line W
L is driven to a high level of SVc of the sub word selection signal SWD0. On the other hand, when the main word selection signal is in the selected state and the sub word selection signal is in the non-selected state, the potential is as shown in FIG. as a result,
Although the P-type transistor Q1 is in the ON state, the word line WL becomes L level because the sub-word selection signal SWD0 becomes Vss (ground) level. However, only with the P-type transistor Q1, the word line WL does not fall below the potential higher than the threshold voltage Vss, which is the gate potential of the transistor, by the threshold voltage or more, and the word line WL becomes a floating state. Therefore, by further providing an N-type transistor Q3, that transistor Q3 is turned on, and the sub
The word select signal SWD0 is clamped to the Vss level.

When the main word selection signal is in the non-selected state, the main word selection signal MWX becomes H level and the N-type transistor Q2 is turned on, so that the word line WL is not affected by the state of the sub word selection signal. It becomes the Vss level.

As described above, it is necessary to supply the three transistors and the three selection signals in the sub-word dramba circuit shown in FIG.

FIG. 9 shows an example of another CMOS circuit of the conventional sub word driver circuit. FIG. 10 shows the level of each selection signal for explaining the operation. When the main word selection signal is in the selected state and the sub word selection signal is in the selected state, the main word selection signal MWX becomes Vss (ground) level, the P-type transistor Q4 turns on, and the sub word selection signal The word line is driven by SVc higher than the power supply voltage Vcc supplied to SWDZ to rise to the SVc level. On the other hand, when the main word selection signal is in the selected state and the sub word selection signal is in the non-selected state, the sub word selection signal SWDZ
Becomes the Vss level, the word line WL becomes the L level through the transistor Q4. However, as in the case of FIG. 6, according to the characteristics of the P-type transistor Q4, the potential of the word line WL becomes a floating state at a level obtained by adding the threshold voltage to the Vss level of the potential of the gate electrode. Therefore, an N-type transistor Q6 is provided as a clamping transistor to force the word line WL to Vs.
It is set to s level.

Therefore, even in the example of the word dramba shown in FIG.
Three transistors and three control signals are needed.

[0013]

[Problems to be Solved by the Invention]
When dividing into word lines and driving each by a sub word driver circuit, in the conventional circuit example, three transistors are required in the sub word driver circuit, and further three selection signals need to be supplied. There is.

As shown in the area of the memory cell block 3 in FIG. 6, a plurality of sub-word driver circuits are formed in the column direction, and three selection signals are supplied to them. Therefore, the area of the region used by these circuits and the selection signal line supplied thereto becomes an adverse effect of miniaturization accompanying the increase in the capacity of the memory.

Therefore, it is an object of the present invention to simplify the configuration of this sub-word deliver circuit.

The object of the present invention is to provide a more simplified sub
It is to provide a memory circuit having a word driver circuit.

Another object of the present invention is to provide a memory circuit having a sub-word driver circuit whose operation is controlled by a smaller number of selection signals.

Another object of the present invention is to provide a sub-circuit composed of two transistors and two control selection signals.
It is to provide a word driver circuit.

[0019]

SUMMARY OF THE INVENTION According to the present invention, the above object is provided in a memory circuit to which a first power source and a second power source higher than the first power source are supplied, the first conductivity type first And the first transistor and the gate are commonly connected, one of the source and drain electrodes is connected to one of the source and drain electrodes of the first transistor, and the other of the source and drain electrodes is the first transistor. A second transistor of a second conductivity type connected to the power supply of, and a word line is connected to the commonly connected source or drain electrodes of the first and second transistors, and the word line is connected to the common. To the gate electrode, which is generated by decoding the first address signal group and which makes one of the first potential for making the second transistor conductive and the second potential lower than the first power source. Is supplied to the other electrode of the source or drain electrode of the first transistor, the second address signal group is generated by decoding, and the first potential of the selected state of the word line is generated. This is achieved by providing a word driver circuit characterized by being supplied with a second selection signal which is one of a third potential and a fourth potential which is lower than the potential of the first power supply.

Here, the first conductivity type transistor is, for example, a P-channel type MOS transistor, and the second conductivity type transistor is, for example, an N-channel type MOS transistor.

The second potential is preferably at a level lower than the potential of the first power source by the threshold voltage of the first transistor or more. In practice, it is practical and easy to set the substrate bias potential generated in the memory circuit.

In order to make the operation more stable, it is desirable that the fourth potential is lower than the potential of the first power source. For example, it is practical to set the substrate bias potential like the second potential.

With this structure, the word driver circuit is composed of two transistors, and the number of selection signals for controlling the word driver circuit is only two. With the above structure, since the potential supplied to the gate electrode of the P-channel first transistor is lower than the ground level by the threshold voltage or more, the potential of the word line connected to the source or drain electrode of the first transistor is reduced. The potential can be clamped to a sufficiently low level.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. It is apparent that the circuits in the drawings shown below are examples of the embodiments of the present invention, and the technical scope of the present invention is not limited to such circuits.

[Word Driver Circuit] FIG. 1 shows an example of a sub word driver circuit according to the present invention. In this example, the CMOS circuit is composed of a P-channel type transistor Q7 and an N-channel type transistor Q8. The main word selection signal MWX is supplied to the common gate electrode. The sub-word selection signal SWD is applied to the electrode of the transistor Q7 on the side opposite to the word line WL.
Is supplied. This main word selection signal MWX is
Unlike the case of the conventional example, the potential becomes lower than the Vss (ground) level in the selected state. Further, the sub-word selection signal SWD is Vss (land) in the non-selected state.
The potential becomes lower than the level or Vss (land) level.

In the figure, the substrate bias potential VBB generated as the potential of the semiconductor substrate is used as an example of the potential lower than the Vss (ground) level. However, the substrate bias potential does not have to be the substrate bias potential, and may be a low level necessary for the unselected word lines WL to sufficiently drop to the Vss (ground) level.

The operation of the sub word driver circuit of FIG. 1 will be described with reference to FIG. First, when both the main word selection signal MWX and the sub word selection signal SWD are in the selected state, the word line WL is also in the selected state. At this time, the main word selection signal MWX becomes VBB level lower than the ground level, and the sub word selection signal SWD becomes level SVc higher than the power supply voltage Vcc. As a result, the P-type transistor Q7 is turned on, and the word line WL rises to the same SVc level as the sub-word selection signal SWD. Then, the transistor of the memory cell MC is turned on, and the level of the bit line BL rises or falls according to the state stored in the capacitor.

On the other hand, even when the main word selection signal MWX is in the selected state, when the sub word selection signal SWD is in the non-selected state, the word line WL is in the non-selected state and needs to be lowered to the ground level. The word line WL is
According to the characteristics of the P-type transistor, the potential becomes a voltage obtained by adding the threshold voltage Vth to the voltage of the gate electrode, but in this example, since the main word selection signal MWX has a substrate bias potential lower than the ground, the word line The level of WL becomes VBB + Vth. Therefore, when the substrate bias potential VBB is lower than the ground level by the threshold voltage Vth of the P-type transistor or more, the level of the word line WL becomes the ground potential or lower.

The potential of the sub-word selection signal SWD in the non-selected state becomes Vss (ground) level or a lower level, for example, the substrate bias potential VBB. In order to more stably bring the unselected word lines WL to the ground potential or lower, it is desirable to set the substrate bias potential lower than the ground level.

When the main word selection signal MWX is in the non-selected state, its level becomes the high power supply Vcc level. Normal power supply Vcc is set to a level such as 3 volts or 3.6 volts. As a result, in the sub word driver circuit, the N-type transistor Q8 is turned on,
The word line WL is clamped to the ground level Vss via the transistor Q8. In this case, the state of the sub word selection signal is not affected.

As described above, the word driver circuit for driving the word line is composed of two transistors, and the number of selection signals for controlling the word driver circuit is also two. As described above, the minimum condition is that the level of the main word selection signal MWX supplied to the gates of both transistors in the selected state is higher than the threshold voltage of the non-selected word line in the P-type transistor. To lower the potential.
By doing so, the word line can be sufficiently clamped to the level of the non-selected state of the sub word selection signal SWD. Also, the sub word decoder and the transistor Q7
In consideration of the voltage rise of the sub-word selection signal line connecting with and other factors, it is desirable that the sub-word selection signal SWD also has a potential sufficiently lower than the level of the non-selected word line.

The main word selection signal and the sub word selection signal need not be supplied as shown in FIG. 1, but may be supplied to the opposite terminals. That is, the first selection signal generated by decoding the first address group and the second selection signal generated by decoding the second address group are the common gate electrode of the CMOS circuit of FIG. Therefore, it is clear that the voltage may be supplied to the source or drain electrode of the P-type transistor Q7.

[Overall Configuration of Memory Cell Block] FIG.
2 shows an overall configuration of a memory cell block when the sub word driver circuit of FIG. 1 is used. The entire memory bank 2 is shown in FIG. As described above, a plurality of regions of the memory bank 2 are formed on the semiconductor chip. A plurality of memory cell blocks 3 are formed in the memory bank 2. In the example of FIG. 3, two memory cell blocks 3 are shown.

As schematically shown in the lower half of FIG. 3, the sense amplifier S is vertically adjacent to the memory cell block 3.
A1 and 2 are provided. Further, in the memory cell block 3, a cell matrix 4 and an array SWDA of sub word drivers are alternately formed. Then, in order to select the word line, for each cell array block 3,
A main word decoder circuit 5 and a sub word decoder circuit 6 are provided. Main word decoder 5
Main word selection signals MWX0, 1 from the sub word selection signal SWD0-
3 and 3 are supplied to the sub-word driver circuit, and the sub-word driver circuit in which both selection signals are in the selected state drives the word line to rise to the H level. 7,8
Are address signals, block selection signals, etc. supplied from the respective predecoders.

In the memory cell block 3 in the upper half of FIG. 3, how the main word selection signal and the sub word selection signal are supplied to the sub word driver circuit SWD is shown. The main word decoder 5 selects the main word selection signal MW so as to select, for example, four of 256 word lines in one memory cell block 3.
Output X. Then, the main word selection signal is supplied to the sub-word driver SWD connected to each of the divided word lines WL. The sub-word decoder 6 selects the sub-word selection signals SWD0-3 SWD0-3 in order to select one of the four word lines.
Is supplied to each sub-word driver SWD.

In the example of FIG. 3, the sense amplifier SA0-2
Are provided adjacently above and below the memory cell block 3. By doing so, the adjacent memory cell blocks 3
However, it is possible to share the sense amplifier between them, and the area occupied by the sense amplifier can be reduced accordingly. In FIG. 3, bit lines are omitted for simplicity.

FIG. 4 is a circuit example showing the memory cell block of FIG. 3 in more detail. WL0-7 are bit lines, which are divided and arranged in the row direction. BL is a bit line, which is connected to the adjacent sense amplifier SA. A memory cell MC is provided at the intersection of the word line WL and the bit line BL. FIG. 4 shows an example including one N-channel transistor and one capacitor. The sub word driver SW0 is connected to the word line WL0. The word line WL1 has a sub
The word dramba SW1 is connected. The word lines WL2 and WL3 arranged in the cell matrix regions on both sides are connected to the sub word drivers SW2 and SW3. These sub word drivers are the circuit example shown in FIG. 1, and the selection signals MWX0, 1 from the main word decoder 5 are supplied to the gate electrodes, and the corresponding selections from the sub word decoder 6 are made. Signal SWD0-
3 is supplied to the source or drain electrode of the P-type transistor Q7.

As shown in FIG. 4, the power source on the high side of the main word decoder 5 is Vcc, while the substrate bias voltage VBB is used as the lower potential. As an example of the circuit of the main word decoder 5, two decoder circuits composed of P-type transistors Q9, Q11, Q13, Q14 and N-type transistors Q10, Q12, Q15, Q16 are shown. The block selection signal 7-5 (a part of the address signal 7) is commonly supplied to the transistors Q11, Q12, and Q13. Also,
Transistors Q9, Q10 and Q14, Q15 and Q1
Different address signals 7 are supplied to 6 respectively.
Now, when the block selection signal becomes H level, the transistor Q12 is turned on and the entire decoder circuit is activated. Then, each decoder sets the selection signals MWX0, 1 to the level of the selected state or the non-selected state according to the states of the remaining address signals.

When the main word selection signal MWX0 is in the selected state, for example, the address signal 7-3 is at H level,
The address signal 7-2 becomes H level, and the transistor Q
10, Q16 is turned on. As a result, the main word selection signal MWX0 becomes the substrate bias potential VBB. At that time, the main word selection signal MWX1 is
The address signal 7-4 becomes L level and the transistor Q1
4 is turned on, and the selection signal MWX1 becomes Vcc (H level).

In the case of the sub word decoder 6 as well, the SVc level and the VBB level are output to the sub word selection signal by a similar circuit. Then, the sub-word driver circuit supplied with both selection signals operates as described according to FIGS.

FIG. 5 is an example of a timing chart according to the embodiment of the present invention. 5 is a timing chart in the case where the word line WL0 is selected in the example of FIG. In this example, the sub-word selection signal is the substrate bias voltage VBB in the non-selected state.

As shown in FIG. 5, for example, at the timing time ta of the row address strobe signal RAS, the memory circuit becomes active. As a result, the output of each decoder changes according to the supplied address signal. In the example of FIG. 5, since the word line WL0 is selected, the main word selection signal MWX0 is selected.
Falls from the power supply Vcc level to the substrate bias potential VBB, and the sub-word selection signal SWD0 rises from the substrate bias potential VBB to a potential SVc higher than the power supply.

On the other hand, the sub-channel corresponding to the non-selected word line is
The word selection signals SWD1-3 fall to the substrate bias potential VBB, and the main word selection signal MWX1 rises to the power supply voltage Vcc. As a result, as explained in FIG.
The sub word driver SW0 drives the word line WL0 and raises it to the SVc level. The other sub word drivers SW1-3 are P-type transistors Q7.
Through the word line to the sub-word selection signals SWD1-3
To the substrate bias potential VBB, and each word line is clamped to the L level.

Then, when the word line WL0 rises, the latch control signal LE is supplied to the sense amplifier, whereby the rising or falling level according to the information of the memory cell MC read to the bit line BL is amplified.

[0045]

As described above, according to the present invention, the sub word driver circuit is composed of two transistors, and the number of selection signals supplied to the sub word driver circuit is two. Therefore, as shown in FIGS. 3 and 4, the area occupied by the sub-word driver array region can be reduced.

[Brief description of the drawings]

FIG. 1 is an example of a sub-word driver circuit of the present invention.

FIG. 2 is a table for explaining the operation of the circuit of FIG.

FIG. 3 is an overall configuration diagram of a memory cell block according to the present invention.

FIG. 4 is a detailed circuit example of a memory cell block according to the present invention.

FIG. 5 is a timing chart diagram of the embodiment of the present invention.

FIG. 6 is a diagram showing a conventional example.

FIG. 7 is an example of a conventional sub-word driver circuit.

8 is a table for explaining the operation of the circuit of FIG.

FIG. 9 is an example of a conventional sub-word driver circuit.

FIG. 10 is a table for explaining the operation of the circuit of FIG.

[Explanation of symbols]

 Vss first power supply Vcc second power supply Q7 first transistor Q8 second transistor MWX first selection signal, main word selection signal SWD second selection signal, sub word selection signal WL word line BL bit line 3 memory cell block 4 cell matrix 5 main word decoder 6 sub word decoder

Claims (14)

[Claims] 1. A memory circuit supplied with a first power supply and a second power supply higher than the first power supply, wherein a first transistor of a first conductivity type and the first transistor and gate are commonly connected. One of the source or drain electrode is connected to one of the source or drain electrode of the first transistor, and the other of the source or drain electrode is connected to the first power source. A word line is connected to a commonly connected source or drain electrode of the first and second transistors, and the first address signal group is decoded to the commonly connected gate electrode. A first selection signal that is generated by the first selection signal and that is one of a first potential that makes the second transistor conductive and a second potential that is lower than the first power supply. The other of the source or drain electrodes of the transistor is generated by decoding the second address signal group, and the third potential of the potential of the selected state of the word line and the fourth potential equal to or lower than the potential of the first power supply are generated. The word driver circuit is supplied with a second selection signal which becomes one of the potentials of the above. 2. The word driver circuit according to claim 1, wherein the second potential is at a level lower than the potential of the first power supply by a threshold voltage of the first transistor or more. circuit. 3. The word driver circuit according to claim 1, wherein the fourth potential is lower than the potential of the first power supply. 4. The word driver circuit according to claim 3, wherein the fourth potential is at substantially the same level as the second potential. 5. The word driver circuit according to claim 1, wherein the second potential is a substrate bias potential generated in the memory circuit. 6. The word driver circuit according to claim 1, wherein the fourth potential is a substrate bias potential generated in the memory circuit. 7. The word driver circuit according to claim 1, wherein the first potential is equal to or near the potential of the second power supply. 8. A memory circuit in which a first power supply at a ground level and a second power supply at a higher level are supplied, wherein a word driver circuit has first and second input terminals. An output terminal connected to a word line and a gate are connected to the first input terminal, one of a source or drain electrode is connected to the second input terminal, and the other of the source or drain electrode is connected to the output terminal. A connected P-channel first transistor, a gate connected to the first input terminal, one of a source or drain electrode connected to the first power supply, and the other source or drain electrode connected to the output An N-channel type second transistor connected to the terminal, wherein the first input terminal is generated by decoding a first address group, and the second transistor A first selection signal that is one of a first potential necessary for conduction and a second potential lower than the first power source is supplied, and the second input terminal has the word line. Is supplied with a second selection signal, which is one of the third potential which is the potential when making the selected state and the fourth potential which is lower than the potential of the first power source. Word driver circuit. 9. The word driver circuit according to claim 8, wherein the second potential is a substrate bias potential generated in a memory circuit. 10. The word driver circuit according to claim 8, wherein the fourth potential is a substrate bias potential generated in a memory circuit. 11. A memory circuit supplied with a first power supply at a ground level and a second power supply at a higher level, the memory circuit being arranged over a plurality of rows and divided into a plurality of rows for each row. Selected word line, a plurality of bit lines intersecting the word line, a plurality of memory cells provided at the intersection of the word line and the bit line, and a first address group are decoded to select a main word. A main word decoder that outputs a signal, a sub word decoder that decodes the second address group and outputs a sub word selection signal, and the corresponding main word selection signal and sub word selection signal are respectively supplied. , A plurality of sub-word driver circuits respectively connected to a plurality of word lines in a corresponding row, the sub-word driver circuit comprising: A first input terminal supplied with a selection signal, a second input terminal supplied with the sub-word selection signal, an output terminal connected to a word line and a gate connected to the first input terminal, One of a source or drain electrode is connected to the second input terminal and the other of the source or drain electrode is connected to the output terminal, and a P-channel type first transistor, and a gate is connected to the first input terminal. An N-channel type second transistor connected to the output terminal, the source or drain electrode being connected to the first power source, and the source or drain electrode being connected to the output terminal. The selection signal has a first potential necessary to turn on the second transistor in a non-selected state, and has a second potential lower than the first power source in the selected state, The word selection signal has a third potential that is the potential when the word line is in the selected state in the selected state, and has a fourth potential that is lower than the potential of the first power supply in the non-selected state. Characteristic memory circuit. 12. The memory circuit according to claim 11, wherein the second potential is a substrate bias potential generated in the memory circuit. 13. The memory circuit according to claim 11, wherein the fourth potential is a substrate bias potential generated in the memory circuit. 14. A memory circuit supplied with a first power supply at a ground level and a second power supply at a higher level, the memory circuit being arranged over a plurality of rows and divided into a plurality of rows for each row. A selected word line, a plurality of bit lines that intersect the word line, a plurality of memory cells provided at the intersection of the word line and the bit line, and a first address group that is decoded to make a first selection. A first word decoder that outputs a signal, a second word decoder that decodes a second address group and outputs a second selection signal, and the corresponding first selection signal and second selection signal are A plurality of word driver circuits respectively supplied to and connected to a plurality of word lines in a corresponding row, wherein the sub-word driver circuit includes a complementary MOS transistor circuit, The selection signal is one of the first potential of the second power supply and the second potential lower than the first power supply according to the selection / non-selection state, and the second selection signal is One of a third potential which is the potential when the word line is brought into a selected state according to a non-selected state and a fourth potential which is equal to or lower than the potential of the first power source is set. Memory circuit.