JPH09181084A - Manufacturing method of bipolar transistor - Google Patents

Abstract

(57) An object of the present invention is to reliably connect a base active region and a graft base region which is a base extraction region. SOLUTION: A base lead-out electrode 26, which is a diffusion source of impurities forming a second impurity type first impurity region, is selectively formed on a first conductive type first semiconductor region 23, and a base lead-out electrode is formed. 26. In a method of manufacturing a bipolar transistor in which a first impurity region of the second conductivity type is formed by diffusing impurities from 26, a step of forming a base active region and a ground base region connected to the base extraction electrode 26 in the substrate 21. 55, and a step of forming a region connecting the base active region and the ground base region 55 by ion implantation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor in which a base lead electrode serving as a diffusion source of a second conductivity type first impurity region is selectively formed on a first conductivity type semiconductor region. .

[0002]

2. Description of the Related Art As a high speed and low power consumption bipolar transistor, for example, a structure shown in FIG. 6 is known. In FIG. 6, for example, an n-type semiconductor layer is provided on the p-type semiconductor substrate 1 by, for example, epitaxial growth, and the n-type semiconductor layer is formed by element isolation regions 2 such as silicon oxide into several island-shaped regions, for example, regions 3. Etc. A p-type base region 4 is formed facing the surface of the n-type semiconductor layer of the island-shaped region 3, and an n ⁺ -type emitter region 5 is formed in the base region 4. The base region 4 is composed of a base active region 4i which substantially functions as an original base in the central portion, and a high concentration so-called graft base region 4g for taking out the base electrode. The graft base region 4g is formed by p-type impurity diffusion from the base extraction electrode 6 of the p ⁺ -type polycrystalline silicon layer, and the base active region 4i is formed by p-type impurity implantation using the base extraction electrode 6 as a mask. The emitter region 5 uses the insulating layer 8 formed on at least the sidewall of the base extraction electrode 6 as a mask, and introduces n-type impurities from the n ⁺ -type polycrystalline silicon layer 7 for extracting the emitter formed on the insulation layer 8. Is formed by.
Further, the base take-out electrode 6 has an aluminum (A
l) and the like, and an emitter electrode 9E is connected to the n ⁺ type polycrystalline silicon layer 7, respectively.
In the example of FIG. 6, the electric collector electrode 9C via a relative island region 3 of the n-type epitaxial layer serving as a collector region, n ⁺ -type buried layer 11 and n ⁺ -type electrode extraction region 12 of the Connected to each other.

According to the so-called graft base type bipolar transistor having such a structure, it is possible to simplify the process by self-aligning the emitter and the base, reduce the parasitic capacitance, miniaturize the emitter width, and so-called shallow junction. Can be achieved.

However, in order to achieve higher speed, lower power consumption, and higher integration of the bipolar transistor, further reduction in the vertical direction (the substrate thickness direction), that is, so-called shallow junction, is required. It is required to reduce the base travel time τ _B by reducing the height. Here, the base transit time t _B is generally t _B = W _B ² / 2D _N (W _B ² ... Base width, _DN ... Electron diffusion constant), and the base junction depth is reduced. By doing so, high performance can be achieved.

By the way, as a technique for making the base junction depth shallower and making the base width narrower, conventionally, base impurities are ion-implanted with low energy through a buffer oxide film and annealed at a low temperature. Techniques and techniques for introducing base impurities into polycrystalline silicon and diffusing at low temperature are known. Among them, a technique of introducing a base impurity into polycrystalline silicon and diffusing it at a low temperature has been widely used to prevent so-called accelerated diffusion, channeling tail, and the like caused by damage due to ion implantation.

[0006]

However, when a technique of introducing a base impurity into polycrystalline silicon and diffusing it at a low temperature is applied to a so-called graft base transistor, the base active region and the graft base region are divided into two regions. There is a possibility that inconveniences as shown in FIGS. 7 and 8 may occur in connection between the two.

That is, the graft base region 4g which is the base extraction region is formed by diffusion from the p ⁺ type polycrystalline silicon 6 which becomes the base extraction electrode, and the base active region 4i is the emitter extraction polycrystalline silicon 7.
Formed by diffusion from the
Alternatively, since the insulating oxide film 8 for separating the emitter and the base is present on the side wall of the base take-out electrode with a thickness of, for example, about 0.3 μm, when the diffusion is insufficient, as shown in FIG. There may be a gap between the region 4i and the graft base region 4g, which may prevent effective connection. Also,
If the diffusion is performed sufficiently, the base width is narrow, about 0.1 μm or less, so that the p ⁺ impurity in the graft base region 4g collides with the n ⁺ impurity in the emitter region 5 as shown in FIG. , The breakdown voltage of the emitter-base junction is deteriorated, the matching characteristic of the base-emitter voltage V _BE is deteriorated, and the operating frequency or the cutoff frequency f _T is lowered.

The present invention has been made to solve the above-mentioned problems and has a shallow base junction, that is,
An object of the present invention is to provide a method for manufacturing a bipolar transistor which can surely connect between a base active region and a graft base region which is a base extraction region while forming a shallow junction.

[0009]

In order to solve the above-mentioned problems, the present invention provides an impurity for forming a first impurity region of a second conductivity type on a first semiconductor region of a first conductivity type. A base extraction electrode serving as a diffusion source is selectively formed, and impurity diffusion from the base extraction electrode causes diffusion of the second electrode.
In a method of manufacturing a bipolar transistor for forming a conductivity type first impurity region, a step of forming a base active region, a step of forming a ground base region connected to a base extraction electrode in a substrate, and the base active region And a step of forming a region connecting the ground base region by ion implantation.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A method for manufacturing a bipolar transistor according to the present invention will be specifically described below.

The example described below NPs the method of the present invention.
This is applied to a method for manufacturing an N-type bipolar transistor.

This method forms a graft base region by diffusion from a polycrystalline silicon layer containing impurities,
This is a method of manufacturing a bipolar transistor having a structure having a connection low-concentration impurity region for connecting a so-called intrinsic base region, which is a base active region, and a graft base region. Then, a method of exposing the region forming the low-concentration impurity region for connection by solution etching with KOH or the like and at the same time leaving the protective film in the active region.

The method according to the present invention will be described below in the order of steps with reference to FIGS.

Note that, in FIGS. 2 to 5, for simplification, only the area within the broken line in FIG. 1 is shown enlarged.

(A) In order to manufacture a bipolar transistor by the method of the present invention, first, as shown in FIG.
For example, an N ⁺ type buried layer 22 is formed on a P type semiconductor substrate 21.
And an element isolation region 24 is formed on the N-type epitaxial layer laminated thereon by selective oxidation, a trench or the like to form an island region 23 as a first conductivity type (N-type) semiconductor region.

Subsequently, a polycrystalline silicon layer (DOPOS) containing impurities is deposited and patterned to form a base extraction electrode 26, which serves as a diffusion source of the first impurity region of the second conductivity type (P type). An insulating film 27 made of silicon oxide or the like is deposited on the region 23.

Next, the base take-out electrode 26 and the insulating film 27 are selectively opened on the island-shaped region 23 to form an opening 28 exposing the island-shaped region 23. A channel formation blocking region 25 is formed under a part of the element isolation region 24, and a part of the buried layer 22 is connected to the collector extraction region 23C.

(B) Then, as shown in FIG. 2, the buffer oxide film 51 is formed by oxidizing the surface of the opening end portion of the base extraction electrode 26, which is a semiconductor region facing the opening 28, and the exposed island region 23. Form. This buffer oxide film 51
Has a thickness of, for example, about 300 and is formed by thermal oxidation of the surface.

Next, a polycrystalline silicon layer 52 for selective etching is formed on the buffer oxide film 51 and the insulating film 27 formed in the opening 28. The film thickness of the polycrystalline silicon layer 52 for selective etching is, for example, about 1000 and is formed into a thin film with good coverage by so-called TEOS or low pressure CVD. As will be described later, this selective etching polycrystalline silicon layer 52 is selectively etched due to the difference in impurity concentration, and will be used as a mask when forming a low concentration impurity region for connection.

[0020] Subsequently, the entire surface CVDS _i O ₂ film is formed, the CVDS _i O ₂ film through the polycrystalline silicon layer 52 for selectively etching the sidewalls of the etch-back opening portion 28 ion implantation mask 53 Is formed. Then
The polycrystalline silicon layer 52 for selective etching is the insulating film 27.
Only the active regions on the top and the bottom of the opening 28 are exposed. Here, the film thickness of the CVDS _i O ₂ film determines the size of the ion implantation mask portion 53, and the size of the ion implantation mask portion 53 controls the size of the connection low-concentration impurity region described later. Therefore CVDS _i O
The reproducibility of the bipolar transistor manufactured by controlling the film thickness of the _two films can be improved. Note that the polycrystalline silicon layer 52 for selective etching is not limited to be formed by using the CVDS _i O ₂ film, and a silicon nitride film can be used.

Then, ion implantation is performed on the entire surface. The dopant for this ion implantation is B ⁺ or BF ₂ ⁺ , and is not limited to this, and N (nitrogen), As (arsenic), P
(Phosphorus) or the like can also be used. By such ion implantation, impurities are selectively introduced into the upper portion of the insulating film 27 of the polycrystalline silicon layer 52 for selective etching and the upper portion of the active region at the bottom of the opening 28, and the opening masked by the ion implantation mask portion 53 is formed. Impurities are not introduced into the polycrystalline silicon layer 52 for selective etching in the side wall portion of the portion 28 and the portion immediately below the ion implantation mask portion 53.

(C) Next, the ion implantation mask portion 53 formed of the CVDS _i O ₂ film is removed and the polycrystalline silicon layer 52 for selective etching is exposed entirely.

Then, the polycrystalline silicon layer 52 for selective etching is selectively removed by solution etching using KOH or the like by utilizing the difference in the concentration of impurities in the ion implantation. That is, since the impurity concentration is high in the upper part of the insulating film 27 of the polycrystalline silicon layer 52 for selective etching and in the upper part of the active region at the bottom of the opening 28,
The etching rate becomes low in solution etching with KOH or the like. On the other hand, no impurities are introduced into the polycrystalline silicon layer 52 for selective etching in the side wall of the opening 28 or in the portion immediately below the ion implantation mask 53, so that KO
The etching rate becomes higher in the solution etching of H or the like. Therefore, the polycrystalline silicon layer 52 for selective etching is selectively removed due to the difference in impurity concentration.

Next, as shown in FIG. 3, B ⁺ and B are formed on the entire surface.
Ion implantation using F ₂ ⁺ is performed. This ion implantation is performed using the selective etching polycrystalline silicon layer 52, which has been selectively etched, as a mask to open the opening 28.
Impurities are introduced into the island region 23 only in the vicinity of the side wall.
That is, no impurities are introduced into the lower portion of the polycrystalline silicon layer 52 for selective etching which remains at the bottom of the opening 28, and the active region remains the first conductivity type (N type).

(D) Next, all of the selectively remaining polycrystalline silicon layer 52 for selective etching is removed, and subsequently,
As shown in FIG. 4, CVDS _i is formed on the entire surface including the opening 28.
The O ₂ film 54 is formed with a thickness of about 4000, for example. The CVDS _i O ₂ film 54 is used as a cap for the next anneal, further also be used to form the side wall portion for forming a base active region and the emitter region in self-alignment.

Next, as shown in FIG. 4, annealing is performed to form a graft base region 55, which is a first impurity region of the second conductivity type, by diffusion of impurities from the base extraction electrode 26, and at the same time, grafting is performed. The active low-concentration impurity region 56, which is the second impurity region of the second conductivity type and is in contact with the base region 55, is covered with the polycrystalline silicon layer 52 for selective etching at the bottom of the opening 28. Except for the region, the ion-implanted P-type impurities are activated and formed.

(E) Next, as shown in FIG.
_{The iO 2} film 54 is etched back by anisotropic etching to form a sidewall part 57 on the sidewall of the opening 28. After forming the sidewall portion 57, 10
A polycrystalline silicon layer 58 having a thin film thickness of about 00 is formed. Then, an impurity for forming a base active region is introduced into this thin polycrystalline silicon layer 58 to form a base active region which is a third impurity region of the second conductivity type.

Hereinafter, an emitter region, which is a second impurity region of the first conductivity type, is formed in the third impurity region of the second conductivity type.
For example, a required bipolar transistor formed by self-alignment is manufactured.

In the method of manufacturing a bipolar transistor according to the present invention having such a manufacturing method, since the connection low-concentration impurity region 56 is formed as described above, the connection between the graft base region 55 and the base active region is made. The low-concentration impurity region 56 for connection which can be made reliable
The withstand voltage can be improved by the impurity concentration of
The parasitic capacitance can also be reduced.

Further, depending on the manufacturing method of the bipolar transistor according to the present invention, the size of the ion implantation mask portion 53 can determine the size of the selectively removed portion of the polycrystalline silicon layer 52 for selective etching. The size of the region of the connection low-concentration impurity region 56 into which impurities are introduced by implantation can be reliably controlled.

Further, the active region is protected by the polycrystalline silicon layer 52 for selective etching, which is partially left after the ion implantation as described above, so that unnecessary impurities are prevented from being introduced and the base region is easily formed. The junction depth can be made shallow.

In the above example, the NPN type bipolar transistor has been described, but the PNP type may be used. Various changes can be made without departing from the spirit of the present invention.

[0033]

According to the method of manufacturing the bipolar transistor of the present invention, the second impurity region of the second conductivity type is formed, and the third impurity region is formed in contact with the second impurity region, thereby activating the active region. The connection between the third impurity region formed in the region and the base extraction region is surely performed. Further, by forming the second impurity region of the second conductivity type excluding the active region, it is possible to accurately control the base junction depth and the like.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of forming a base extraction electrode in a semiconductor region of a first conductivity type.

FIG. 2 is a cross-sectional view showing a step of forming an ion implantation mask portion on a side wall of an opening.

FIG. 3 is a cross-sectional view showing a step of performing ion implantation using the polycrystalline silicon layer as a mask.

FIG. 4 is a cross-sectional view showing a step of performing annealing.

FIG. 5 is a cross-sectional view showing a step of forming a polycrystalline silicon layer after forming a sidewall portion of an opening.

FIG. 6 is a sectional view showing a conventional bipolar transistor.

FIG. 7 is a cross-sectional view illustrating a problem of a conventional bipolar transistor.

FIG. 8 is a cross-sectional view illustrating a problem of a conventional bipolar transistor.

[Explanation of symbols]

23 island region, 26 base extraction electrode,
28 openings, 52 polycrystalline silicon layer for selective etching, 53 ion implantation mask part.

Claims (1)

[Claims] 1. A second semiconductor is formed on the first semiconductor region of the first conductivity type.
A base extraction electrode serving as a diffusion source of impurities forming a conductivity type first impurity region is selectively formed, and the second conductivity type first impurity region is formed by impurity diffusion from the base extraction electrode. In the method of manufacturing a bipolar transistor, a step of forming a base active region, a step of forming a ground base region connected to a base extraction electrode in a substrate, and a region connecting the base active region and the ground base region And a step of forming by implantation.