JPH09181590A - Logic circuit and data processing device using the same - Google Patents

Abstract

(57) Abstract: In a redundant system using two equivalent logic LSIs as a master and a checker, not only the occurrence of a failure but also the name of a signal line whose signal values do not match can be identified. To provide a logic LSI that facilitates failure diagnosis. A master LSI 11 outputs a signal sequence of a processing result to a pin 1
Output from 12. The processing result is also input to the checker LSI 12 through the pin 122. The comparator 26 determines the matching between the processing result of the logic circuit 24 and the processing result of the master LSI 11 for each signal, and outputs the result to the storage circuit 14. Memory circuit
14 captures and holds this comparison result. When the comparator 26 finds even a part of the mismatch, it notifies the storage circuit 14 of that fact. It also informs the outside through the pin 123. The memory circuit 14 continues to hold the comparison result (match / mismatch) for each signal line when the mismatch occurs. The contents of the memory circuit 14 are observed through the pin 124.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit suitable for a redundant system using two logic circuits as a master and a checker, and a data processor using the logic circuit.

[0002]

2. Description of the Related Art Conventionally, as a redundant system using two equivalent logic LSIs as a master and a checker, I Triple E Micro Vol. 4 (1984) No. 34.
Pages 43 to 43 (IEEE MICRO, Vol.4 (1984) PP.
34-43). This conventional example will be described with reference to FIG. FIG. 19 shows the functional redundancy check (Functional redundancy check) published on page 37 of the above document.
is a circuit that realizes checking). In FIG. 19, reference numerals 21 and 22 denote a logical LSI, reference numeral 2
3 and 24 are attached to the logic circuit section, reference numerals 25 and 2
A reference numeral 6 indicates a comparison circuit, and reference numerals 27 and 28 indicate tristate gate strings.

Here, the logic LSI 21 is the master, and the logic L
In order to operate the SI 22 as a checker, the control signal 272 to the tri-state gate row 27 is set to “H” and the control signal 282 to the tri-state gate row 28 is set to “L” through the external input pin or the internal register. Be present.

The master LSI 21 includes an external input pin group 21.
The signal supplied from 1 is processed, and the signal sequence of the processing result is output from the external input / output pin group 212 via the tristate gate array 27.

On the other hand, the checker LSI 22 processes the signals supplied from the external input pin group 221 at the same timing as the master LSI 21. Then, the signal sequence of the processing result and the master LS input from the external input / output pin group 222 are input.
The comparison circuit 26 compares the signal sequence of the processing result of I21. As a result of this comparison, an "L" signal is output from the external output pin 223 when all the signals match, and an "H" signal when one or more signals do not match. Therefore, by monitoring the output from the external output pin 223, the occurrence of a failure can be detected.

[0006]

The above-mentioned prior art is effective for detecting the occurrence of a failure. However, there is a problem that the cause of the failure cannot be determined because it is not known which signal caused the mismatch.

It is an object of the present invention to provide a logic circuit which can easily detect not only the occurrence of a failure but also which signal causes a mismatch, and a data processing device using the same. And

[0008]

According to the present invention, there is provided a storage means for storing information capable of identifying a signal line in which a mismatch has occurred (further, the signal series itself), and a means for notifying the contents of the storage means to the outside. This achieved the above objective. In this case, when the signal series itself is stored, not only the signal line name in which the mismatch has occurred but also the signal value can be known. If the signal sequence immediately before the occurrence of the failure is known, it may be effective for diagnosis of the failure. Therefore, in addition to the signal sequence at the time when the mismatch occurs, the signal sequence before the mismatch occurs is stored.

The present invention will be described more specifically and in detail below.

According to a first aspect of the present invention, a data sequence is received, a separately determined arithmetic processing is performed on the input data, and a signal sequence indicating the result of the arithmetic operation (hereinafter referred to as "own system signal sequence"). A logic section for outputting a predetermined signal sequence, and comparing the input signal sequence (hereinafter referred to as "other system signal sequence") with the self system signal sequence, A comparison unit that outputs a comparison result for each signal that forms a signal sequence that has become a signal sequence that is included in the signal sequence that is the target of the comparison when the comparison unit detects a mismatch And a storage unit that stores the comparison result of 1. and outputs the comparison result to the outside.

In a second aspect of the present invention, a data input is accepted, a separately-specified arithmetic processing is performed on the input data, and a signal sequence indicating the result of the arithmetic operation (hereinafter referred to as "self-system signal sequence"). A) logic unit for outputting a signal sequence, and receiving an input of a signal sequence, comparing the input signal sequence (hereinafter referred to as “other system signal sequence”) and the self system signal sequence,
A comparison unit that outputs a comparison result for each signal that forms the signal sequence that was the target of the comparison, and the signal sequence that is the target of the comparison when the comparison unit detects a mismatch The comparison result for each signal constituting the, the own system signal sequence that has been the target of the comparison when the comparison unit detects a mismatch, and the comparison target when the comparison unit detects a mismatch And a storage means for storing at least two of the other-system signal sequences that have been described above and outputting the same to the outside.

According to a third aspect of the present invention, an input of data is accepted, a separately-specified arithmetic processing is performed on the input data, and a signal series indicating the result of the operation (hereinafter referred to as "self-system signal series"). , Which receives an input of a signal sequence, compares the input signal sequence (hereinafter referred to as “other system signal sequence”) with the self system signal sequence,
A comparison unit that outputs a comparison result for each signal that forms the signal sequence that was the target of the comparison, and the signal sequence that is the target of the comparison when the comparison unit detects a mismatch The above-mentioned comparison result for each signal constituting the, and the above-mentioned own-system signal sequence that was the subject of the comparison when the above-mentioned comparison unit detects a mismatch and the above-mentioned own-system signal sequence before that, and the above-mentioned comparison unit does not match A storage means for storing at least two of the other-system signal series that has been the target of the comparison and the other-system signal series before that, and outputting this to the outside. A logic circuit characterized by the above is provided.

In the above first, second and third modes,
Further, the following configuration may be provided. In other words, the comparison section may output a mismatch detection signal indicating that any one of the signals forming the signal sequence detects a mismatch.

The logic unit may be configured to be able to output the calculation result to the outside.

Further, a terminal for inputting / outputting a signal, a master mode as an operation mode for outputting the operation result of the logic section to the outside through the terminal, and an output of the operation result to the outside through the terminal. And a checker mode that suppresses the signal sequence input through the terminal as the other system signal sequence and inputs the comparison circuit to the comparison circuit, and sets the operation mode to the master mode and the checker mode according to a mode designation signal separately input. It may have a mode control means set to either.

The operations of the first, second and third modes will be described collectively.

The logic unit performs a separately determined arithmetic processing on the input data and outputs a signal sequence indicating the arithmetic result (in some cases, the arithmetic result may be output as it is to the outside. ). The comparison unit compares the signal series (self-system signal series) indicating the calculation result with the separately-received other-system signal series. Then, the comparison result for each signal forming the signal sequence is output. Note that, in addition to this, the comparison unit may output a mismatch detection signal indicating that any one of the signals forming the signal sequence detects a mismatch.

The storage means detects the comparison result for each signal at the time when the non-coincidence is detected, the self-system signal sequence in which the non-coincidence is detected (further, the self-system signal sequence before that), and the non-coincidence is detected. At least two of the other-system signal series (and further other-system signal series before that) are stored and output to the outside. However, only the comparison result for each signal at the time when the mismatch is detected may be stored alone. Failure can be diagnosed by observing this output signal.

In the case of a configuration having a plurality of operation modes, the mode control means sets the operation mode to either the master mode or the checker mode according to the mode designation signal. In the master mode, the operation result of the logic section is output to the outside through the terminal. In checker mode,
The output of the calculation result through the terminal is suppressed and the signal series input through the terminal is input to the comparison circuit as the comparison target signal series. By doing so, one logic circuit can be used separately for the master and the checker.

According to a fourth aspect of the present invention, the above-mentioned two logic circuits and a mode designating signal designating an operation mode of the logic circuit are generated, and one of the logic circuits is set to a master mode and the other is designated. A mode setting means for setting the checker mode, a first bus signal line for inputting the data to both the logic circuits, an input means for supplying a signal to the first bus signal line, and a master mode. A second bus signal line for inputting the operation result output from the set logic circuit to the logic circuit set to the checker mode; and an observing means for observing the state of the second bus signal line. A data processing system having the above is provided.

According to a fifth aspect of the present invention, a first input terminal to which data is input, a second input terminal to which a predetermined signal series (hereinafter referred to as "other system signal series") is input,
Operation comparison for performing predetermined arithmetic processing on the data input through the first input terminal and comparing the signal series of the arithmetic processing result (hereinafter referred to as "self system signal series") with the other system signal series. Means for outputting a comparison result for each signal constituting the signal series for the signal series that was the object of the comparison when a mismatch is detected by the comparison by the operation comparing means.
And an output terminal of.

According to a sixth aspect of the present invention, a first input terminal to which data is input, a second input terminal to which a predetermined signal series (hereinafter referred to as "other system signal series") is input,
Operation comparison for performing predetermined arithmetic processing on the data input through the first input terminal and comparing the signal series of the arithmetic processing result (hereinafter referred to as "self system signal series") with the other system signal series. And a means for outputting the comparison result for each signal forming the signal series of the signal series that has been the object of the comparison when the operation comparing means detects a mismatch. In the case where the output terminal, the second output terminal for outputting the self-system signal sequence which is the object of the comparison when the operation comparing means detects a mismatch, and the operation comparing means detects a mismatch There is provided a logic circuit characterized by having at least two output terminals of the third output terminal for outputting the other-system signal series which has been the object of the comparison. That.

According to a seventh aspect of the present invention, a first input terminal to which data is input, a second input terminal to which a predetermined signal series (hereinafter referred to as "other system signal series") is input,
Operation comparison for performing predetermined arithmetic processing on the data input through the first input terminal and comparing the signal series of the arithmetic processing result (hereinafter referred to as "self-system signal series") with the other-system signal series. And a means for outputting the comparison result for each signal forming the signal series of the signal series that has been the object of the comparison when the operation comparing means detects a mismatch. An output terminal, a second output terminal for outputting the own-system signal series that has been the target of the comparison when the operation-comparison means detects a mismatch, and the own-system signal series before that; A third output terminal for outputting the other-system signal series that was the object of the comparison and the other-system signal series before that when the comparison unit detects a mismatch Having at least two output terminals, the logic circuit according to claim is provided of.

In the above fifth, sixth and seventh aspects,
You may further have the 4th output terminal from which the signal which shows that the said system signal series and the said other system signal series did not correspond is output.

The operation of the fifth, sixth and seventh modes will be described.

The calculation comparison means performs a predetermined calculation process on the data input through the first input terminal. Then, the signal series resulting from the arithmetic processing is compared with the signal series input through the second input terminal.

From the first output terminal, the comparison result for each signal forming the signal series in which the mismatch is detected is output.
From the second output terminal, the own system signal sequence in which the mismatch is detected (further, the own system signal sequence before that) is output. From the third output terminal, the other-system signal series in which the mismatch is detected (further, the other-system signal series before that) is output. A signal indicating that a mismatch has occurred is output from the fourth output terminal. Therefore, failure diagnosis can be performed by observing the signals output from these terminals.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG.

The present embodiment is a redundant system using two logic LSIs of the present invention.

This redundant system comprises a logic LSI 11 and a logic LSI 12.

The logic LSI 11 includes a logic circuit section 23, a comparison circuit 25, a tristate gate array 27, and a storage circuit 1.
3, an external input pin group 111, an external output pin group 112, an external output pin 123 ', and an external output pin group 124'.

Similarly, the logic LSI 12 includes the logic circuit unit 2
4, comparison circuit 26, tristate gate array 28, storage circuit 14, external input pin group 121, external output pin group 12
2, an external output pin 123, and an external output pin group 124.

The comparison circuits 25 and 26 are connected to the logic circuit section 23,
The signal sequence of the processing result by 24 and the input / output pin group 11
2, 122 and 122 are compared with the signal series input. Then, the comparison result (that is, whether there is any signal that does not match between both signal sequences)
Are output from the external output pins 123 and 123 '. Further, this comparison result is stored in the memory circuits 13 and 14.
Is also output. Further, the comparison result for each signal (or signal line) is output to the storage circuits 13 and 14.

The memory circuits 13 and 14 store the comparison result (match / mismatch) of each signal line by the comparator circuits 25 and 26 at the time when the mismatch occurs.
In addition, the stored comparison result (information indicating the position where the mismatch occurs) for each signal line is output to the external output pin groups 124, 1
The output is from 24 '.

The specific configurations of the comparison circuits 25 and 26 and the storage circuits 13 and 14 will be described later with reference to some examples (FIGS. 2, 4, and 6).

The external input / output pin groups 112 and 122 are for outputting the processing results by the logic circuit portions 23 and 24. However, in the checker mode described later, the signal series to be compared by the comparison circuits 25 and 26 are input from the external output pin groups 112 and 122.

The logic LSI 11 and the logic LSI 12 are arranged in parallel with each other. That is, the external input pin group 111 and the external input pin group 121 are connected to each other, and the same input data is input to both logic LSIs at the same timing. Also, the external input / output pin group 11
2 and the external input / output pin group 122 are connected. As a result, the result of the other logic LSI processing can be input as a signal series to be compared.

These logic LSIs 11 and 12 are provided with a master mode and a checker mode as their operation modes, and one of them is selected and used. The operation mode is set (selected) by inputting control signals 272, 2 to the tristate gate arrays 27, 28 through an external input pin (or an internal register) not shown.
82. Control signal 272,
When 282 is set to "H", the incoming logic LSI is set to the master mode, and the tristate gate arrays 27 and 28 output the processing results of the logic circuits 23 and 24 to the external input / output pins 112 and 12.
Output to the outside through 2. On the other hand, when set to "L", the checker mode is set, and the tri-state gate rows 27, 2
8 blocks the output of the processing result to the outside. As a result, in the checker mode, the external input / output pins 112,
Through 122, the above-mentioned signal sequence to be compared can be input. Details of the difference in processing operation in each operation mode will be described later.

The operation of this embodiment will be described below.

Here, the logic LSI 11 is operated in the master mode, while the logic LSI 12 is operated in the checker mode. That is, the control signal 272 is "H" and the control signal 282 is "L". Assuming that the operation mode is set in this way, the logic LSI 11 will be referred to as “master LSI 11” and the logic LSI 12 will be referred to as “checker LSI 12” hereinafter.

The logic circuit section 23 of the master LSI 11 processes the signals input from the external input pin group 111, and outputs the signal sequence of the processing result from the external input / output pin group 112 via the tristate gate array 27. To do.

The logic circuit section 24 of the checker LSI 12 is also
The signal input from the external input pin group 121 is used as the master LS.
Processing is performed at the same timing as I11, and the processing result is output to the comparison circuit 26. Furthermore, the checker LSI12 is
The signal series output from the external input pin group 111 by the master LSI 11 is received as an input signal through the external input pin group 122. In the checker LSI 12, the output of the logic circuit section 24 is blocked by the tri-state gate array 28, so the logic circuit section 24
The result of processing by is not output to the outside through the external output pin 122.

The comparison circuit 26 of the checker LSI 12 compares the signal series of the processing result of the master LSI 11 with the signal series of its own processing result. When all the signals match as a result of the comparison, the comparison circuit 26 outputs the “L” signal from the external output pin 123. On the contrary, when there is even one signal that does not match, the "H" signal is output to the external output pin 12
Output from 3. A signal having the same content as the signal output from the external output pin 123 is also input to the storage circuit 14. Further, the comparison circuit 26 outputs the comparison result for each signal line to the storage circuit 14.

When "H" is output from the external output pin 123 (that is, when there is a signal that does not match), the memory circuit 14 causes the comparison result (match / mismatch) for each signal output from the comparison circuit 26. ) Is stored. Then, the stored comparison result is output to the outside through the external output pin group 124. The storage operation in this case is performed in parallel for each signal in synchronization with the rising timing of the output signal of the comparison circuit 26.

An example of the comparison circuit 26 and the storage circuit 14 will be described with reference to FIG.

The circuit 2601 in FIG. 2 corresponds to the comparison circuit 26 in FIG. 1, and the circuit 1401 in FIG. 2 corresponds to the memory circuit 14 in FIG.

The circuit 2601 uses an exclusive OR (EOR).
Elements 301, 302, 303, 304, logical sum (OR)
It is composed of an element 305 and a storage element 306.

Exclusive OR (EOR) elements 301, 30
The processing result of the master LSI 11 and the processing result of the checker LSI 12 are input to 2, 303 and 304. Of these, the signal lines 3001, 3003, 3005
The signal series input through 3007 is the signal series of the processing result of the master LSI 11, which is input through the input / output pin group 122. On the other hand, the signal lines 3002 and 300
The signal sequence input through 4,3006,3008 is the signal sequence of the processing result by the logic circuit unit 24 of the checker LSI 12. Of course, the exclusive OR (EO
The signals input to the (R) elements 301, 302, 303, 304 are signals corresponding to each other in the signal sequence of the processing result.

The logical sum (OR) element 305 inputs the outputs of the exclusive logical sum (EOR) elements 301, 302, 303, 304.

The memory particle 306 takes in the signal input to the D terminal at the rising timing of the signal input to the C terminal and outputs it from the Q terminal. The output from the Q terminal is input to the circuit 1401. Further, it is output to the outside through the external output terminal 123 of FIG. The system clock is applied to the C terminal of the storage element 306.
The output of the logical sum (OR) element 305 is input to the D terminal.

The circuit 1401 includes storage elements 307 and 30.
It consists of 8,309,310. These are storage elements 30
This is the same element as 6. Storage elements 307, 308, 30
9, 310 are respectively associated with exclusive OR (EOR) elements 301-304 in a one-to-one correspondence. The outputs of the corresponding exclusive OR (EOR) elements 301 to 304 (this is the comparison result for each signal) are input to each D terminal. Further, an output from the Q terminal of the storage element 306 (this is a signal indicating whether or not there is any signal that does not match between both signal series) is input to these C terminals. The Q terminals of the storage elements 307 to 310 are connected to the external output pin group 124 in FIG.

The circuit 2601 shown in FIG. 2 (comparing circuit 2
6) and the operation of the circuit 1401 (memory circuit 14) will be described with reference to the time chart of FIG.

Here, it is assumed that the signal on the signal line 3001 and the signal on the signal line 3002 do not match.

When the signal on the signal line 3001 and the signal on the signal line 3002 do not match (41), the EOR element 3
The output of 01 rises from "L" to "H" (43), OR
The output of the element 305 also rises from "L" to "H". In the storage element 306, the output of the OR element 305 is from "L" to "H".
The "H" signal output from the OR element 305 is stored at the next rising timing of the system clock (44). Then, the signal is directly output to the circuit 1401 or the like. The output is a signal indicating whether or not a mismatch has occurred. The memory element 306 is used to remove the dynamic hazard (in FIG. 3, the part denoted by reference numeral 42).

Storage elements 307, 308, 309, 310
Are EOR elements 301, 302, 303, 3 at the timing of the rising edge (44) of the output of the storage element 306, respectively.
The output signal of 04 is stored. Here, the storage element 307
"H" signal is applied to the other storage elements 308, 309, 31.
“L” is stored in 0. Therefore, if the signals output from the external output pin group 124 are observed,
In which signal line the signals did not match (here, the signal on the signal line 3001 and the signal on the signal line 3002)
Can find out that there was a disagreement.

Another configuration example of the memory circuit 14 (circuit 140
2) will be described with reference to FIG.

The circuit 1402 includes storage elements 507 and 50.
8, 509, 510, 511, AND (AND) element 5
It consists of 12.

The storage element 3 is connected to the D terminal of the storage element 511.
The negative output of 06 is input. Further, the system clock is input to the C terminal.

The output of the storage element 306 and the output of the storage element 511 are input to the logical product (AND) element 512.

Storage elements 507, 508, 509, 510
Are respectively associated with the exclusive OR (EOR) elements 301, 302, 303, 304 in a one-to-one correspondence relationship. The outputs of the corresponding exclusive OR (EOR) elements 301 to 304 (this is the comparison result for each signal) are input to each D terminal. Further, the logical product (AND) element 512 is connected to these C terminals.
Output is input. Q of storage elements 507 to 510
The terminals are connected to the external output pin group 124 in FIG.

Storage elements 507, 508, 509, 510
Is a level sensitive type storage element, not an edge trigger type. Since the circuit of the level-sensitive type storage element is simple, the circuit scale can be reduced accordingly.

The operation of the circuit 1402 (memory circuit 14) will be described with reference to the time chart of FIG.

Here, the case where the signal on the signal line 3001 and the signal on the signal line 3002 do not match is taken as an example.

The process up to the output of the storage element 306 is the same as in the example of FIG.

The storage element 511 stores the negative output of the storage element 306 at the falling timing of the system clock input to the C terminal. Then, the stored negative output is output as it is (61). AND element 512
Is a pulse signal (6 with a 1-clock width obtained by performing a logical product of the output of the storage element 306 and the output of the storage element 511.
2) is generated.

Storage elements 507, 508, 509, 510
When the pulse signal (62) is input, the output signals of the EOR elements 301, 302, 303, 304 are stored, respectively. Here, the storage element 507 receives the “H” signal, and the storage elements 507, 508, 509, and 510.
The "L" signal is stored in. Therefore, when observing the signals output from the external output pin group 124, which signal line does not match the signal (here, the signal on the signal line 3001 and the signal on the signal line 3002) do not match. I can know that.

Still another example of the memory circuit 14 (circuit 140
3) will be described with reference to FIG.

If this circuit 1403 is used, the external output pin group 124 is required to have only one pin. The comparison circuit 26 used in combination with the circuit 1403 is the circuit 260 shown in FIG.
1 is fine.

The circuit 1403 includes storage elements 71, 72, 7
It consists of 3,74.

The storage element 71 does not have an access terminal for scanning operation.

The storage elements 72, 73 and 74 are provided with a C terminal and a D terminal.
In addition to the terminals and Q terminals, access terminals (SD terminals, SC terminals) for scan operation are provided. Storage element 72,
To the SC terminals of 73 and 74, through the signal line 7006,
Timing signal for scan operation (scan clock)
Is supplied. The SD terminals are connected to the Q terminals of other storage elements. That is, the storage element 7
The SD terminal of 2 is connected to the Q terminal of the storage element 71. The SD terminal of the storage element 73 is connected to the Q terminal of the storage element 72. Furthermore, the SD of the storage element 74
The terminal is connected to the Q terminal of the storage element 73. The Q terminal of the storage element 74 is connected to the external output pin 124 in FIG. 1 through the signal line 7007.

Signal lines 7001, 7002, 7003, 7
004 is the EOR element 301 in FIG.
It is connected to the output lines 302, 303, 304. The signal line 7005 is connected to the Q terminal of the memory element 306.

The operation of the circuit 1403 will be described.

In FIG. 6, when a mismatch occurs in any of the signals, the storage elements 71, 72, 73, 74.
Stores the outputs of the EOR elements 301, 302, 303, 304, as in the above-described example. However, in this example, in order to externally observe the information (comparison result for each signal) stored in the storage elements 71, 72, 73, 74, the circuit 1
The 403 is operated as follows.

During the actual operation, the scan clock is fixed at "L". When it is confirmed that a failure has occurred based on the signal output from the external output pin 123, the external LSI
A scan clock is input from the signal line 7006 through the signal line 7006. Then, in synchronization with this scan clock, the contents of the storage elements 71, 72, 73 are respectively stored in the storage element 7
It will be sequentially shifted to 2, 73, 74. Therefore, if the signal of the external output pin 124 is strobed in synchronization with the scan clock application timing, the storage elements 71, 7
Information stored in 2, 73, 74 can be observed.

The example of FIG. 6 employs the shift scan configuration. However, the scan configuration is not limited to this. For example, a random access scan (address scan) configuration may be used.

The logic LSI of this embodiment outputs a comparison result (match / mismatch) for each signal (signal line). However, it is not always necessary to output comparison results for all signals (signal lines). It is also possible to output only the information (for example, the signal line number) indicating the signal (signal line) in which the mismatch has occurred.
This can be easily done by providing a circuit for examining the contents of the memory circuit 14.

The logic LSI of this embodiment stores the comparison result when a mismatch occurs and can output only this comparison result to the outside. However, the comparison result for each signal line by the comparison circuit 26 may be always output to the outside. In this case, the storage circuit for storing the comparison result may not be provided in the logic element.

A second embodiment of the present invention will be described with reference to FIG.

In this embodiment, in order to reduce the number of external output pins provided in the logic LSI, the external output pin (the external output pin 123 in FIG. 1) that outputs the occurrence of the mismatch and the external output that observes the information of the mismatch signal line. It is characterized in that the pin (the external output pin 124 in FIG. 1) is commonly used.

As shown in FIG. 7, the logic LSI 8 includes a selection circuit 81 in addition to the comparison circuit 26, the memory circuit 14 and the like. The logical LSI 8 constitutes a redundant system by being combined with a master as in the first embodiment, but the logical LSI used as a master is not shown in FIG. The same applies to the configuration diagrams of the other embodiments described below.

A signal for detecting the occurrence of mismatch is input to the selection circuit 81 from the comparison circuit 26. Further, the signal indicating the comparison result (match / mismatch) for each signal is
It is input from the signal line 7007 of 403. And
The selection circuit 81 selects either one of the two signals according to a separately input selection signal, and outputs the external output pin 80.
It is designed to output through 1.

The signal for designating the operation mode (master mode / checker mode) of this logic LSI is
It is also input to the selection circuit 81. A selection signal for switching the selection circuit 81 also serves as a signal designating this operation mode.

The selection circuit 81 causes the external output pin 801 to output a signal for detecting the occurrence of mismatch in the checker mode. On the other hand, in the master mode, a signal 7007 indicating information (comparison result for each signal) regarding the mismatch signal line is output from the external output pin 801 according to the scan clock.

As the comparison circuit 26, the circuit 2601 described with reference to FIG. 2 can be adopted. The circuit 1403 is as described with reference to FIG.

A third embodiment of the present invention will be described with reference to FIGS. 8 and 9.

This embodiment is characterized in that not only which signal (signal line) has a mismatch, but also the signal value of the signal (signal line) in which the mismatch has occurred can be known.

In order to realize this, the present embodiment has a configuration having a memory circuit 91 in addition to the configuration similar to that of the first embodiment (see FIG. 1).

The storage circuit 91 is arranged on the subsequent stage side of the logic circuit section 24, and the processing result output from the logic circuit section 24 is temporarily stored in the storage circuit 91 and then the tristate gate array 28. And to the comparison circuit 26. Further, the storage circuit 91 includes the comparison circuit 2
The comparison result in 6 (information indicating whether or not a mismatch occurs in any of the signal lines) is input through the signal line 94. Further, the system clock is input through the signal line 93. The storage circuit 91 continues to store the output of the logic circuit section 24 at the rising timing of the system clock as long as no mismatch occurs. However, when a mismatch occurs, the system clock is suppressed and a new signal is not stored. That is, the contents at the time when the mismatch occurs are retained.

The contents stored in the storage circuit 91 are transferred to the external input / output pin group 902 through the tristate gate 28.
It is possible to output from. The external input / output pin group 902
Like the external input / output pin group 122 described above, is also used to input the processing result of the master LSI.

A concrete example of the memory circuit 91 is shown in FIG.
01. The circuit 1001 includes a storage element 102,
It is composed of 103, 104 and 105 and an AND element 101. The signal line 1002 in FIG. 9 is connected to the signal line 92 in FIG. Similarly, the signal line 1003 is connected to the signal line 93, the signal line 1004 is connected to the signal line 94, and the signal line 100.
5 is connected to the signal line 95. Therefore, the processing result by the logic circuit section 24 is input to the D terminals of the respective storage elements 102, 103, 104, 105 through the signal line 1002. Further, the AND element 10 is connected to these C terminals.
The output signal of 1 is input. A system clock is input to the AND element 101 via a signal line 1003, and a signal indicating whether or not a mismatch occurs is input via a signal line 1004.

In FIG. 8, when a mismatch occurs, the signal on the signal line 94 rises from "L" to "H". Then
The output signal of the AND element 101 of the circuit 1001 is fixed to "L". As a result, the storage elements 102, 103, 10
Reference numerals 4 and 105 do not update the internal state, and continue to hold the processed signal sequence on the checker side when a mismatch occurs.

In order to confirm the processed signal sequence when the mismatch occurs, the operation mode of the logic LSI 9 is switched to the master mode. Then, the contents held in the memory circuit 91 can be observed through the external input / output pin group 902. On the other hand, the contents of the memory circuit 14 are the same as those of the other embodiments, except that the external output pin group 901 (the external output pin group 1 in FIG.
It corresponds to 24). Therefore, by collating the signal series output from the external output pin group 901 with the signal series observed from the external input / output pin group 902, the signal name and the signal value in which the mismatch occurs can be obtained. .

In this example, it is not necessary to add a new external pin in order to observe the processed signal sequence when a mismatch occurs.

The fourth embodiment will be described with reference to FIGS.

The logic LSI 1100 of this embodiment is the third
Similar to the embodiment described above, it is possible to obtain the presence / absence of a mismatch in any signal line, the comparison result (match / mismatch) for each signal line, and the signal value for each signal line.

The memory circuit 1101 stores a signal sequence (signal line) indicating which signal line the processing result of the checker LSI at the time when the processing result of the master LSI and that of the checker LSI do not match is detected. And the result of comparison for each). A signal indicating whether or not a mismatch has occurred in any of the signal lines and the comparison result for each signal line are input from the comparison circuit 26 to the storage circuit 1101. The processing result is directly input from the logic circuit section 24.

FIG. 11 shows an example of the memory circuit 1101.

The basic configuration of the memory circuit 1101 is almost the same as that of the circuit 1403 (see FIG. 6) described above. However,
In the storage circuit 1101, storage elements 1213 to 1208 to which an output signal of the comparison circuit 26 is input and storage elements 1201 to 1204 to which an output signal of the logic circuit portion 24 is input are provided as signals of data to be stored. is there.

In FIG. 11, signal lines 1209 and 121
0, 1211, 1212 propagate the output signal of the logic circuit section 24. Signal lines 1213, 1214, 1
Reference numerals 215 and 1216 propagate the EOR output signal (comparison result for each signal line) of the comparison circuit 26. Therefore, when a mismatch occurs, the storage elements 1201 and 120
2, 1203 and 1204 store the processed signal sequence on the checker side. On the other hand, storage elements 1205, 1206,
1207 and 1208 store the position information of the signal lines that have caused the mismatch (results of match / mismatch for each signal line).

The signal line 1217 propagates the output signal of the comparison circuit 26 (a signal indicating whether or not a mismatch has occurred in any signal line) which becomes "H" when a mismatch occurs. The signal line 1218 propagates a scan clock.

In this embodiment, by inputting the scan clock, the contents held in the memory elements 1201 to 1208 can be scanned out from the external output pin 1103 through the signal line 1219.

In the third embodiment (FIGS. 8 and 9) and the fourth embodiment (FIG. 10) described above, the processed signal sequence on the checker side and the position information of the mismatch signal line are stored. Was there. However, the signal sequence of the processing result on the master side and the position information of the mismatch signal line may be stored. Further, both the signal sequence of the processing result on the master side and the processed signal sequence on the checker side may be stored. Hereinafter, such an example is shown in FIG.
An extension example thereof will be further described with reference to FIGS. 15 and 16 in FIG.

FIG. 12 shows a logic LSI 130 for storing the processed signal sequence on the master side and the position information of the mismatch signal line.
This is an example of 0. The difference from the logic LSI 1100 of FIG. 10 is that some of the input signal lines of the memory circuit 1101 (the signal line 12
09-1212) is connected not to the output signal line of the logic circuit section 24 but to the external output pin group 1302 for propagating the processed signal sequence on the master side. As a result, the processing signal sequence on the master side is stored in the storage circuit 1101. Therefore, when the scan clock is input to the memory circuit 1101, the external output pin 1301
From (Note: this is connected to the signal line 1219), the comparison result for each signal line and the processed signal sequence on the master side are scanned out.

FIG. 13 shows a logic LSI 1 for storing both the processed signal series on the master side and the processed signal series on the checker side.
400 is an example.

The memory circuit 1411 is arranged on the preceding stage side of the comparison circuit 26, and the signal series 1413 of the processing result of the logic circuit section 24 and the signal of the processing result of the master side sent through the external input / output terminal 1412. The sequence 1414 and are input. The storage circuit 1411 stores the input signal series 1413 and outputs it to the comparison circuit 26 as a signal series 1417. Further, in parallel with this, the input signal series 1414 is stored and is output to the comparison circuit 26 as a signal series 1418.

The storage circuit 1411 is supplied with the comparison result by the comparison circuit 26 (whether or not any signal line has a mismatch) 1416. Memory circuit 1411
Stores the processing signal sequence 1413 on the checker side and the processing signal sequence 1414 on the master side at the timing of the rise of the system clock 1415 while the discrepancy does not occur, thereby continuously updating the stored contents. There is.
However, when a mismatch occurs, the update is stopped and the signal stored at that time is kept. The storage circuit 141
The contents stored in No. 1 can be scanned out through the external output terminal 1421.

An example of this memory circuit 1411 is shown in FIG. In FIG. 14, a memory circuit 1411 includes memory elements 1501, 1502, 1503, 1504, 1505.
It is composed of 1506, 1507, 1508 and an OR element 1509.

Storage elements 1502, 1503, 1504
1505, 1506, 1507 and 1508 are provided with scan operation access terminals SD and SC. The memory element 1501 may not include an access terminal for scan operation.

The signal line 1520 stores the timing signal (scan clock) for the scan operation in the storage elements 1502 to 1502.
It is for supplying to 1508.

The signal lines 1510 to 1513 store the processed signal sequence 1413 (see FIG. 13) on the checker side in the storage element 15.
It propagates to 01 to 1504.

The signal lines 1514 to 1517 pass the master side processed signal sequence 1414 (see FIG. 13) to the storage element 15
It propagates to 05-1508.

The signal line 1518 is connected to the system clock 14
15 is propagated to the OR element 1509.

The signal line 1519 propagates the output signal 1416 of the comparison circuit 26 to the OR element 1509. The output signal 1416 rises from "L" to "H" when a mismatch occurs.

The outputs from the Q terminals of the storage elements 1501 to 1508 are input to the comparison circuit 26 through the signal lines 1521 to 1528, respectively. Of these, outputs from the storage elements 1501 to 1504 (signal lines 1521 to 152
4) is the processing result on the checker side and corresponds to the output signal 1417 in FIG. Storage elements 1505 to 15
The output of 08 (signal lines 1525 to 1528) is the processing result on the master side and corresponds to the output signal 1418 in FIG.

When a mismatch occurs, the output signal 1416 is "L".
Rise to "H". Then, the system clock 141
5 is not applied to the storage elements 1501 to 1508. As a result, the storage circuit 1411 holds the checker side processed signal series and the master side processed signal series at the time of occurrence of the mismatch.

The scan line is used to observe the signal values on the signal line and the master side and the checker side which cause the mismatch. That is, the processed signal series on the checker side and the processed signal series on the master side when the mismatch occurs are scanned out from the signal line 1528. The signal line 1
The signal scanned out from 528 is output to the outside as the signal output 1421 in FIG.

A logic LSI 1800, which is an extension of the logic LSI 1400 (FIG. 13), will be described with reference to FIGS.

The logic LSI 1800 is not limited to the signal sequence (process signal sequence on the master side, process signal sequence on the checker side) at the time of occurrence of a mismatch, but also the signal sequence immediately before (process signal sequence on the master side, checker side). The processed signal sequence) is also stored.

The basic configuration of the logic LSI 1800 is almost the same as that of the logic LSI 1400 (FIG. 13). But,
The logic LSI 1800 includes a storage circuit 19 in the subsequent stage of the storage circuit 1401. The signal sequences 1417 and 1418 output from the storage circuit 1411 are input not only to the comparison circuit 26 but also to the storage circuit 19.

The memory circuit 19 is assumed to have the circuit configuration shown in FIG. 16, for example. The circuit configuration of FIG. 16 is almost the same as the circuit configuration of FIG. However, instead of the storage element 1501 in FIG. 14, a storage element 1901 having access terminals SD and SC for scan operation is adopted.

Signal lines 1510, 1511, 15 shown in FIG.
The signal input through 12, 1513 corresponds to the input signal 1417 to the memory circuit 19 in FIG. Signal lines 1514, 1515, 1516, 1517 of FIG.
Is the input signal 1418 to the memory circuit 19 in FIG.
Is equivalent to That is, the signal lines 1510 and 151 of FIG.
1,1512,1513,1514,1515,151
6, 1517 are signal lines 1521, 1522, and 1521 of FIG.
1523, 1524, 1525, 1526, 1527,
1528 is connected.

The signal input through the signal line 1910 in FIG. 16 is the input signal 1 to the memory circuit 19 in FIG.
Equivalent to 419.

That is, when the configuration of FIG. 14 is adopted as the memory circuit 1401, the signal line 1910 of FIG.
Are connected to the signal line 1528 of FIG.

The signal input through the signal line 1518 in FIG. 16 corresponds to the system clock 1415 in FIG. The signal input through the signal line 1519 in FIG. 16 corresponds to the mismatch detection signal 1416 in FIG.

The signal input through the signal line 1520 is the scan clock.

The comparison circuit 26 compares the signal series 1417 with the signal series 1418. When a mismatch is detected as a result of the comparison, the comparison circuit 26 causes the mismatch detection signal 1416.
To "H". Then, the logic element 15 of the memory circuit 19
09, the system clock 1415 is the storage element 190.
1, 1502 to 1508 are suppressed. As a result, the respective storage elements 1901, 1502-1508,
The acquisition of new signal sequences 1417 and 1418 is stopped. Similarly, the logic element 1509 of the memory circuit 1411
Also, the system clock 1415 causes the storage elements 1501-1 to 150-1.
The input to 508 is suppressed. As a result, each of the storage elements 1501 to 1508 has the signal sequences 1413 and 1414.
Stop importing new. As a result of the above operation, the storage circuit 1411 holds the signal sequence on the master side and the checker side at the time when the mismatch occurs, and the storage circuit 1
9 holds the signal sequence on the master side and the checker side one cycle before the mismatch occurs.

To observe the information stored in the memory circuits 1411 and 19, a scan clock is input to the memory circuits 1411 and 19 through the signal line 1520. Then, the storage elements 1901, 1502
The values stored in 1508 are sequentially output through the signal line 1528. This output signal corresponds to the signal output from the external signal line 181 in FIG. Also,
In parallel with this, the values stored in the memory circuit 1411 are also sequentially output through the signal line 1528 in FIG. The signal line 1528 of the memory circuit 1411 (see FIG. 14)
Is connected to the signal line 1910 of the memory circuit 19, this signal scanned out from the memory element 1411 is directly transmitted through the signal line 1910 to the memory element 1911.
Is input to the memory element 1910 of. Then, the contents stored in the storage element 19 are the signal line 1 of the storage element 19.
After being scanned out from 528, the contents stored in the memory element 1411 are also shown in the signal line 152 in FIG.
It is sequentially output through 8.

The output signal line 192 of the memory circuit 19
By connecting a storage circuit similar to the storage circuit 19 to 1,1522 to 1528, it is possible to hold the previous processing result.

According to this embodiment, even if an address mismatch occurs while incrementing the address, the faulty LSI can be specified.

The fifth embodiment of the present invention will be described with reference to FIG.

In the present embodiment, not only the mismatch signal position information when a mismatch has occurred is stored in the memory circuit 14, but also the checker side LS at the time of the mismatch and immediately before the mismatch occurs.
The processed signal sequences of I are stored in the storage circuits 1601 and 1 respectively.
It is characterized in that it is stored in 602.

Storage circuit 1601 and storage circuit 1602
Can be configured by using, for example, the circuit 1001 shown in FIG. In this case, the signal input through the signal line 1003 in FIG.
01, 1602 input to system clock 1603
Is equivalent to A signal input through the signal line 1004 in FIG. 9 corresponds to the input signal 1604 to the memory circuits 1601 and 1602. Similarly, the signal input through the signal line 1002 is the input signal 1 to the memory circuit 1601.
605, which corresponds to an input signal 1606 to the memory circuit 1602. The signal output through the signal line 1005 is the output signal 1606 from the memory circuit 1601 and the memory circuit 160.
2 corresponds to the output signal (which is output to the outside of the logic LSI 1600 through the output pin group 1607).

The external input / output pin 1608 corresponds to the external input / output pin group 122 in FIG. 1, and the external output pin 1609.
Corresponds to the external output pin 123.

When no mismatch occurs, the memory circuit 1
Reference numeral 601 stores the processed signal series of the checker LSI being compared with the processed signal series of the master LSI. On the other hand, the memory circuit 1602 stores the processed signal series of the checker LSI compared with one clock cycle before.

When a mismatch occurs, the signal 1604 is "
The memory circuit 14,1601,1 rises from "L" to "H".
The clock signal applied to the memory element forming 602 is suppressed. Therefore, the memory circuits 14, 1601, 1602
Holds the internal state at that time. That is, the memory circuit 1601 stores the processed signal series of the checker-side LSI when the mismatch occurs, and the memory circuit 1602 stores the processed signal series of the checker-side LSI immediately before the mismatch occurs. The storage circuit 14 holds the comparison result for each signal line.

By supplying the system clock 1603 and outputting the signal series stored in the memory circuits 1601 and 1602 from the external output pin group 1607, information for failure diagnosis (that is, when a mismatch occurs and immediately before the mismatch occurs). The checker side LSI processing signal sequence) can be obtained. Information stored in the memory circuit 14 is also
It can be output through the external output pin 1610.

According to the present embodiment, for example, even when an address mismatch occurs while incrementing the address, the faulty LSI can be specified.

The number of external output pins can be reduced by adopting, as the memory elements forming the memory circuits 14, 1601, 1602, those having an access terminal for a scan operation, and configuring a scan chain in these elements. it can.

Note that, in place of the mismatch signal position information when the mismatch occurs, the master L when the mismatch occurs
A means for storing the SI processed signal sequence may be provided. Further, instead of the processing signal sequence of the checker side LSI at the time of the mismatch occurrence and immediately before the mismatch occurrence, the processing signal sequence of the master side LSI at the time of the mismatch occurrence and immediately before the mismatch occurrence may be stored to achieve the above object. You can

The sixth embodiment of the present invention will be described with reference to FIG.

The present embodiment is an information processing system constructed by using the logic LSI of the present invention (here, the logic LSI in the first embodiment).

As shown in FIG. 18, this information processing system includes logic LSIs 11 and 12 and an external storage device 170.
1, input device 1702, display device 1703, bus signal lines 1704, 1705, control circuit 1706, substrate 170
7, controller 1708 and main memory 1711, 1
712.

The control circuit 1706 sets one of the logic LSI 11 and the logic LSI 12 in the master mode and the other in the checker mode.

The controller 1708 has a display device 170.
3 controls the information displayed in 3.

Logic LSIs 11 and 12, main memory 171
1, 1712 and the control circuit 1706 are mounted on the substrate 1707.

The operation of this information processing system is shown in FIGS.
8 will be described.

The control circuit 1706 is set in advance so that the logic LSI 11 is in the master mode and the logic LSI 12 is in the checker mode.

In normal operation, the user operates the display device 1703.
The desired processing is performed using the input device 1702 while referring to FIG. In this case, the logical L set to master mode
SI11 processes the signal input through the bus signal line 1704, and outputs the processing result to the bus signal line 1705.

On the other hand, the logic LSI 12 set in the checker mode also processes the signal input through the bus signal line 1704. Then, the logic LSI 12 compares its processing result with the processing result of the logic LSI 11 input through the bus signal line 1705. As a result of the comparison, when there is a mismatch, the comparison circuit 26 (see FIG. 1)
Sets the signal output through the external output pin 123 to "H". The signal is also output to the memory circuit 14, and when the signal becomes "H", the memory circuit 14 stores the comparison result for each bit at that time.

The signal output from the external output pin 123 is also input to the controller 1708 via the bus signal line 1705. The display device 1703 indicates that the signal is "
When it becomes "H", the user is notified of the occurrence of the abnormality by displaying a message indicating the occurrence of the mismatch.

Next, a method for the user to observe the disagreement information when an abnormality occurs will be described.

When the logic LSI 12 is realized by the circuit shown in FIG. 2 or 4, the comparison result can be observed by directly probing the signal line 124.

If the logic LSI 12 is realized by the circuit of FIG. 6, a scan clock is applied to the logic LSI 12. The mismatch information can be observed by probing the signal output from the external output pin 124 in synchronization with the scan clock. However, in this case, a separate tester device for generating a scan clock and probing a signal in synchronization with the scan clock is required.

When the storage value of the storage circuit 14 can be output to the system data bus by addressing or the like, the mismatch information can be observed through the bus signal line 1705 by changing the logic LSI 12 to the master mode. it can.
In this case, first, the control circuit 1706 changes the logic LSI 12 to the master mode. After that, the storage circuit 14 is designated using the input device 1702. The logic LSI 12 in the master mode outputs the content stored in the storage circuit 14 to the bus signal line 1705. Therefore, by displaying this value on the display device 1703, the comparison result can be observed.

The "logic unit" in the claims corresponds to, for example, the logic circuit unit 24 in FIG. The “own system signal sequence” corresponds to, for example, the signal sequence of the processing result output from the logic circuit unit 24 in FIG. The "other system signal series" corresponds to the signal series input from the input / output pin group 122 of FIG. 1, for example. The “comparison section” corresponds to the comparison circuit 26.

"Storage means" as used in the claims
Corresponds to, for example, the memory circuit 14 in FIG. 1 and the memory circuit 1403 in FIG. 7. Further, in the example of FIG. 8, it corresponds to the memory circuit 14 and the memory circuit 91. In the example of FIGS. 10 and 12, the memory circuit 1101 and in the example of FIG. 13, the memory circuit 14
11, the memory circuits 1411 and 19 in the example of FIG. In the example of FIG. 17, it corresponds to the storage circuits 1601 and 1602. Further, constituent elements for outputting the stored contents from these storage circuits, for example, a circuit for generating a scan clock and the like, the external output pin group 124, etc. are also included in the "storage means".

In the claims, the "mismatch detection signal" is a signal output from the comparison circuit 26, which indicates whether or not a mismatch occurs.

The "terminal" referred to in claim 6 corresponds to, for example, the input / output terminal group 122. The "mode control means" is, for example, the tristate gate array 28 in the logic LSI 12 set in the checker of FIG.
Is equivalent to The "mode designation signal" corresponds to the control signal 282 in FIG.

The "mode setting means" referred to in the claims corresponds to the control circuit 1706 in FIG. The “first bus signal line” corresponds to the bus signal line 1704. The “input means” corresponds to the input device 1702. The “second bus signal line” is the bus signal line 1705.
Is equivalent to “Observation means” means the controller 1708
And so on.

The "first input terminal" referred to in the claims corresponds to the input terminal 121.

The "second input terminal" corresponds to, for example, the external input / output terminal 122 in the example of FIG. 1 and the input / output terminal group 1412 in the example of FIG. The "arithmetic / comparison means" corresponds to, for example, the arithmetic circuit unit 24 and the comparison circuit 26 in the example of FIG. The “first output terminal” corresponds to, for example, the external output terminal 124 in the example of FIG. 1, the external output terminal 901 in the example of FIG. 8, and the external output terminal group 1103 in the example of FIG. 10. The “second output terminal” is, for example, the external output pin 1103 in the example of FIG.
Is equivalent to The “third output terminal” corresponds to the external output pin 1301 in the example of FIG. 12, for example. The external output pin 1421 in the example of FIG. 13 and the external output pin 181 in the example of FIG. 15 also serve as the second output terminal and the third output terminal. "Fourth output terminal"
Corresponds to the external output pin 123 in the example of FIG. 1, for example.

[0163]

By constructing a dual system using the logic LSI of the present invention, when one fails, not only the failure occurrence is detected, but also the signal line names whose signal values do not match are specified. be able to.

Further, since the faulty LSI can be specified by the signal value immediately before the fault has occurred, the parity, etc., the external output pin that has output an incorrect signal and its normal value / fault value can be identified. The failure diagnosis can be performed by referring to the failure dictionary used for the function test and the like.

Since it is known whether the failure location is the address section or the data section, it is possible to perform appropriate recovery processing such as purging the cache memory according to the failure location.

[Brief description of the drawings]

FIG. 1 is a configuration of a logic LSI showing a first embodiment of the present invention and an application example thereof.

FIG. 2 is a circuit diagram showing an example of a configuration (circuit 2601, circuit 1401) of a comparison circuit 26 and a memory circuit 14.

FIG. 3 is a time chart showing the operation of circuits 2601 and 1401.

FIG. 4 is a diagram showing another configuration example (circuit 1402) of the memory circuit 14 in FIG.

FIG. 5 is a time chart showing the operation of circuits 2601 and 1402.

6 is a diagram showing still another configuration example (circuit 1403) of the memory circuit 14 in FIG.

FIG. 7 is a block diagram showing a configuration of a logic LSI 8 according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a logic LSI 9 according to a third embodiment of the present invention.

9 is a configuration example of a memory circuit 91 in FIG. 8 (circuit 10).
It is a circuit diagram showing (01).

FIG. 10 is a logic LSI 1 according to a fourth embodiment of the present invention.
3 is a block diagram showing the configuration of 100. FIG.

11 is a circuit diagram showing a configuration example of a memory circuit 1101 in FIG.

FIG. 12 is a logic LSI 1300 that is a modified example of the third embodiment (FIGS. 8 and 9) and the fourth embodiment (FIG. 10).
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 13 is a logic LSI 1400 that is a modification of the third embodiment (FIGS. 8 and 9) and the fourth embodiment (FIG. 10).
FIG. 3 is a block diagram showing the configuration of FIG.

14 is a circuit diagram showing a configuration example of a memory circuit 1411 in FIG.

15 is a logic LSI that is an extension example of the example shown in FIG.
1 is a block diagram showing 1800. FIG.

16 is a circuit diagram showing a configuration example of a storage circuit 19 in FIG.

FIG. 17 shows a logic LSI 1 according to a fifth embodiment of the present invention.
6 is a block diagram showing the configuration of 600. FIG.

FIG. 18 is a block diagram showing an information processing system using a logic LSI of the present invention.

FIG. 19 shows a configuration of a conventional logic LSI and its application example.

[Explanation of symbols]

11 ... Logic LSI, 12 ... Logic LSI, 13 ... Memory circuit, 14 ... Memory circuit, 19 ... Memory circuit, 23 ... Logic circuit section, 24 ... Logic circuit section, 25 ... Comparison circuit, 26 ... Comparison circuit, 27 ... Tri State gate row, 28 ... Tri-state gate row, 81 ... Selection circuit, 91 ... Storage circuit, 12
1 ... External input pin group, 122 ... External input / output pin group, 12
3 ... External output pin, 124 External output pin group, 181, ... External output pin, 272 ... Control signal, 282 ... Control signal, 9
01 ... External output pin group, 902 ... External input / output pin group, 1
101 ... Memory circuit, 1103 ... External output pin group, 130
1 ... External output pin group, 1302 ... External input / output pin group, 1
411 ... Memory circuit, 1412 ... External input / output pin group, 14
21 ... External output pin, 1601 ... Memory circuit, 1602 ...
Storage circuit, 1607 ... External output pin, 1608 ... External input / output pin group, 1610 ... External output pin group

Front Page Continuation (72) Inventor Nobuyasu Kanakawa 7-1, 1-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Takashi Hotta 7-1-1, Omika-cho, Hitachi City, Ibaraki Hitachi, Ltd., Hitachi Research Laboratory

Claims (11)

[Claims] 1. A logic unit for receiving data input, performing a separately specified arithmetic processing on the input data, and outputting a signal series (hereinafter referred to as "self-system signal series") indicating the operation result. , Accepts an input of a predetermined signal sequence, compares the input signal sequence (hereinafter referred to as “other system signal sequence”) with the own system signal sequence, and forms a signal sequence that is the target of the comparison. A comparison unit that outputs a comparison result for each signal, and stores the comparison result for each signal that constitutes the signal sequence of the signal sequence that was the target of the comparison when the comparison unit detects a mismatch. And a storage unit that outputs the external to the logic circuit. 2. A logic unit that receives data input, performs a separately specified arithmetic processing on the input data, and outputs a signal series (hereinafter referred to as "self-system signal series") indicating the operation result. , Accepting an input of a signal sequence, comparing the input signal sequence (hereinafter referred to as “other system signal sequence”) with the own system signal sequence, and for each signal forming the signal sequence that was the object of the comparison. Comparing unit for outputting the comparison result of, the comparison result for each signal constituting the signal sequence of the signal sequence that was the target of the comparison when the comparison unit detects a mismatch, and the comparison unit Of the own system signal sequence that was the target of the comparison when a mismatch was detected and the other system signal sequence that was the target of the comparison when the comparison unit detected a mismatch, Logic circuit, characterized in that it comprises storage means for storing Kutomo two outputs it to the outside. 3. A logic unit that receives data input, performs a separately specified arithmetic processing on the input data, and outputs a signal series (hereinafter referred to as "self-system signal series") indicating the operation result. , A signal sequence is input, the input signal sequence (hereinafter referred to as “other system signal sequence”) is compared with the own system signal sequence, and each signal forming the signal sequence that is the target of the comparison is compared. Comparing unit for outputting the comparison result of, the comparison result for each signal constituting the signal sequence of the signal sequence that was the target of the comparison when the comparison unit detects a mismatch, and the comparison unit When the non-coincidence is detected, the own-system signal sequence that has been the target of the comparison and the own-system signal sequence before that, and the comparison unit when the non-coincidence is detected by the comparison unit. Logic circuit, characterized in that it comprises which was the other system signal sequence and with the other system a signal sequence in earlier, and a storage means for outputting it stores at least two outside of. 4. The comparing section outputs a mismatch detection signal indicating that any mismatch occurs in any one of the signals forming the signal sequence, the mismatch detection signal indicating that fact. The logic circuit according to claim 1, 2 or 3. 5. The logic circuit according to claim 1, 2, 3 or 4, wherein the logic section is configured to output the operation result to the outside. 6. A terminal for inputting / outputting a signal, a master mode as an operation mode for outputting the operation result of the logic section to the outside through the terminal, and a suppression of outputting the operation result to the outside through the terminal. And a checker mode for inputting the signal series input through the terminal as the other system signal series to the comparison circuit, and the operation mode is selected from the master mode and the checker mode according to a mode input signal separately input. 6. The logic circuit according to claim 5, further comprising: a mode control unit for setting the crab. 7. A mode in which two logic circuits according to claim 6 and a mode designating signal designating an operation mode of the logic circuit are generated, and one of the logic circuits is set to a master mode and the other is set to a checker mode. A first means for inputting the data to both the setting means and the logic circuit
Bus signal line, input means for supplying a signal to the first bus signal line, and the operation result output from the logic circuit set to the master mode is input to the logic circuit set to the checker mode. A data processing system, comprising: a second bus signal line for observing; and observing means for observing a state of the second bus signal line. 8. A first input terminal for inputting data, a second input terminal for inputting a predetermined signal series (hereinafter referred to as "other system signal series"), and an input through the first input terminal. A predetermined arithmetic processing is performed on the obtained data, and the arithmetic operation comparing means compares the signal series of the arithmetic processing result (hereinafter referred to as “self-system signal series”) with the other-system signal series. A first output terminal for outputting a comparison result for each signal forming the signal series, which is the target of the comparison when a mismatch is detected by the comparison by the comparison means. circuit. 9. A first input terminal for inputting data, a second input terminal for inputting a predetermined signal series (hereinafter referred to as "other system signal series"), and an input through the first input terminal. A predetermined arithmetic processing is performed on the obtained data, and a calculation series comparison means for comparing the signal series of the calculation processing result (hereinafter referred to as “self-system signal series”) with the other system signal series, A first output terminal for outputting the comparison result for each signal forming the signal series of the signal series that was the object of the comparison when the operation comparison means detects a mismatch, and the operation comparison means Is the target of the comparison when the mismatch is detected and the second output terminal to which the own system signal sequence is output and the calculation comparing means is the target of the comparison when the mismatch is detected. And a third output terminal for outputting the other-system signal sequence, and at least two output terminals out of the third output terminals. 10. A first input terminal for inputting data, a second input terminal for inputting a predetermined signal series (hereinafter referred to as "other system signal series"), and an input through the first input terminal. A predetermined arithmetic processing is performed on the obtained data, and a calculation comparing means for comparing the signal series of the calculation processing result (hereinafter referred to as “own system signal series”) with the other system signal series, A first output terminal for outputting the comparison result for each signal forming the signal series of the signal series that was the object of the comparison when the operation comparison means detects a mismatch, and the operation comparison means When the mismatch is detected, the operation comparing means detects a mismatch between the second output terminal to which the own system signal sequence which has been the target of the comparison and the previous own system signal sequence before that are output. And a third output terminal that outputs the other-system signal sequence that was the target of the comparison when the signal is output and a third output terminal that outputs the other-system signal sequence before that. Characteristic logic circuit. 11. The apparatus according to claim 8, further comprising a fourth output terminal for outputting a signal indicating that the own system signal series and the other system signal series do not match. 9. The logic circuit according to 9 or 10.