JPH0918331A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a high-speed operation by a low power supply voltage by providing a main switching means for changing a conducting state corresponding to a voltage applied to a control terminal and a voltage conversion means for outputting a prescribed voltage to the control terminal. SOLUTION: This logic circuit 1 is provided with a voltage converter 10 and a main switching element 20, the voltage converter 10 drives the main switching element 20 corresponding to the voltage of a node 11 and the main switching element 20 changes the conducting state between the nodes 22 and 23 corresponding to the voltage of the node 21. A power supply voltage Vdd is supplied to the node 14 and a resistor 13 pulls up the node 12 which functions as the output terminal of the logic circuit 1 to the power supply voltage Vdd. When the main switching element 20 is ON, the voltage higher than the Vdd is supplied to the node 21 of the control terminal. Thus, the turn-ON time of the main switching element 20 is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit that operates at high speed with a low voltage power supply.

[0002]

2. Description of the Related Art The use of a capacitor to apply a voltage higher than the power supply voltage between the gate and source of a transistor to improve the operation speed is described in, for example, Japanese Patent Laid-Open No. 5-14166. . FIG. 31 is a circuit diagram of a conventional logic circuit. Reference numeral 3101 represents a logic input terminal, 3120 represents an output terminal, and 3110 represents a power supply for supplying a voltage Vdd. 31
Reference numerals 08 and 3109 represent a P-channel FET and an N-channel FET, respectively. 3106 and 3107 are
It is a bias power supply that supplies a voltage Vs. 3102 and 3103 represent capacitors. 3104 and 31
05 is an N channel FET and a P channel F, respectively.
Represents ET.

[0003]

However, the above-mentioned prior art has the following problems. That is,
A leak current flows when the FETs 3108 and 3109 are off. Further, there is a problem that the FETs 3108 and 3109 cannot be sufficiently cut off by sufficiently driving them or by applying a deep reverse voltage to their gates. As a result, power consumption increases and high-speed operation at a low voltage is impossible.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a logic circuit which can realize high-speed operation with a low power supply voltage.

[0005]

SUMMARY OF THE INVENTION A logic circuit according to the present invention has at least 2 depending on a voltage applied to a control terminal.
The main switching means for changing the conduction state between the two terminals and the voltage converting means for converting the voltage of the input terminal and outputting the converted voltage to the control terminal are provided, thereby achieving the above object. To be done.

In one embodiment, the voltage converting means has a voltage generating means and a sub-switching means.

In one embodiment, the sub-switching means has an SOI structure.

[0008] In one embodiment, the voltage generating means includes at least one of a capacitor, a battery, and a ferroelectric substance.

In one embodiment, when the state of the input terminal for bringing the main switching means into the conducting state is set to the first state, the voltage conversion means sets the voltage higher than the voltage of the input terminal in the first state. Is supplied to the control terminal.

In one embodiment, when the state of the input terminal that brings the main switching means into the non-conducting state is set to the second state, the voltage conversion means is lower than the voltage of the input terminal in the second state. A voltage is supplied to the control terminal.

In one embodiment, when the state of the input terminal that brings the main switching means into the conducting state is the first state and the state of the input terminal that brings the main switching means into the non-conducting state is the second state. , The voltage conversion means supplies a voltage higher than the voltage of the input terminal to the control terminal in the first state, and supplies a voltage lower than the voltage of the input terminal to the control terminal in the second state. .

[0012] In one embodiment, the voltage conversion means further includes a capacitor having a first terminal connected to the input terminal, and the sub-switching means includes a second capacitor of the capacitor in the first state. A terminal is connected to the control terminal of the main switching means, the second terminal of the capacitor is connected to the voltage generating means in a state other than the first state, and the control terminal of the main switching means is grounded. Connecting.

In one embodiment, the voltage conversion means further includes a capacitor having a first terminal connected to the input terminal, and the sub-switching means includes a second capacitor of the capacitor in the second state. A terminal connected to the control terminal of the main switching means, and in a state other than the second state, the first terminal of the capacitor is connected to the control terminal of the main switching means and the second terminal of the capacitor. To ground.

In one embodiment, the voltage conversion means further includes a first capacitor having a first terminal connected to the input terminal and a second capacitor having a first terminal connected to the input terminal, In the first state, the second terminal of the first capacitor is connected to ground, the second terminal of the second capacitor is connected to the control terminal of the main switching means, and in the second state, the first terminal The second terminal of the capacitor is connected to the control terminal of the main switching means, and the second terminal of the second capacitor is connected to the voltage generating means.

In one embodiment, the main switching means comprises an N channel MOSFET.

In one embodiment, the main switching means comprises a P-channel MOSFET.

In one embodiment, the main switching means is a complementary MOSFET.

The logic circuit according to the present invention converts the voltage at the input terminal and the first and second main switching means for changing the conduction state between at least two terminals according to the voltage applied to the control terminal, The converted voltage is converted into the first
First voltage converting means for outputting to the control terminal of the main switching means, and second voltage converting means for converting the voltage of the input terminal and outputting the converted voltage to the control terminal of the second main switching means. , The first voltage conversion means includes a first capacitor having first and second terminals, a second capacitor having first and second terminals, and a first sub-switching means. , A first voltage generating means, the first terminal of the first capacitor and the first terminal of the second capacitor are connected to the input terminal, and the second voltage converting means , First and second
A third capacitor having a terminal, a fourth capacitor having first and second terminals, a second sub-switching means, and a second voltage generating means, and the first terminal of the third capacitor and The first terminal of the fourth capacitor is connected to the input terminal via an inverter, and the first sub-switching means connects the second terminal of the first capacitor to ground in the first state. The second terminal of the second capacitor is connected to the control terminal of the first main switching means, and the second terminal of the first capacitor is connected to the control of the first main switching means in the second state. A second terminal of the second capacitor, the second terminal of the second capacitor being connected to the first voltage generating means, the second sub-switching means in the second state,
Connect the terminal to ground and connect the second capacitor of the second capacitor
A terminal connected to the control terminal of the second main switching means, and in the first state, the second terminal of the first capacitor.
The terminal is connected to the control terminal of the second main switching means and the second terminal of the second capacitor is connected to the second voltage generating means, whereby the above object is achieved.

The operation will be described below. The logic circuit according to the present invention stores an electric charge in the capacitor by applying a voltage to the capacitor. The sum of the voltage due to this charge accumulated in the capacitor and the voltage supplied to the input terminal is applied to the gate of the switching element. Thereby, the voltage supplied to the gate can be higher than Vdd or lower than the ground level. Therefore, even with a low power supply voltage, it is possible to sufficiently drive the switching element and sufficiently cut off. As a result, a sufficiently low on-resistance can be realized without generating an off-leak current, so that a logic circuit of low voltage driving and low power consumption can be realized.

[0020]

DETAILED DESCRIPTION OF THE INVENTION A logic circuit according to the present invention will be described below with reference to the drawings. Like reference numerals refer to like components. As used herein, a "V" followed by a reference numeral representing a node indicates the potential of that node with respect to ground. For example, "voltage V1" represents the potential of "node 1" with respect to ground. For simplicity, the potential of the node with respect to the ground is also referred to as “node voltage” or “node level”.

In the present specification, in an ideal state, a logic low level (hereinafter referred to as "L level") is equal to 0 V (that is, a ground potential), and a "logic high level".
(Hereinafter, referred to as “H level”) is assumed to be equal to a potential higher than the ground by the power supply voltage Vdd. Ideally, the node (particularly the output node) of the logic circuit should be at either the H level or the L level, and
You should not take levels between levels. However, in the actual operation of the logic circuit, the voltage of the node may take a transitional intermediate voltage level.

FIG. 1 is a block diagram of a logic circuit 1 according to the present invention. The logic circuit 1 has a voltage converter 10 and a main switching element 20. The voltage converter 10 drives the main switching element 20 according to the voltage of the node 11. The main switching element 20 has a node 21
˜23, the conduction state between the nodes 22 and 23 changes according to the voltage of the node 21. In this specification, a state in which the switching element conducts is referred to as an "on" state, and a state in which the switching element does not conduct is referred to as an "off" state. As the main switching element 20,
For example, a FET (field effect transistor) can be used. When an FET is used as the main switching element 20, the nodes 21, 22 and 23 correspond to the gate, drain and source, respectively.

A power supply voltage Vdd is supplied to the node 14. The resistor 13 pulls up the node 12 that functions as the output terminal of the logic circuit 1 to the power supply voltage Vdd.
When the main switching element 20 is on, the node 12 is at L level, and when the main switching element 20 is off, the node 12 is at H level. In FIG. 1, node 22 is pulled up,
Although the node 23 is connected to the ground, the connection is not limited to this. For example, as the main switching element 20, a plurality of switching elements connected so as to form a transfer gate can be used.

The voltage converter 10 improves the switching characteristic of the main switching element 20 by converting the voltage of the node 11 and outputting it to the node 21. Specifically, this improvement includes increasing the switching speed (that is, improving the transient characteristics) and reducing the on-resistance of the switching element (that is, improving the steady characteristics). Voltage converter 10 used in the logic circuit 1 according to the present invention
There are the following types 1 to 3.

In the type 1, when the node 11 is at L level (that is, ground level), the node 21 is at ground level, and when the node 11 is at H level (that is, Vdd level), the node 21 is at (Vdd + Vov1) level. is there. Here, Vdd and Vov1 are positive voltages. Therefore, the type 1 logic circuit 1 overdrives the main switching element 20 when the voltage of the node 21 is at the H level, that is, when the main switching element 20 is in the ON state. In other words, when the main switching element 20 is on, a voltage higher than Vdd is supplied to the node 21 that is its control terminal. This makes it possible to shorten the turn-on time of the main switching element 20 and reduce the turn-on resistance of the main switching element 20 (that is, the resistance corresponding to the drain-source voltage VDS (sat) in the on state). Become. As the main switching element 20 used in the type 1 logic circuit 1, it is preferable to use an FET having a threshold voltage Vt of 0.35 V or more.

In the type 2, when the node 11 is at L level (that is, ground level), the node 21 is at -Vov2.
When the node 11 is at the H level (that is, Vdd level), the node 21 is at the Vdd level. Here, Vov2 is a positive voltage. Therefore, the type 2 logic circuit 1 sufficiently cuts off the main switching element 20 when the voltage of the node 21 is at the L level, that is, when the main switching element 20 is in the off state. In other words, the main switching element 2
When 0 is off, its control terminal is node 21
Is supplied with a voltage lower than the ground level. This makes it possible to shorten the turn-off time of the main switching element 20 and increase the turn-off resistance of the main switching element 20. Type 2
Main switching element 20 used in the logic circuit 1 of
As the above, it is preferable to use an FET whose threshold voltage Vt is 0.35 V or less.

In the type 3, when the node 11 is at the L level (that is, the ground level), the node 21 has -Vov2.
When the node 11 is at the H level (that is, the Vdd level), the node 21 is at the (Vdd + Vov1) level. Therefore, type 3 logic circuit 1
When the voltage of 1 is at the H level, that is, when the main switching element 20 is in the on state, the main switching element 20 is overdriven. In other words, when the main switching element 20 is on,
A voltage higher than Vdd is supplied to the node 21 which is its control terminal. Thereby, the turn-on time of the main switching element 20 is shortened, and the turn-on resistance of the main switching element 20 (that is, the resistance corresponding to the drain-source voltage VDS (sat) in the on state).
Can be reduced.

In the type 3 logic circuit 1, the main switching element 20 is sufficiently cut off when the voltage of the node 21 is at the L level, that is, when the main switching element 20 is in the off state. In other words, when the main switching element 20 is off, the node 21 that is its control terminal is supplied with a voltage lower than the ground level. This makes it possible to shorten the turn-off time of the main switching element 20 and increase the turn-off resistance of the main switching element 20. As the main switching element 20 used in the type 3 logic circuit 1, it is preferable to use an FET having a threshold voltage Vt of 0.35 V or less.

(Embodiment 1) FIGS. 2A to 2C are circuit diagrams of a first embodiment of a logic circuit according to the present invention. The logic circuit of the first embodiment is classified into the above type 1.

The operation of the logic circuit shown in FIG. 2A will be described below. The logic circuit shown in FIG. 2A has a voltage converter 210.
And a main switching element 220. The node 211 is set to H level or L level by receiving an input signal from the outside. In this specification, the state in which the main switching element (220 in the first embodiment) is off is defined as state I, and the state in which it is on is defined as state II. In the state II, the voltage converter 210 outputs a voltage (Vdd + Vov1) higher than the voltage Vdd supplied to the node 211 to the node 221. As a result, the switching characteristics of the main switching element 220 are improved. Main switching element 2
20 is MOS (metal-oxide-semiconductor) F
ET is used and nodes 221, 222 and 2 are
Reference numerals 23 are a gate, a drain and a source, respectively. In the following embodiments, an SOI (semiconductor-on-insulator) transistor, an MES (metal-semiconductor) FET, a bipolar transistor, a TFT (thin film transistor), or the like may be used as the main switching element.

The voltage converter 210 has switches S20 and S21, a voltage generator 214 and a capacitor 212. The switches S20 and S21 have a plurality of FETs.
Can be realized. Although the power supply voltage Vdd is used as the voltage generator 214 in the first embodiment, the voltage generator 2
The voltage value supplied by 14 is not limited to this. Also the first
In the above embodiment, an external power supply is used as the voltage generator 214, but the invention is not limited to this. In all embodiments, capacitors or batteries may be used as the voltage generator. As a capacitor such as the capacitor 212 or the voltage generator 214, it is preferable to use a capacitor using a ferroelectric material. The reason for this will be described in detail later.

In state I, switch S20 has contact C
1 is set to connect to contact C2, and in state II switch S20 is set to connect contact C1 to contact C3. Switch S21 in state I
Is set so that the contact C1 is connected to the contact C2,
In state II, the switch S21 has the contact C1 at the contact C.
2 is set not to be connected. Therefore, in Figure 2 (a)
Indicates state I. FIG. 2B is an equivalent circuit of the circuit shown in FIG. 2A in the state I. Figure 2 (c)
Is an equivalent circuit of the circuit shown in FIG. 2A in the state II.

As shown in FIG. 2B, in the state I, the node 211 is at L level. In state I,
A node 211 to which one end of the capacitor 212 is connected
Is connected to the ground, and the other end of the capacitor 212 is connected to the voltage generator 214. As a result, the capacitor 212 receives the voltage Vd of the voltage generator 214.
It is charged by d. In the state I, since the node 221 which is the gate of the main switching element 220 is connected to the ground, the main switching element 220
The gate charge is discharged. As a result, the turn-off time of the main switching element 220 is shortened.

As shown in FIG. 2C, in the state II, the node 211 is at the H level. In the state II, the node 211 to which one end of the capacitor 212 is connected is pulled up to Vdd which is the power supply voltage, and the other end of the capacitor 212 is connected to the node 221. As a result, the voltage (Vdd + Vov) is applied to the node 221 which is the gate of the main switching element 220.
1) is supplied. Here, Vov1 is a positive voltage and is determined by the voltage supplied by the voltage generator 214 and the gate-source capacitance of the main switching element 220. When the capacitance of the capacitor 212 and the gate-source capacitance of the main switching element 220 are C212 and Cgs, respectively, C2
It is preferable that 12 >> Cgs.

FIG. 3 is a circuit diagram of a first embodiment of a logic circuit of the present invention realized by using an N channel FET and a P channel FET. The voltage converter 310 and the main switching element 320 correspond to the voltage converter 210 and the main switching element 220, respectively. Inverter 330 inverts the voltage applied at node 301 and outputs it to node 302. That is, node 3
When 01 is H level, the node 302 is L level, and when node 301 is L level, the node 302 is H level.
Level. Capacitor 312 and voltage generator 31
4 is a capacitor 212 and a voltage generator 21 respectively.
Corresponds to 4. The FETs 332 and 334 realize the function of the switch S20, and the FET 336 controls the switch S2.
1 function is realized. Main switching element 320
Corresponds to the main switching element 220, and nodes 304, 322 and 323 are respectively connected to node 2
21, 222 and 223. In the logic circuit of FIG. 3, because of the inverter 330, the main switching element 320 is in the off state when the node 301 is at the H level, and the main switching element 320 is in the on state when the node 301 is at the L level (that is, Node 30
Except that the logic of 1 is inverted) operates in the same manner as described with reference to FIG. That is, the node 30 of FIG.
2 corresponds to the node 211 in FIG. This is true for all the examples below. The use of the inverter here is not the essence of the present invention, and only the inverter is required to switch the switching elements of the voltage converter in a predetermined phase.

FIG. 4 is a diagram showing the voltages of the nodes 301 to 304 in FIG. 3 in the states I and II. The node 304 that is the gate of the main switching element 320
In state II, the voltage V304 of (Vdd + Vo
v1). The main switching element 320 is sufficiently driven by this voltage V304. As a result, turn-on time and turn-on resistance can be reduced.

Here, the gate of the N-channel MOS transistor used as the main switching element 320 is
The relationship between the source-to-source voltage Vgs and the drain current Id is expressed by the following equation.

Id = K (Vgs-Vt) ² where K is a positive constant and Vt is the threshold voltage of the N-channel FET. In the future, it is expected that the operating voltage of LSI (Large Scale Integrated Circuit) will decrease more and more due to the reduction of reliability and power consumption. Power supply voltage Vd
When d is 1.0 V and Vt is 0.35 V, the voltage generator 31
4 is assumed to supply the power supply voltage Vdd. The ratio of the drain current of the main switching device 320 of the logic circuit according to the present invention to the drain current of the logic circuit according to the prior art is as follows.

(1.0 + 1.0−0.35) ² /(1.0−0.35) ² = 6.44 As can be seen from this equation, according to the present invention, the drain current of the main switching element 320 can be increased, Higher speed operation becomes possible.

FIG. 5A is a circuit diagram of a logic circuit in which a P-channel FET is used instead of the main switching element 220 which is the N-channel FET of the circuit shown in FIG. 5B is a circuit diagram of a logic circuit in which two switches in the circuit of FIG. 5A are realized by FETs. Voltage converter 510 and main switching element 5
20 corresponds to the voltage converter 210 and the main switching element 220, respectively. Nodes 511, 521-
Reference numeral 523 corresponds to the nodes 211 and 221-223, respectively. Switches S50 and S51, capacitor 51
2. The voltage generator 514 corresponds to the switches S20 and S21, the capacitor 212, and the voltage generator 214, respectively. The power supply 516 supplies an output voltage to the node 523 via the main switching element 520. The voltage generator 514 supplies the same Vdd as the voltage supplied by the power supply 516, but is not limited to this voltage value.

The operation of the circuit shown in FIG. 5A will be described.
In the state I, the switch S50 has the contact C1 and the contact C2.
, And in state II, switch S50 is set so that contact C1 is connected to contact C3. In state I, switch S51 has contact C1
Is set to be connected to the contact C2, and in the state II, the switch S51 is set so that the contact C1 is not connected to the contact C2. In state I, node 511
The terminal of the capacitor 512 connected to is at H level, and the terminal of the capacitor 512 connected to the contact C1 of the switch S50 is at ground level. Therefore state I
At, the capacitor 512 is charged. On the other hand, the gate of the main switching element 520 (that is, the node 5
21) is set to the H level.

In the state II, the node 511 becomes L level, and the other terminal of the capacitor 512 is connected to the node 521. As a result, the node 521 has −
A voltage of Vov1 (Vov1 is a positive voltage) is supplied.

In FIG. 5B, the FET 550 corresponds to the switch S51, and the FETs 551 and 552 are
Corresponds to the switch S50. For example, the signal “D bar” applied to the gate of FET 550 represents the inversion of signal D. The circuit shown in (b) of FIG. 5 is a circuit complementary to the circuit of FIG. 3, and its operation is similar to that of the circuit of FIG.

(Embodiment 2) FIGS. 6A to 6C are circuit diagrams of a second embodiment of the logic circuit according to the present invention. The logic circuit of the second embodiment is classified into the type 2 described above.

The operation of the logic circuit shown in FIG. 6A will be described below. The logic circuit shown in FIG. 6A has a voltage converter 610.
And a main switching element 620. Node 611 is set to H level or L level by receiving an input signal from the outside. In the state I, the voltage converter 610 outputs to the node 621 a voltage −Vov2 lower than the voltage 0 V supplied to the node 611. As a result, the switching characteristics of the main switching element 620 are improved. MOS (metal-oxide-semiconductor) is used as the main switching element 620.
FETs are used and nodes 621, 622 and 623 are the gate, drain and source, respectively.

Voltage converter 610 has switches S60 and S61, and capacitor 612. The switches S60 and S61 can be realized by a plurality of FETs. In the second embodiment, the contact C3 of the switch S60
Is connected to the ground, but the voltage value applied to the contact C3 is not limited to this. However, as can be seen from the operation described below, the contact C3 is preferably connected to the ground.

In state I, switch S60 has contact C
1 is set to connect to contact C2, and in state II switch S60 is set to connect contact C1 to contact C3. In state I, switch S61
Is set so that the contact C1 is not connected to the contact C2, and in the state II, the switch S61 is set so that the contact C1 is connected to the contact C2. Therefore, in FIG.
(a) shows the state I. FIG. 6B is an equivalent circuit of the circuit shown in FIG. 6A in the state I. Figure 6 (c)
Is an equivalent circuit of the circuit shown in FIG. 6A in the state II.

As shown in FIG. 6B, in the state I, the node 611 is at the L level. In the state I, the node 6 to which one end of the capacitor 612 is connected
11 is pulled down to 0V which is the ground level, and the other end of the capacitor 612 is connected to the node 621. As a result, the main switching element 62
The voltage -Vov2 is supplied to the node 621 which is the gate of 0. Here, Vov2 is a positive voltage and is determined by the voltage supplied to the node 611 and the gate-source capacitance of the main switching element 620. The capacitance of the capacitor 612 and the gate-source capacitance of the main switching element 620 are C6 and C6, respectively.
When 12 and Cgs, it is preferable that C612 >> Cgs.

As shown in FIG. 6C, in the state II, the node 6 to which one end of the capacitor 612 is connected.
11 is an H level (that is, Vdd level), and the other end of the capacitor 612 is connected to the ground.
As a result, the capacitor 612 is charged by the externally supplied voltage Vdd connected to the node 611.

FIG. 7 is a circuit diagram of a second embodiment of the logic circuit of the present invention realized by using an N channel FET and a P channel FET. The voltage converter 710 and the main switching element 720 correspond to the voltage converter 610 and the main switching element 620, respectively. Inverter 730 inverts the voltage applied at node 701 and outputs it to node 702. That is, node 7
When 01 is at H level, the node 702 is at L level, and when the node 701 is at L level, the node 702 is at H level.
Level. The capacitor 712 is the capacitor 612.
Corresponding to FETs 732 and 734 are switches S
60 function is realized, and the FET 736 switches the switch S61.
Implement the function of The main switching element 720 is
Corresponding to the main switching element 620, nodes 704, 722 and 723 are respectively connected to node 62.
Corresponding to 1, 622 and 623. The logic circuit of FIG. 7 operates in the same manner as described with reference to FIG.

FIG. 8 is a diagram showing voltages at the nodes 701 to 704 in FIG. 7 in the states I and II. The node 704 which is the gate of the main switching element 720
In the state I, the voltage V704 is −Vov2. The main switching element 720 is sufficiently cut off by this voltage V704. As a result, it is possible to reduce the turn-off time and increase the turn-off resistance.

(Embodiment 3) FIGS. 9A to 9C are circuit diagrams of a third embodiment of the logic circuit according to the present invention. The logic circuit of the third embodiment is classified into the above-mentioned type 3.

The operation of the logic circuit shown in FIG. 9A will be described below. The logic circuit shown in FIG. 9A has a voltage converter 910.
And a main switching element 920. Node 911 is set to H level or L level by receiving an input signal from the outside. In the state I, the voltage converter 910 outputs the voltage −Vov2, which is lower than the voltage 0V supplied to the node 911, to the node 921. In state II, the voltage converter 910 has a voltage (Vd) higher than the voltage Vdd supplied to the node 911.
d + Vov1) is output to the node 921. as a result,
The switching characteristics of the main switching element 920 are improved. MO as the main switching element 920
An S (metal-oxide-semiconductor) FET is used, and nodes 921, 922 and 923 are a gate, a drain and a source, respectively.

Voltage converter 910 has switches S90 and S91, a voltage generator 914 and capacitors 912 and 913. The switches S90 and S91 are
It can be realized by a plurality of FETs. Although the power supply voltage Vdd is used as the voltage generator 914 in the third embodiment,
The voltage value supplied by the voltage generator 914 is not limited to this. Further, in the third embodiment, an external power supply is used as the voltage generator 914, but the invention is not limited to this. For example, a capacitor using a ferroelectric material may be used as a voltage generator 9
It may be used as 14.

In state I, switch S90 has contact C
1 is set to connect to contact C2, and in state II switch S90 is set to connect contact C1 to contact C3. Switch S91 in state I
Is set so that the contact C1 is connected to the contact C2,
In state II, the switch S91 has the contact C1 at the contact C.
3 is set to be connected. Therefore, in (a) of FIG.
Indicates state I. FIG. 9B is an equivalent circuit of the circuit shown in FIG. 9A in the state I. Figure 9 (c)
Is an equivalent circuit of the circuit shown in FIG. 9A in state II.

As shown in FIG. 9B, in the state I, the node 911 is at the L level. In state I,
A node 911 to which one end of the capacitor 912 is connected
Are connected to the ground, and the other end of the capacitor 912 is connected to the voltage generator 914. As a result, the capacitor 912 causes the voltage Vd of the voltage generator 914 to increase.
It is charged by d. In the state I, the node 921, which is the gate of the main switching element 920, is connected to the ground via the capacitor 913. Since the capacitor 913 is charged in the state II as described later, the voltage Vov2 is applied to the nodes 911 and 9
Supply during 21. Therefore, the voltage of the node 921 is
-Vov2. Here, Vov2 is a positive voltage and is determined by the voltage supplied to the node 911 (that is, Vdd) and the gate-source capacitance of the main switching element 920. When the capacitance of the capacitor 913 and the gate-source capacitance of the main switching element 920 are C913 and Cgs, respectively, it is preferable that C913 >> Cgs.

As shown in FIG. 9C, in the state II, the node 911 is at the H level. In state II, node 9 to which one end of capacitor 913 is connected
11 receives the power supply voltage Vdd, and the other end of the capacitor 913 is connected to the ground. As a result, the capacitor 913 is charged by the power supply voltage Vdd.
In the state II, the node 921 which is the gate of the main switching element 920 is connected to the node 911 via the capacitor 912. Since the capacitor 912 is charged in the state I as described above, Vov1
Is applied between nodes 911 and 921.
Therefore, the voltage of the node 921 is (Vdd + Vov1)
It is. Here, Vov1 is a positive voltage, and is determined by the voltage (that is, Vdd) supplied by the voltage generator 914 and the gate-source capacitance of the main switching element 920. When the capacitance of the capacitor 912 and the gate-source capacitance of the main switching element 920 are C912 and Cgs, respectively,
It is preferable that C912 >> Cgs.

FIG. 10 is a circuit diagram of a third embodiment of the logic circuit of the present invention realized by using an N channel FET and a P channel FET. The voltage converter 1010 and the main switching element 1020 are the voltage converter 9 and the voltage converter 9 respectively.
10 and the main switching element 920.
Inverter 1030 inverts the voltage applied at node 1001 and outputs the inverted voltage to node 1002. That is, when the node 1001 is at the H level, the node 1002
Is at the L level, and when the node 1001 is at the L level,
The node 1002 is at the H level. Capacitor 1012
And 1013, and voltage generator 1014 are capacitors 912 and 913, and voltage generator 9 respectively.
14 corresponds to. FETs 1032 and 1034 realize the function of the switch S90, and FETs 1033 and 1
036 realizes the function of the switch S91. The main switching element 1020 is the main switching element 9
20 and nodes 1005, 1022 and 1023 are connected to nodes 921, 922 and 92, respectively.
Corresponds to 3. The logic circuit of FIG. 10 operates in the same manner as described with reference to FIG.

FIG. 11 is a diagram showing the voltages of the nodes 1001 to 1005 of FIG. 10 in the states I and II. In the state I, the voltage V1005 of the node 1005 which is the gate of the main switching element 1020 is −
Vov2, and in state II, (Vdd + Vov
1). As a result, the main switching element
Well driven and well cut off. This voltage V1005 causes the main switching element 10 to
In the case of 20, the turn-on time and the turn-off time can be reduced, and the turn-on resistance and the turn-off resistance can be increased.

FIG. 12 is a circuit diagram of a structure suitable for use in place of the main switching element 1020 of FIG. Node 1205 corresponds to node 1005 and receives the output from voltage converter 1010. Node 122
5 is pulled up to the power supply voltage Vdd. FET
1220 and 1221 change the voltage at node 1222 by alternately turning on. That is, when the node 1205 is at the H level, the FET 122
By turning off 0 and turning on the FET 1221,
The node 1222 becomes L level. When the node 1205 is at L level, the FET 1220 turns on and the FET 1
When the node 221 turns off, the node 1222 changes to H
Become a level. The voltage converter of the logic circuit of the third embodiment outputs -Vov2 (<0) in the state I and (Vdd + Vov1) (> Vd in the state II).
d) is output. As a result, the complementary FE shown in FIG.
The main switching element having a configuration in which Ts are connected in series can be efficiently driven.

Referring again to FIG. 9A, the voltage generator 914 generates the power supply voltage Vdd, and the H level of the node 911 is also equal to the power supply voltage Vdd. Therefore, the capacitors 912 and 913 are charged by the voltage Vdd, but are not limited to this voltage value. In order to apply a higher voltage to the control terminal to overdrive the main switching element, it is preferable that the voltage generated by the voltage generator 914 is high. Also, the contact C of the switch S91
Although 3 is connected to the ground, a voltage different from the ground level may be set. To cut off the main switching element deeper, contact C3
Are preferably supplied with a voltage even below ground level.

(Fourth Embodiment) FIG. 13 is a circuit diagram of a fourth embodiment of the logic circuit according to the present invention. The fourth embodiment is the first
And the configuration of the second embodiment. First, the operations of the voltage converter 1310 and the FET 1331 will be described.
The state in which the FET 1331 is off is set to the state I, and the FET 13
A state in which 31 is on is referred to as a state II. In state I,
Switch 1312 is set to connect capacitor 1311 to voltage generator 1313, and switch 1315
Are set to connect the gate of the FET 1331 to the power supply 1380. In state II, switch 131
2 is set to connect the capacitor 1311 to the FET 1331, and the switch 1315 switches the FET 1331
Is set not to be connected to the power supply 1380. As a result, in the state I, a voltage lower than 0V is supplied to the gate of the FET 1331. This voltage corresponds to −Vov2 described in the second embodiment.

Next, the voltage converter 1320 and the FET 13
The operation of 32 will be described. A state in which the FET 1332 is off is set as a state I, and a state in which the FET 1332 is on is set as a state II. In state I, switch 1322 is set to connect capacitor 1321 to voltage generator 1323 and switch 1325 is set to connect the gate of FET 1332 to ground. In state II, switch 1322 causes capacitor 1321 to FE.
The switch 132 is set to connect to T1332.
5 is set not to connect the gate of FET 1332 to ground. As a result, in state II, F
A voltage higher than the power supply voltage Vdd is supplied to the gate of the ET1332. This voltage corresponds to (Vdd + Vov1) described in the first embodiment.

In the fourth embodiment, the power supply voltage Vdd
A power supply 1380 for supplying power and voltage generators 1313 and 1323 are used. Voltage generators 1313 and 132
3 generates a voltage Vdd, for example. Voltage generator 131
3 may be used as the ground, and the power supply 1380 may be used as the voltage generator 1323. In this case, the contact connected to the negative electrode of the voltage generator 1313 is connected to the ground, and the contact connected to the positive electrode of the voltage generator 1323 is connected to the positive electrode of the power supply 1380. As a result, only one type of power supply (ie, power supply 1380) is needed. This also applies to the other embodiments.

When the node 1301 is at H level, the node 1390 is at L level, and when the node 1301 is at L level, the node 1390 is at H level. In other words, the circuit shown in FIG. 13 functions as an inverter.

FIG. 14 is a circuit diagram of a logic circuit in which the four switches in the circuit of FIG. 13 are realized by FETs. FETs 1412 and 1414 are switches 131
2, the FETs 1422 and 1424 are connected to the switch 13
22. FETs 1415 and 1425 correspond to switches 1315 and 1325, respectively. The circuit of FIG. 14 operates in the same manner as described for the circuit of FIG.

(Embodiment 5) FIG. 15 is a circuit diagram of a fifth embodiment of a logic circuit according to the present invention. The circuit of FIG.
It has the same configuration as in FIG. 13 except that the FETs 1331 and 1332 are replaced by the FETs 1531 and 1532, and the node 1301 is replaced by the nodes 1501 and 1502. Switch 1312,
1315, 1322 and 1325 operate in the same manner as described with reference to FIG.

When the input signal received by the node 1502 is D, the node 1501 receives D bar as an input signal. FETs 1531 and 1532 turn on and off at the same time, resulting in nodes 1591 and 1592.
The conduction state of changes. For example, nodes 1501 and 1
When 502 is at L level and H level, respectively, both FETs 1531 and 1532 are in the ON state. Conversely, when nodes 1501 and 1502 are at the H level and the L level, respectively, FETs 1531 and 1532 are both off. In other words,
The fifth embodiment applies the logic circuit according to the present invention to a transfer gate.

FIG. 16 is a circuit diagram of a logic circuit in which the four switches in the circuit of FIG. 15 are realized by FETs. The circuit of FIG. 16 operates in the same manner as described for the circuit of FIG.

(Embodiment 6) FIG. 17 is a circuit diagram of a sixth embodiment of a logic circuit according to the present invention. The logic circuit shown in FIG. 17 is obtained by using the voltage converter 1010 in the third embodiment described with reference to FIG.
Drive 32. When the node 1701 is at the L level, the nodes 1705 and 1706 are (Vd
d + Vov1) and -Vov2, resulting in nodes 1791 and 1792 conducting. Node 170
When 1 is at H level, nodes 1705 and 1706
Becomes -Vov2 and (Vdd + Vov1), respectively, and as a result, nodes 1791 and 1792 become non-conductive.

According to the sixth embodiment, when the FETs 1731 and 1732 are off, -Vov2 and (V
dd + Vov1) can be given respectively. This allows the FETs 1731 and 1732 to be completely turned off. Further, an FET having a low Vt can be used, and the operating voltage can be lowered.

(Embodiment 7) FIG. 18 is a circuit diagram of a seventh embodiment of a logic circuit according to the present invention. In FIG.
Nodes 1801 and 1802 receive D1 and D2 as inputs and NAN to D1 and D2 that they receive.
D operation is performed and the operation result is output to the node 1834. In other words, node 1834 goes high only when nodes 1801 and 1802 are both low. FETs 1830 and 1831 are shown in FIG.
Driven by the voltage converter in (b). FET 18
32 and 1833 are driven by the voltage converter of FIG. As a result, the ability to drive the main switching element can be enhanced, and high-speed operation can be performed at a low voltage.

(Embodiment 8) FIG. 19 is a circuit diagram of an eighth embodiment of a logic circuit according to the present invention. The operation of the logic circuit of the eighth embodiment will be described. When the node 1901 is at the H level, the FET 1903 is in the ON state and the FET 191
3 is an off state. Therefore, at this time, FET19
15 is in the on state and the FET 1905 is in the off state, so that the node 1931 is at the L level. The voltage generator 1904 generates the voltage Vs, the power supply 1981 supplies the power supply voltage Vdd, and the node 1901 receives the voltage Vdd.
Is given, the capacitor 1902 receives (Vd
It is charged by a voltage of d-Vs). FET191
The gate of 5 has a voltage of node 1901 (H level)
And a voltage (described later) due to the charges charged in the capacitor 1912 are given.

When the node 1901 is at the L level, the FET
1903 is in an off state, and FET 1913 is in an on state. Therefore, at this time, the FET 1915 is in the off state and the FET 1905 is in the on state, and as a result, the node 1931 becomes the H level. Voltage generator 191
4 generates the voltage Vs, and the power source 1981 outputs the power source voltage Vdd.
, And node 1901 is at ground level, capacitor 1912 is charged by a voltage of -Vs. The gate of the FET 1905 has a node 1
The sum of the voltage of 901 (L level) and the voltage due to the charges charged in the capacitor 1902 is given.

In any of the above cases, the gate of the FET in the ON state of the FETs 1905 and 1915 is applied with a voltage higher than Vdd, and the gate of the FET in the OFF state of the FETs 1905 and 1915 is connected to the ground. A voltage below the level is applied. As a result, the operating speed can be improved when operating at a low voltage. According to the eighth embodiment, the circuit structure is simplified and the chip area of the integrated circuit can be reduced.

The FETs used in the voltage converters of the logic circuits of the above-mentioned first to eighth embodiments are preferably SOIFETs. The reason will be described below. FIG.
0 is a diagram showing the structure of an N-channel MOSFET and its equivalent circuit. FIG. 21 shows a P-channel MOSFET
It is a figure which shows the structure and its equivalent circuit. Normal MO
As shown in FIGS. 20 and 21, the S transistor is
A junction capacitance Cj and a diode are formed between the drain and source and the back gate.

FIG. 22A is a diagram showing a part of the logic circuit of the first embodiment shown in FIG. 3, and FIG.
FIG. 23 is a diagram showing an equivalent circuit of FIG. After the voltage of Vdd is applied to the capacitor Cc, the capacitor Cc
It is assumed that among the terminals of c, the terminals without dots are pulled up to Vdd. Junction capacitance Cj and MOSFET
The gate voltage Vg after the electric charges are redistributed is calculated by the gate capacitance Cg of Charge Q = V in the initial state
After the ddCc is redistributed, the capacitor Cc
Charge (Vg-Vdd) Cc and capacity (Cg
It is equal to the sum of the charge Vg (Cg + 2Cj) stored in + 2Cj). That is, the following equation is obtained.

VddCc = (Vg-Vdd) Cc + Vg
(Cg + 2Cj) If this equation is solved for Vg, then Vg = 2CcVdd / (Cc + Cg + 2Cj) is obtained. That is, in the case of Cc >> Cg + 2Cj, the effect of the present invention can be obtained. On the contrary, when Cc <Cg + 2Cj, the effect is small. Therefore, it is necessary to set Cc so that Cc >> Cg + 2Cj. Junction capacitance C
The smaller j is, the larger the effect of the present invention is.

When the forward voltage of the diode is Vf,
When Vg ≧ Vdd + Vf, a current flows through the parasitic diode, and the voltage Vg is clamped at Vg = Vdd + Vf. As a result, the gate voltage Vg cannot be made higher than this clamped value.

By using the transistor having the SOI structure, the above-mentioned problems of junction capacitance and parasitic diode are solved. Therefore, the transistor having the SOI structure maximizes the effect of the present invention. FIG. 23 is a diagram showing structures of an N-channel transistor and a P-channel transistor having an SOI structure.

The reason why the logic circuit according to the present invention can operate at high speed will be described in more detail below. The drain current Id of the FET is generally expressed by the following equation.

Id = β (Vgs-Vt) ^α where α = 1.4 to 2.0, β is a constant, Vgs is a gate-source voltage, and Vt is a threshold voltage. The delay time τd of the circuit is expressed by the following equation.

Τd = γ · CL · Vdd / Id = γ · CL
Vdd / (β (Vgs-Vt) ^α ) where γ = proportional constant and CL = load capacitance.

The operating speed of the system using the logic circuit is 1
Assuming that it is proportional to / τd, the speed f of the system is
It is expressed by the following equation. For simplicity, α = 2.

F = 1 / τd = (β / (γ · CL))
((Vgs / Vdd) ² −2Vt (Vgs / Vdd) −
(Vt / Vdd) ² ) Here, Vgs = ηVdd, and η = 1 + Vov1 / V
If dd (> 1.0), then (Vt / Vdd) ²
Since <<< 1, it is expressed by the following equation.

F = (β / (γ · CL)) · (η ² −2V
t η) = β · η (η−2Vt) / (γ · CL) Therefore, in order to increase the operating speed of the system, it is necessary to increase η and reduce Vt.

On the other hand, the leak current Ileak when the transistor is off is expressed by the following equation.

Idleak = λw · 10 ^{(Vgs-Vt) / S} where λ = proportional constant and w = transistor gate width. S is about 70 mV.

Here, when Vgs = 0, the following equation is obtained.

Ileak = λw · 10 ^{(-Vt / S)} As can be seen from the above equation, in order to reduce the leak current Ileak, Vt must be increased.

In the present invention, η can be increased by increasing the voltage applied to the gate by the voltage converter, and the operating speed can be improved even with the normal Vt (about 0.5 V). . Further, when the main switching element is off, the gate is at the ground level, so that the leak current can be suppressed.

Further, in the third embodiment, when the main switching element is off, the gate voltage is-.
It is Vov2. At this time, the leak current Ileak is λ
w · 10 ^{(-Vov2-Vt / S)} . As a result, Vt is 0.3
Even if it is 5 V or less, -Vov2 is about -0.3 V, so that the leak current Ileak can be sufficiently suppressed. This means that a transistor with a lower Vt can be used as the main switching element. Therefore, the main switching device can be driven by the drive current increased by the small Vt,
As a result, the excellent effect that the operation speed of the logic circuit according to the present invention is increased can be obtained.

The effects when the logic circuit according to the present invention is applied to a transfer gate type switch will be described below. FIG. 24 (a) is a diagram showing a transfer gate type switch, and FIG. 24 (b) is a transfer gate drain-source conductance Gon.
FIG. 5 is a diagram showing V as a function of source voltage Vs. Of FIG. 24
In (b), Vtn and Vtp are threshold voltages of the N-channel FET and the P-channel FET, respectively. In the transfer gate type switch, the potentials of the source and drain are not fixed, as shown in FIG. Therefore, the source voltage may be equal to the power supply voltage Vdd. At this time, a voltage of (Vdd + Vt) or more is required to turn on the FET, and a voltage higher than that of a normal logic gate is required. FIG. 25 shows the drain-source conductance Go of the transfer gate when the source voltage Vs is low.
FIG. 5 shows n as a function of source voltage Vs. When the source voltage Vs becomes about 1.0 V, two complementary F
There is a region where both ETs do not turn on. The voltage converter of the logic circuit according to the present invention can output a voltage equal to or higher than the power supply voltage Vdd to the gate of the main switching element, and the threshold voltage V of the main switching element.
A deep reverse bias can be applied to Vgs even when t is low. As a result, high-speed operation at a low operating voltage is possible.

In the first to eighth embodiments, capacitors made of a ferroelectric material can be used as the voltage generator and the capacitors. FIG. 26 is a diagram showing the polarization of a capacitor using a ferroelectric material as an insulator as a function of applied voltage. The ferroelectric capacitor is shown in FIG.
It has polarization characteristics as shown in. When the voltage applied to the ferroelectric capacitor exceeds the coercive voltage Vc, spontaneous polarization occurs. As a result, the ferroelectric capacitor holds a constant voltage even if the voltage is not applied from the outside. Moreover, since the dielectric constant is extremely large, a large capacitance can be realized in a small area. Therefore, there is little voltage drop due to charge redistribution, and efficient operation can be realized when used in the logic circuit according to the present invention.

The performance of the logic circuit according to the present invention shown in FIG. 14 will be described below in comparison with the logic circuit according to the prior art.
FIG. 27 is a circuit diagram of a conventional logic circuit to be compared. 28 (a) and 28 (b) respectively show the voltage V of the conventional logic circuit at the rising edge of the output signal.
a and Vc and the voltages Va and V of the logic circuit of the present invention
It is a figure which shows c. 28 (c) and (d) are diagrams respectively showing the voltages Vb and Vc of the logic circuit of the prior art and the voltages Vb and Vc of the logic circuit of the present invention at the falling edge of the output signal. In FIGS. 28A to 28D, the power supply voltage Vdd is 1.0V. 28
Referring to (a), according to the conventional technique, the voltage Va is equal to the power supply voltage Vdd in the off state of the main switching element.
Lower by about 0.1V. As a result, a leak current flows when the main switching element is off. Further, when the main switching element is in the ON state, Va
Is -0.05V, it can be seen that the drive capacity is insufficient. In FIG. 28A, the gate delay time is 1.2 ns.

On the other hand, referring to FIG. 28B, according to the present invention, Va is equal to Vdd in the off state of the main switching element. Therefore, no leak current flows. Further, in the ON state of the main switching element, Va is −0.3V, so the drive capability is improved. In FIG. 28B, the gate delay time is 0.9 ns.

Referring to FIG. 28 (c), in the prior art, when the main switching element is in the off state,
Since Vb is 0.1 V, a leak current flows. When the main switching element is on, Vb is Vd
0.1V higher than d. Therefore, the drive capacity is
It is insufficient. The gate delay time is 1.0 ns.

On the other hand, referring to FIG. 28 (d), according to the present invention, since Vb is equal to 0 V in the off state of the main switching element, no leak current flows.
In the ON state of the main switching element, Vb is
It is 0.3 V higher than Vdd. As a result, the drive capacity is greatly improved. The gate delay time is 0.75 ns.

The performance of the logic circuit according to the present invention shown in FIG. 29 will be described below in comparison with the logic circuit according to the prior art.
FIG. 29 is a circuit diagram of a logic circuit according to the present invention. A conventional CMOS inverter is used as the logic circuit according to the conventional technique. In the logic circuit according to the present invention and the logic circuit according to the related art, 0.5 V is used as Vdd. FIG. 30A is a diagram showing the voltages Va and Vb of the logic circuit of the present invention at the rising edge of the output signal. FIG. 30B is a diagram showing the gate voltage Vg and the output signal Vout of the main switching element of the conventional logic circuit at the rising edge of the output signal. FIG. 30C is a diagram showing the voltages Va and Vb of the logic circuit of the present invention at the falling edge of the output signal. FIG. 30D is a diagram showing the gate voltage Vg and the output signal Vout of the main switching element of the conventional logic circuit at the falling edge of the output signal.

Referring to FIG. 30 (a), when the main switching element is in the off state, Va is more than 0.
Since it is 5V higher, it is well cut off. Further, in the ON state of the main switching element, Va is 0.3 V lower than the ground level, so the drive capability is improved. The gate delay time is 1.63 ns. On the other hand, as shown in FIG. 30B, the gate delay time is 5.6 ns according to the conventional technique.

Referring to (c) and (d) of FIG. 30, the gate delay time of the present invention is
It is smaller than the gate delay time of the prior art. Specifically, the gate delay time of the present invention is 1.88 ns, while the gate delay time of the prior art is 6.4 ns.

As can be seen from the above simulation results, according to the present invention, particularly in the low voltage region,
The operation speed can be improved.

In the first to eighth embodiments, the terminal of the capacitor not connected to the node receiving the input signal may be set to a potential other than Vdd or the ground level. For example, in the circuit of FIG.
In addition to 80, voltage generators 1313 and 1323 are provided. The voltage generated by voltage generators 1313 and 1323 is not limited to Vdd. In addition, the voltage generator 131
3 may be used as the ground, and the voltage generator 1323 may be used as the power supply 1380. That is, the contact connected to the negative electrode of the voltage generator 1313 may be connected to the ground, and the contact connected to the positive electrode of the voltage generator 1323 may be connected to the positive electrode of the power supply 1380.

In the logic circuit of the present invention, terminals other than the control terminal of the main switching element (that is, drain and source in the case of FET) may be pulled up, for example, if necessary. For example, in (a) of FIG.
The node 222 of the main switching element 220 is in a floating state, but may actually be pulled up to the power supply voltage Vdd. Alternatively, the nodes 222 and 223 may be used as output terminals without connecting the node 223 to the ground.

In the logic circuit of the present invention, the drain or source voltage of the FET included in the voltage converter becomes a forward voltage with respect to the substrate of the transistor, which is an undesired voltage, but the power supply voltage at which the present invention is effective. Is 1.
Since it will be 0 V or less, it is considered that the drain or source voltage does not go deep in the forward direction below this power supply voltage. It also controls the substrate potential of each transistor,
For example, it can be prevented by biasing the substrate (P well) of the P channel MOSFET to a potential higher than the power supply voltage and the substrate (P well) of the N channel MOSFET to a potential lower than the ground potential. It can also be prevented by using the SOI technique to float the substrate. Further, as the drain or source voltage becomes a forward voltage with respect to the substrate of the transistor, a certain amount of voltage is applied between the source and drain when the transistor forming the switch circuit is off, which may cause an off-leak current. However, since it is a transistor for switching and has a small gate width, the problem as in the conventional example is unlikely to occur, and it can be prevented by setting the threshold voltage Vt of the transistor forming the switch circuit high.

[0106]

The present invention has at least the following effects. That is, it is possible to realize a logic circuit which operates at high speed with a low power supply voltage and has a small leak current (that is, low power consumption). Therefore, the logic circuit according to the present invention is particularly effective for speeding up and reducing power consumption of a battery-powered portable device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a logic circuit 1 according to the present invention.

FIG. 2 is a circuit diagram of a first embodiment of a logic circuit according to the present invention.

FIG. 3 is a circuit diagram of a first embodiment of a logic circuit of the present invention realized by using an N channel FET and a P channel FET.

4 is node 3 of FIG. 3 in states I and II.
It is a figure which shows the voltage of 01-304.

5 is a circuit diagram of a logic circuit using a P-channel FET instead of the main switching element 220 of the circuit shown in FIG. 2A and a circuit diagram of a logic circuit in which two switches in this logic circuit are realized by FETs. Is.

FIG. 6 is a circuit diagram of a second embodiment of the logic circuit according to the present invention.

FIG. 7 is a circuit diagram of a second embodiment of the logic circuit of the present invention realized by using an N channel FET and a P channel FET.

8 is node 7 of FIG. 7 in states I and II.
It is a figure which shows the voltage of 01-704.

FIG. 9 is a circuit diagram of a third embodiment of the logic circuit according to the present invention.

FIG. 10 is a circuit diagram of a third embodiment of the logic circuit of the present invention realized by using an N-channel FET and a P-channel FET.

11 is a diagram showing voltages at nodes 1001-1005 of FIG. 10 in states I and II.

12 is a circuit diagram of a configuration suitable for use in place of the main switching element 1020 of FIG.

FIG. 13 is a circuit diagram of a fourth embodiment of the logic circuit according to the present invention.

FIG. 14 is a diagram showing four switches in the circuit of FIG.
It is a circuit diagram of a logic circuit realized by T.

FIG. 15 is a circuit diagram of a fifth embodiment of a logic circuit according to the present invention.

FIG. 16 is a diagram showing four switches in the circuit of FIG.
It is a circuit diagram of a logic circuit realized by T.

FIG. 17 is a circuit diagram of a sixth embodiment of the logic circuit according to the present invention.

FIG. 18 is a circuit diagram of a seventh embodiment of a logic circuit according to the present invention.

FIG. 19 is a circuit diagram of an eighth embodiment of the logic circuit according to the present invention.

FIG. 20 is a diagram showing a structure of an N-channel MOSFET and its equivalent circuit.

FIG. 21 is a diagram showing the structure of a P-channel MOSFET and its equivalent circuit.

22 is a diagram showing a part of the logic circuit of the first embodiment shown in FIG. 3 and a diagram showing an equivalent circuit of the part.

FIG. 23 is a diagram showing structures of an N-channel transistor and a P-channel transistor having an SOI structure.

FIG. 24 is a diagram showing a transfer gate type switch and a diagram showing a drain-source conductance Gon of the transfer gate as a function of a source voltage Vs.

FIG. 25 is a diagram showing the drain-source conductance Gon of the transfer gate when the source voltage Vs is low, as a function of the source voltage Vs.

FIG. 26 shows the polarization of a capacitor using a ferroelectric material as an insulator as a function of applied voltage.

FIG. 27 is a circuit diagram of a conventional logic circuit.

FIG. 28 is a diagram showing voltage waveforms of the logic circuit of the related art and the present invention at the rising and falling edges of the output signal.

FIG. 29 is a circuit diagram of a logic circuit according to the present invention.

FIG. 30 is a diagram showing voltage waveforms of the logic circuits of the related art and the present invention at the rising and falling edges of the output signal.

FIG. 31 is a circuit diagram of a conventional logic circuit.

[Explanation of symbols]

 1 Logic Circuit 10 Voltage Converter 11, 12, 14, 21, 22, 23 Node 13 Resistor 20 Main Switching Element

Claims (18)

[Claims] 1. A main switching means for changing a conduction state between at least two terminals according to a voltage applied to the control terminal and a voltage of an input terminal and outputting the converted voltage to the control terminal. And a voltage converting means for performing the voltage conversion. 2. The logic circuit according to claim 1, wherein the voltage conversion unit has a voltage generation unit and a sub-switching unit. 3. The logic circuit according to claim 2, wherein the sub-switching means has an SOI structure. 4. The voltage generating means includes at least one of a capacitor, a battery, and a ferroelectric.
The logic circuit according to the above. 5. The voltage conversion means controls the voltage higher than the voltage of the input terminal in the first state when the state of the input terminal that brings the main switching means into a conductive state is set to a first state. The logic circuit according to claim 2, which is supplied to a terminal. 6. The voltage converting means sets a voltage lower than the voltage of the input terminal in the second state when the state of the input terminal that brings the main switching means into the non-conducting state is set to the second state. The logic circuit according to claim 2, which is supplied to a control terminal. 7. The voltage is applied when the state of the input terminal that brings the main switching means into a conductive state is a first state and the state of the input terminal that brings the main switching means into a non-conductive state is a second state. The conversion means is the first
3. The logic circuit according to claim 2, wherein a voltage higher than the voltage of the input terminal is supplied to the control terminal in the state and a voltage lower than the voltage of the input terminal is supplied to the control terminal in the second state. 8. The voltage conversion means further includes a capacitor having a first terminal connected to the input terminal, and the sub-switching means connects the second terminal of the capacitor to the second terminal in the first state. It is connected to the control terminal of the main switching means, and in a state other than the first state, the second
The logic circuit according to claim 5, wherein a terminal is connected to the voltage generating means, and the control terminal of the main switching means is connected to the ground. 9. The voltage conversion means further includes a capacitor having a first terminal connected to the input terminal, and the sub-switching means connects the second terminal of the capacitor to the second terminal in the second state. Is connected to the control terminal of the main switching means, and in the states other than the second state, the first of the capacitors
7. The logic circuit according to claim 6, wherein a terminal is connected to the control terminal of the main switching means and the second terminal of the capacitor is connected to the ground. 10. The voltage conversion means further includes a first capacitor having a first terminal connected to the input terminal, and a second capacitor having a first terminal connected to the input terminal. In a state, the second terminal of the first capacitor is connected to ground, the second terminal of the second capacitor is connected to the control terminal of the main switching means, and in the second state, the second terminal of the first capacitor is connected. 8. The logic circuit according to claim 7, wherein the second terminal is connected to the control terminal of the main switching means, and the second terminal of the second capacitor is connected to the voltage generating means. 11. The logic circuit according to claim 8, wherein the main switching means includes an N-channel MOSFET. 12. The logic circuit according to claim 8, wherein the main switching means includes a P-channel MOSFET. 13. The logic circuit according to claim 9, wherein the main switching means includes an N-channel MOSFET. 14. The logic circuit according to claim 9, wherein the main switching means includes a P-channel MOSFET. 15. The logic circuit according to claim 10, wherein the main switching means includes an N-channel MOSFET. 16. The logic circuit according to claim 10, wherein the main switching means includes a P-channel MOSFET. 17. The logic circuit according to claim 10, wherein the main switching means is a complementary MOSFET. 18. Depending on the voltage applied to the control terminal,
First and second main switching means for changing a conduction state between at least two terminals, and a first voltage for converting a voltage of an input terminal and outputting the converted voltage to the control terminal of the first main switching means. A logic circuit comprising: a conversion means; and a second voltage conversion means for converting a voltage at the input terminal and outputting the converted voltage to the control terminal of the second main switching means, the logic circuit comprising: The voltage conversion means has a first terminal having first and second terminals.
A first capacitor, a second capacitor having first and second terminals, a first sub-switching means, and a first voltage generating means, and the first terminal of the first capacitor and the second capacitor of the second capacitor. The first terminal is connected to the input terminal, and the second voltage conversion means is a third terminal having first and second terminals.
A third capacitor, a fourth capacitor having first and second terminals, a second sub-switching means, and a second voltage generating means, and the first terminal of the third capacitor and the fourth capacitor The first terminal is connected to the input terminal via an inverter, and the first sub-switching means connects the second terminal of the first capacitor to ground in the first state, and connects the second terminal to the ground. Connecting the second terminal of the capacitor to the control terminal of the first main switching means, and connecting the second terminal of the first capacitor to the control terminal of the first main switching means in a second state, The second of the second capacitor
A terminal is connected to the first voltage generating means, and the second sub-switching means, in the second state,
Connecting the second terminal of the first capacitor to ground,
Connecting the second terminal of the second capacitor to the control terminal of the second main switching means, and in the first state,
A logic circuit connecting the second terminal of the first capacitor to the control terminal of the second main switching means and connecting the second terminal of the second capacitor to the second voltage generating means.