JPH09185886A - Data holding circuit - Google Patents

Abstract

(57) An object of the present invention is to speed up a read operation or a write operation at the time of driving at a low voltage and reduce a leak current to reduce power consumption. A memory cell (11) includes a first inverter (12) and a second inverter (13) whose one output node and the other input node are connected to each other, and first and second transistors (18, 19). Has been done. Each transistor 1 whose gate electrode is connected to the word line WL
8 and 19 are bit line pairs BL and / BL and storage nodes N
1 and N2, respectively. This data holding circuit is a means for increasing the power supply potential VCM of the memory cell 11 that drives the pair of inverters 12 and 13 higher than the power supply potential VCC applied to the peripheral circuit, or the ground potential that drives the pair of inverters 12 and 13. A means for lowering VSM to the ground potential VSS applied to the peripheral circuit is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data holding circuit, and more particularly to a static random access memory (=
The present invention relates to a data latch type data holding circuit such as SRAM).

[0002]

2. Description of the Related Art In recent years, there has been a demand for a semiconductor integrated circuit capable of low-voltage operation with a power supply voltage of about 1 V in order to meet the demand for portable electronic equipment. A problem in low voltage operation of a semiconductor integrated circuit is S
It is a latch-type data holding circuit such as a RAM memory cell.

For example, when the SRAM memory cell is operated at a low voltage, there is a problem that the word line is activated and the delay time when the bit line rises increases. A source line drive type memory cell that solves this problem is the 1995 S
ymposium on VLSI Circuits Digest of Technical Paper
s have been proposed.

A conventional data holding circuit will be described below with reference to the drawings based on the research report.

FIG. 6 is a circuit diagram of a low voltage drive type SRAM memory cell as a conventional data holding circuit. In FIG. 6, a memory cell 51 is one of a group of memory cells arranged in an array, and includes load transistors 52 and 53 made of PMOS, drive transistors 54 and 55 made of NMOS, and access transistors 56 and 5.
It is composed of 7.

A bit line pair B that enables access to the memory cells 51 in the column direction of the memory cell array.
When activated, L and / BL are applied to the power supply potential VCC.

The word line WL that enables access to the memory cells 51 in the row direction of the memory cell array is connected to the gate electrodes of the access transistors 56 and 57.

The source line SL for driving the sources of the drive transistors 54 and 55 is a drive transistor 54,
55 to the common source electrode.

A first node N11 and a second node N1
2 holds opposite potentials to each other, and the held data is determined according to the latch states of the first and second nodes N11 and N12. For example, if the potential of the first node N11 is high, the potential of the second node N12 is low. That is, when the potential of the first node N11 is high and the potential of the second node N12 is low,
Since the gate electrodes of the load transistor 52 and the drive transistor 54 are both connected to the second node N12, the load transistor 52 turns on and the drive transistor 54 turns off. In addition, the gate electrodes of the load transistor 53 and the drive transistor 55 are the first
, The load transistor 53 is turned off and the drive transistor 55 is turned on. Therefore, the high data continues to be held in the first node N11 and the low data continues to be held in the second node N12.

When the memory cell 51 is selected by an external address during the read operation, the word line WL connected to the memory cell 51 is supplied with the power supply potential VCC.
Since the source line SL is applied to a negative potential of about -0.5V while being applied to a high potential of (about 1V),
The first node N11 and the bit line BL are connected, and the second
Node N12 and bit complementary line / BL are connected.
At this time, since the bit line pair BL, / BL is precharged to the high potential which is the power supply potential VCC, nothing happens on the side of the first node N11 holding the high data, but the low data is held. On the side of the second node N12 which is connected to the source line S from the bit complementary line / BL via the access transistor 57 and the drive transistor 55.
A current is drawn to L, and the drawn current is detected by a sense amplifier or the like as a current difference or a potential difference flowing through the bit line pair BL, / BL, and is transferred to the outside as data.

Generally, in a memory cell having a small power supply potential VCC, the difference between the power supply potential VCC and the threshold voltage of the transistor is small and the drive current is small.
Although the transistor does not operate at high speed, the low voltage drive type SRAM memory cell of this report has a source line S connected to the source electrodes of the drive transistors 54 and 55.
Since the potential of L is applied so as to be lower than the ground potential, the gate-source voltage of the drive transistor 55 expands and the current driving capability of the drive transistor 55 increases, so that the drive transistor 55 operates at high speed.

[0012]

However, in the conventional low voltage drive type SRAM memory cell, although the read current is increased and the read speed is increased, the negative voltage for driving the source line SL is changed to the negative voltage inside the chip. When the voltage is supplied using the generation circuit, it is difficult to efficiently generate a negative voltage under a low voltage condition of 1 V or less, the power consumption required for driving the source line increases, and the power consumption of the entire chip decreases. I had the problem of not doing it.

Further, in the commonly used twin-well structure, the NMOS well cannot be separated from other NMOS wells, so it is impossible to selectively control the NMOS well potential. When a negative voltage is applied to the source line SL, forward bias is applied to the PN junction between the source and the well, so the source potential cannot be lowered to -0.7V or lower. Considering the breakdown voltage of noise and the like, the lower limit of the source potential is further increased, so that the gate-source voltage of the drive transistor cannot be sufficiently expanded, and there is a limit to the speedup.

It is an object of the present invention to solve the above-mentioned conventional problems and to speed up the read operation or the write operation and reduce the power consumption when driving at a low voltage.

[0015]

In order to achieve the above-mentioned object, the present invention increases the drivability of only a transistor which is required to operate at high speed when driven at a low voltage.
It is intended to achieve both high-speed operation and low power consumption.

Specifically, the solution means taken by the invention of claim 1 is that the data holding circuit comprises a first inverter and a second inverter in which one output node and the other input node are connected to each other. A data holding unit is provided, and a power supply potential applied to the data holding unit during a data reading period is set to be higher than a power supply potential applied to a peripheral circuit of the data holding unit. Is.

According to the structure of claim 1, the power supply potential applied to the data holding unit during the data reading period is set to be higher than the power supply potential applied to the peripheral circuit of the data holding unit. , If the first and second inverters are composed of CMOSFETs, the gate-source voltage of the N-type drive transistor increases during the read period.

According to a second aspect of the present invention, there is provided a data holding circuit comprising a data holding unit including a first inverter and a second inverter, one output node and the other input node of which are connected to each other. And a power supply potential applied to the data holding unit during a data reading period is set to be higher than a power supply potential applied to the data holding unit during a data writing period. is there.

According to the structure of claim 2, the power supply potential applied to the data holding unit during the data reading period is set to be higher than the power supply potential applied to the data holding unit during the data writing period. Therefore, when the first and second inverters are composed of CMOSFETs, the gate-source voltage of the N-type drive transistor increases during the read period.

According to a third aspect of the present invention, there is provided a data holding circuit, wherein a data holding circuit comprises a first inverter and a second inverter having one output node and the other input node connected to each other. And a data read line for reading data from the data holding unit, the data read line is row-precharged, and the ground potential applied to the data holding unit during the data reading period is the data holding unit. The configuration is such that it is set to be lower than the ground potential applied to the peripheral circuit of.

According to the structure of claim 3, the data read line is row precharged, and the ground potential applied to the data holding section during the data read period is the ground potential applied to the peripheral circuit of the data holding section. Since it is set to be lower than the
In the case of a MOSFET, the gate-source voltage of the P-type drive transistor increases during the read period.

According to a fourth aspect of the present invention, there is provided a data holding circuit in which a data holding unit is composed of a first inverter and a second inverter having one output node and the other input node connected to each other. And a data read line for reading data from the data holding unit, the data read line is pre-charged with a row, and the ground potential applied to the data holding unit during the data reading period is the data writing period. And is set to be lower than the ground potential applied to the data holding unit.

According to the configuration of claim 4, the data read line is row precharged, and the ground potential applied to the data holding unit during the data reading period is the ground potential applied to the data holding unit during the data writing period. Since it is set to be lower than the potential, when the first and second inverters are composed of CMOSFETs,
The gate-source voltage of the P-type drive transistor increases during the read period.

According to a fifth aspect of the present invention, a data holding circuit is provided with a data holding unit including a first inverter and a second inverter whose one output node and the other input node are connected to each other. The power supply potential applied to the data holding unit during the data writing period is set to be lower than the power supply potential applied to the peripheral circuit of the data holding unit.

According to the structure of claim 5, the power supply potential applied to the data holding unit during the data writing period is set to be lower than the power supply potential applied to the peripheral circuit of the data holding unit. When the first and second inverters are composed of CMOSFETs, the data latching capability of the drive transistor of the high-side data holding unit is reduced during the writing period.

According to a sixth aspect of the present invention, there is provided a data holding circuit in which a data holding unit is composed of a first inverter and a second inverter in which one output node and the other input node are connected to each other. And a power supply potential applied to the data holding unit during a data writing period is set to be lower than a power supply potential applied to the data holding unit during a data reading period. is there.

According to the structure of claim 6, the power supply potential applied to the data holding unit during the data writing period is set to be lower than the power supply potential applied to the data holding unit during the data reading period. Therefore, when the first and second inverters are composed of CMOSFETs, the data latching capability of the drive transistor of the data holding unit on the high side decreases during the writing period.

According to a seventh aspect of the present invention, there is provided a data holding circuit in which a data holding unit is composed of a first inverter and a second inverter in which one output node and the other input node are connected to each other. And a ground potential applied to the data holding unit during a data writing period is set to be higher than a ground potential applied to a peripheral circuit of the data holding unit.

According to the structure of claim 7, the ground potential applied to the data holding portion during the data writing period is set to be higher than the ground potential applied to the peripheral circuit of the data holding portion. When the first and second inverters are composed of CMOSFETs, the data latching ability of the drive transistor of the data holding unit on the row side becomes large.

According to another aspect of the present invention, there is provided a data holding circuit, comprising a data holding unit including a first inverter and a second inverter whose one output node and the other input node are connected to each other. And a ground potential applied to the data holding unit during a data writing period is set to be higher than a ground potential applied to the data holding unit during a data reading period. is there.

According to the structure of claim 8, the ground potential applied to the data holding portion during the data writing period is set to be higher than the ground potential applied to the data holding portion during the data reading period. Therefore, when the first and second inverters are composed of CMOSFETs, the data latching capability of the drive transistor of the data holding unit on the row side increases during the writing period.

According to a ninth aspect of the present invention, there is provided a data holding circuit, comprising: a data holding circuit, a first inverter having an output node on one side and an input node on the other side connected to each other, each including a P-type transistor and an N-type transistor. A second inverter, and the well potential of the P-type transistor during a data read period is equal to the P-type transistor during a data write period.
The configuration is such that it is set to be lower than the well potential of the type transistor.

According to the structure of claim 9, P in the reading period
Since the well potential of the P-type transistor is set to be lower than the well potential of the P-type transistor in the writing period, when the data read line for reading data from the data holding unit is high precharged, it is caused by the substrate bias effect. Since the threshold voltage of the P-type load transistor in the read period becomes small, the driving capability of the load transistor becomes large. As a result, the driving capability of the N-type drive transistor during the read period increases.

Further, even when the read line is row precharged, the threshold voltage of the P-type drive transistor decreases due to the substrate bias effect, so that the drive capability of the drive transistor increases.

According to a tenth aspect of the present invention, a data holding circuit is configured such that one output node and the other input node are connected to each other, and a P-type transistor and an N-type are respectively provided.
A first inverter and a second inverter each of which is formed of a transistor, and is set such that the well potential of the N-type transistor during a data read period is higher than the well potential of the N-type transistor during a data write period. It is configured as described above.

According to the structure of the tenth aspect, the well potential of the N-type transistor in the read period is set to be lower than the well potential of the N-type transistor in the write period, so that data read from the data holding unit is performed. When the line is highly precharged, the threshold voltage of the N-type drive transistor is reduced due to the substrate bias effect, and the drive capability of the drive transistor during the read period is increased.

Further, even when the read line is row precharged, the threshold voltage of the N-type load transistor decreases due to the substrate bias effect, so that the driving capability of the load transistor increases. As a result, the driving capability of the P-type drive transistor during the read period increases.

According to another aspect of the present invention, there is provided a data holding circuit in which one output node and the other input node are connected to each other, and a P-type transistor and an N-type transistor are provided, respectively.
A first inverter and a second inverter each of which is composed of a P-type transistor, and is set such that a well potential of the P-type transistor in a data writing period is lower than a well potential of the P-type transistor in a data reading period. It is configured as described above.

According to the structure of claim 11, the well potential of the P-type transistor in the writing period is set to be lower than the well potential of the P-type transistor in the reading period, so that the P-type transistor in the writing period is caused by the substrate bias effect. Since the threshold voltage of the transistor decreases, the driving capability of the transistor increases.

According to a twelfth aspect of the present invention, a data holding circuit is configured such that one output node and the other input node are connected to each other, and a P-type transistor and an N-type transistor are provided, respectively.
A first inverter and a second inverter each of which is composed of a P-type transistor, and is set such that a well potential of the P-type transistor in a data writing period is higher than a well potential of the P-type transistor in a data reading period. It is configured as described above.

According to the twelfth aspect, the well potential of the P-type transistor in the writing period is set to be higher than the well potential of the P-type transistor in the reading period, so that the P-type transistor in the writing period is caused by the substrate bias effect. The threshold voltage of the transistor increases.

According to a thirteenth aspect of the present invention, a data holding circuit is configured such that one output node and the other input node are connected to each other, and a P-type transistor and an N-type transistor are provided, respectively.
A first inverter and a second inverter each of which is formed of a transistor of the N-type, and is set such that the well potential of the N-type transistor in the data writing period is lower than the well potential of the N-type transistor in the data reading period. It is configured as described above.

According to the thirteenth aspect, the well potential of the N-type transistor in the writing period is set to be lower than the well potential of the N-type transistor in the reading period, so that the N-type transistor in the writing period is caused by the substrate bias effect. The threshold voltage of the transistor increases.

According to a fourteenth aspect of the present invention, there is provided a data holding circuit comprising a first inverter and a first inverter each having a P-type transistor and an N-type transistor in which one output node and the other input node are connected to each other. 2 inverters, and the well potential of the N-type transistor during the data writing period is equal to the N-type transistor during the data reading period.
The configuration is such that it is set higher than the well potential of the type transistor.

According to the structure of claim 14, the well potential of the N-type transistor in the writing period is set to be higher than the well potential of the N-type transistor in the reading period, so that the N-type in the writing period is caused by the substrate bias effect. Since the threshold voltage of the transistor decreases, the driving capability of the transistor increases.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an SRAM memory cell as a data holding circuit according to the first embodiment of the present invention and its peripheral circuits, and FIG. 2 is an SRAM memory according to the first embodiment of the present invention. It is a circuit diagram which shows a cell. In FIG. 1, a memory cell 11 is one of the memory cells arranged in an array. The ground potential VSS and the power supply potential VCC are applied to a row decoder that selects a word line based on a row address input from the outside, and the memory cell 11 arranged in the row direction is connected by a word line WL. There is. The I / O system circuit controls the read operation and the write operation, and the decoder circuit that decodes the column address input from the outside is connected to the memory cells 11 arranged in the row direction and the bit line pair BL as a data read line. It is connected by / BL. The sense amplifier circuit is a circuit that amplifies a minute read current read to the bit line pair BL, / BL during a read operation. The power supply potential VCM of the memory cell that drives the memory cell 11 is a power supply potential for holding high data that is controlled independently of the power supply potential VCC of the peripheral circuits such as the row decoder, and the ground potential VSM of the memory cell is the row decoder. Is a ground potential for holding row data, which is controlled independently of the ground potential VSS of peripheral circuits such as.

As shown in FIG. 2, the memory cell 11 is composed of a first inverter 12, a second inverter 13, a first access transistor and a second access transistor. For example, the bit line pair BL, / BL for accessing the memory cell 11 in the column direction of the memory cell array is composed of the switch transistors 20, 21.
Assuming that the first inverter 12 is precharged to the ground potential VSS while being activated by the power supply potential PRE, the configuration of the first inverter 12 is as follows: The NMOS transistor shown becomes the first load transistor. In the configuration of the second inverter 13 paired with the first inverter 12, the PMOS transistor indicated by the reference numeral 15 serves as the second drive transistor, and the NMOS transistor indicated by the reference numeral 17 serves as the second load transistor.

The output node of the first inverter 12 serving as the first storage node N1 of the memory cell 11 has the second drive transistor 15 and the second load transistor 17 which are the input nodes of the second inverter 13, respectively. It is connected to the gate electrode. The output node of the second inverter 13, which is the second storage node N2 of the memory cell 11, is the input node of the first inverter 12, which is the first drive transistor 14 and the first load transistor 1.
6 to each gate electrode. The word line WL that enables access to the memory cells 11 in the row direction of the memory cell array is the gate of the first access transistor 18 connected between the bit line BL and the first storage node N1. The gate electrode of the second access transistor 19 connected between the electrode and the bit complementary line / BL and the second storage node N2 is connected thereto.

The data held by the first storage node N1 and the second storage node N2 is determined according to the latch states of the first storage node N1 and the second storage node N2,
The first storage node N1 and the second storage node N2 hold opposite potentials. For example, if the potential of the first storage node N1 is high, the potential of the second storage node N2 is low. When the potential of the first storage node N1 is high and the potential of the second storage node N2 is low, the gate electrodes of the first drive transistor 14 and the first load transistor 16 are both in the second storage node. Since it is connected to the node N2, the first drive transistor 14 is on and the first load transistor 16 is off. Also, the second drive transistor 1
Since the gate electrodes of the fifth load transistor 17 and the second load transistor 17 are connected to the first storage node N1, the first drive transistor 15 is turned off and the second load transistor 17 is turned on. Therefore, the high data continues to be held in the first storage node N1 and the low data continues to be held in the second storage node N2.

Next, during the read operation, when the memory cell 11 is selected from the memory cell array by the address designating a single memory cell, the word line WL connected to the selected memory cell 11 is supplied with the power supply potential VCC. Therefore, the first storage node N1 is connected to the bit line BL, and the second storage node N2 is connected to the bit complementary line / BL. At this time, since the bit line pair BL, / BL is precharged to the low potential which is the ground potential VSS, nothing happens on the side of the second storage node N2 holding the row data, but high data is output. On the side of the held first node N1, the read current ICM flows into the bit line BL via the first access transistor 18 and the first drive transistor 14. This read current ICM is the bit line pair BL, /
It is detected by the sense amplifier as a current difference or a potential difference flowing through BL, and is transferred to the outside as desired data.

To increase the data transfer rate during the read operation, the first access transistor 18, the second access transistor 19 and the first drive transistor 14 are used.
It is only necessary to increase the drive capability of one of the second drive transistor 15 and the second drive transistor 15.

The drivability of the transistor can be increased by increasing the transistor size. However, increasing the transistor size also increases the memory cell area in proportion to the increase in transistor size, making it difficult to increase the transistor size. Further, lowering the threshold voltage of the transistor is also effective in increasing the driving ability of the transistor.
However, when the threshold voltage of the transistor is lowered, the influence of process variation on the threshold voltage increases, which causes problems such as an extreme increase in leak current and a decrease in noise margin.

The data holding circuit according to the first embodiment is
The power supply potential VCM of the memory cell, which is the source of the first drive transistor 14 and the second drive transistor 15 forming the memory cell 11, is set to the power supply potential V of the peripheral circuit.
By setting it higher than CC, the driving ability of each drive transistor 14, 15 is increased.

For example, the first drive transistor 14
The read current ICM supplied through the first drive transistor 14 depends on the gate-source potential of the first drive transistor 14. The larger the gate-source potential, the larger the read current ICM, and thus the read speed becomes faster. On the contrary, when the power supply potential VCM of the memory cell is supplied to the required minimum level in order to achieve the target operation speed, unnecessary consumption current does not increase, and the first drive transistor and the first drive transistor The size of the second drive transistor can be reduced.

Further, the first load transistor 16 and the second load transistor 17 which constitute the memory cell 11
If the ground potential VSM of the memory cell, which is the power source of the first drive transistor 14, is set to a potential lower than the normal ground potential VSS, the voltage applied to the gate electrode of the first drive transistor 14 becomes small, so that the first drive transistor Since the gate-source potential of 14 is expanded, the read current I
The value of CM can be increased. Further, by setting the ground potential VSM of the memory cell to a potential lower than the normal ground potential VSS, the drive capability required for each load transistor 16 and 17 can be realized even with a small-sized transistor, so that the memory cell can be realized. The area can be reduced.

The power supply potential VCM of the memory cell is set higher than the power supply potential VCC of the peripheral circuit, and the ground potential VSM of the memory cell is set to the normal ground potential VSM.
Since the setting to be lower than SS can be performed independently of each other, any one of them may be configured.

When the precharge potential of the bit line pair BL, / BL is high potential, the first load transistor 16 and the second load transistor 17 act as each drive transistor, and the first drive transistor 14 And the second drive transistor 15 acts as each load transistor. Therefore, the bit line pair BL, / B
Similar to the case where the L precharge potential is low,
Power supply potential V of the memory cell applied to the load transistor
If CM is set higher than the power supply potential VCC to set the potential difference applied to the sources of the respective transistors to be large, the read speed can be increased without increasing the area of the memory cell 11. .

Further, since the drive capability of the drive transistor is stronger than the access transistors 18 and 19 without increasing the transistor size, the threshold voltage of the access transistors 18 and 19 can be lowered. It is also possible to increase the drive capability of each access transistor 18 and 19 without increasing the area of the memory cell 11. In this case, there is a concern that a leak current may flow into the memory cell 11 via the access transistors 18 and 19 during standby, but during standby, the ground potential VSM of the memory cell and the precharge potential of the bit line BL may be the gate of the access transistor. If the potential is set higher than the potential (= the potential of the word line WL), a negative voltage is applied between the gate and the source of the access transistors 18 and 19 which are NMOS transistors, so that the leak current is suppressed. be able to.
Regarding the relative potential relationship between the word line WL and the ground potential VSM of the memory cell and the bit line BL, it suffices that the potential of the word line WL is lower than the ground potential VSM of the memory cell and the potential of the bit line BL during standby. , Even if the word line WL is controlled, the ground potential VSM of the memory cell or the bit line B
The potential of L may be controlled.

By the way, as long as the power supply potential VCM of the memory cell applied to the memory cell 11 is a potential at which the writing operation is possible, the power supply potential VCM is not always limited to the reading operation, but is constantly higher than the power supply potential VCC of the peripheral circuit or the like. It is possible to keep it high.

Hereinafter, the operation in each of the case where the bit line of the memory cell is high precharged and the case where it is row precharged will be verified.

FIG. 3 shows the SR according to the first embodiment of the present invention.
FIG. 6 is a diagram comparing operating speeds related to a high or low precharge potential of a bit line of an AM memory cell.

FIG. 3A is an equivalent circuit diagram of the memory cell on the read side when the bit line is high precharge, and FIG. 3C is the memory cell on the read side when the bit line is row precharge. It is an equivalent circuit diagram.

The memory cell equivalent circuit shown in FIG.
When the bit line BL is in high precharge, the first storage node N1 holds row data and the read current I of each transistor in the memory cell of the SRAM is read.
It represents a transistor through which CM flows. FIG. 3 (a)
In the memory cell equivalent circuit shown in, the drive transistor when the bit line BL is in high precharge is an NMOS transistor indicated by reference numeral 26 whose source is connected to the ground potential. When the power supply potential VCC is applied to the word line WL and the read operation is started for the memory cell, the charge charged in the bit line BL is discharged through the access transistor 28 and the drive transistor 26, and the bit line BL is discharged. Potential drops. At this time, the source of the access transistor 28 is the first storage node N1 and the capacitance of the bit line BL is overwhelmingly larger than that of the first storage node N1. Therefore, depending on the conductance ratio of the access transistor 28 and the drive transistor 26, Since the potential of the first storage node N1 rises, the gate-source potential of the access transistor 28 is lowered, and the drive capability of the access transistor 28 is lowered.

The memory cell equivalent circuit shown in FIG.
When the bit line BL is row precharged, the first storage node N1 holds high data and the read current I of each transistor in the memory cell of the SRAM is read.
It represents a transistor through which CM flows. Figure 3 (c)
In the memory cell equivalent circuit shown in, the drive transistor when the bit line BL is row precharged has a source connected to the power supply potential VCM of the memory cell by a reference numeral 24.
Is a PMOS transistor shown in FIG. When the power supply potential VCC is applied to the word line WL and the read operation is started for the memory cell, the bit line BL is charged through the access transistor 28 and the drive transistor 24, and the potential of the bit line BL is changed. To rise. At this time,
Since the source of the access transistor 28 is connected to the bit line BL, the drive capability of the access transistor 28 immediately after the start of the read operation is large. As the potential of the bit line BL rises, the drive capability of the access transistor 28 gradually decreases, and when the potential of the bit line BL rises from the high potential of the word line WL to a potential lower by the threshold voltage of the access transistor 28, The drive capability of the access transistor 28 is lost and the read current stops flowing.

FIG. 3B is a graph showing the result of simulating the relationship between each voltage of the word line WL, the bit line BL and the first memory node N1 and the time when the bit line BL is in high precharge. Yes, FIG. 3 (d)
Is the word line W when the bit line BL is row precharge
7 is a graph showing the results of simulating the respective relationships between the voltages of L, the bit line BL, and the first storage node N1 and time.

Comparing immediately after the word line WL is activated and the read operation for the memory cell is started, as shown in FIG. 3B, when the bit line BL is high precharged, the source of the access transistor is Therefore, the first storage node N1 becomes higher than the ground potential by about 0.2V, and the gate-source voltage of the access transistor 28 becomes small. On the other hand, as shown in FIG. 3D, when the bit line BL is row precharged, since the source of the access transistor 28 is the bit line BL, the gate-source voltage of the access transistor 28 is high precharged. It will be bigger than the case.

Therefore, when the time when the potential difference between the bit line pair BL and / BL becomes 100 mV is represented as the read time tMA, the read time tMA in the case of row precharge shown in FIG. It is faster than the read time tMA in the case of high precharge shown in b).
Incidentally, although it depends on the configuration of the sense amplifier, the potential difference between the senseable bit line pair BL, / BL is usually several tens mV.

Further, as shown in FIG. 3D, after a lapse of time from the start of the read operation, the potential of the bit line BL which is the source changes, and the gate-source potential of the access transistor 28 changes to the access transistor 28. Since the charging / discharging of the bit line BL is stopped when the voltage drops to the threshold voltage of, the unnecessary charging / discharging current flowing out to the bit line can be reduced without newly providing a control circuit.

When the access transistor 28 shown in FIGS. 3 (a) and 3 (c) is a PMOS transistor, contrary to the above, in the case of high precharge,
Since the source of the access transistor 28 is the bit line BL, the gate-source voltage of the access transistor 28 is larger than that in the case of row precharge. Therefore, the read time tMA in the case of high precharge is faster than the read time tMA in the case of row precharge.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

In the first embodiment described above, the power supply potential VCM of the memory cell applied to the drive transistor is set to be high in order to increase the read speed. If it is large, the time required to invert the data increases, and in some cases, the data cannot be inverted.

Therefore, in the present embodiment, the power supply potential VCM of the memory cell is lowered during the write operation,
Increase the writing speed.

FIG. 4 is a control sequence diagram of the SRAM as the data holding circuit according to the second embodiment of the present invention. In FIG. 4, WL indicates the potential applied to the word line, VCM indicates the power source potential of the memory cell, and BL, /
BL indicates the potential applied to the bit line pair, and N1, N2
Indicates the potentials of the first and second storage nodes. VS
S is the ground potential of the peripheral circuit, and VCC is the power supply potential supplied to the peripheral circuit. Also, the power supply potential VCM of the memory cell
The low potential side is set to VCC and the high potential side is set to VCMH. The data holding circuit according to the second embodiment is similar to that shown in FIG.
The SRAM memory cell shown in FIG.

As shown in FIG. 4, the first operation before the read operation is performed.
The electric potentials of the storage node N1 and the second storage node N2 are complementary to each other, and if one is the power supply potential VCC, the other is the ground potential VSS.

First, the read period will be described. Immediately before the read operation is started, the power supply potential VCM of the memory cell is boosted to the high potential VCMH, and the storage node holding the high data rises to the high potential VCMH. When the word line WL is activated and the read operation is started, the potential of the storage node holding the high data temporarily drops, but as described in the first embodiment, the drive capability of the drive transistor is reduced. Because it is increased, the voltage drop does not erase the data. When the read operation is completed, the power supply potential VCM of the memory cell is stepped down from the high potential VCCH to the power supply potential VCC, and the potentials of the first storage node N1 and the second storage node N2 also become the power supply potential VCC and the ground potential VSS. Return.

Next, the writing period will be described. When the word line WL is activated and the write operation is started, when the held data is different from the write data, it is called reverse writing, and the voltage drop on the high side of the storage node and the low side of the storage node are called. The voltage rises at the same time. During the write operation, since the power supply potential VCM of the memory cell is lowered to the power supply potential VCC lower than the high potential VCMH, the drive capability of the drive transistor is also small, and the voltage drop amount on the high side of the storage node is large. Therefore, the potentials of the storage nodes are exchanged, and the data is written correctly.

In the second embodiment, the power supply potential VCM of the memory cell is high potential VCM during the read period.
The voltage is boosted to H and lowered to the power supply potential VCC which is lower than the high potential VCMH in the writing period. However, the memory cell 11 is not limited to this, and the power supply potential VCC is applied in the reading period and is higher than the power supply potential VCC in the writing period. The same effect can be obtained even if a potential reduced to a low potential is applied.

Regarding the power supply potential VCM of the memory cell 11 in the standby state, the gate-source potential of the transistor serving as the leak source is 0 V, so that the value of the power supply potential VCM of the memory cell is higher than the normal power supply potential VCC. The leakage current does not increase even at a high potential VCMH. Further, when the power supply potential VCM of the memory cell in the standby state is set to be high, it is less likely to be affected by noise such as soft error, so that the data retention characteristic is improved.

As shown in FIG. 4, the power supply potential VCM of the memory cell is boosted from the power supply potential VCC to the high potential VCMH before the read period is started, and before the write period is started. Power supply potential VC of memory cell
M is stepped down from the high potential VCMH to the power supply potential VCC. This is an example for the purpose of surely ending the read operation or the write operation within each period, and it is not always necessary to change the voltage before the start of each period.

The writing ability can also be improved by setting the ground potential VSM of the memory cell to be high during the writing period. When the access transistors 18 and 19 are NMOS transistors, the low level of the bit line BL is the memory cell 11.
Writing is performed by destroying the high data of the memory cell 11. However, as described in the first embodiment, the read current of the memory cell 11 is increased so much that even if 0V is applied to the bit line BL, Data retention is so high that high data cannot be destroyed. Therefore, by increasing the ground potential VSM of the memory cell during the write operation, the data holding power is weakened and the ground potential VSM of the memory cell is boosted to the extent that writing is possible. This will be described with reference to FIG.

First, it is assumed that high data is held in the first storage node N1. Now, the power supply potential VCC is applied to the word line WL, and the access transistors 18, 1
When 9 is turned on and a low potential is applied to the bit line BL and a high potential is applied to the bit complementary line / BL, the potential of the first storage node N1 is pulled to the bit line BL and drops. If the power supply potential VCM is high, the potential of the first storage node N1 does not drop to a level sufficient to invert the inverter 13, and thus writing is not completed.

Therefore, when the ground potential VSM of the memory cell is raised, the potential at which the inverter 13 is inverted is increased and the potential of the second storage node N2 is the ground potential VSM of the memory cell. Since the gate potential of the first drive transistor 14 increases, the current flowing through the first drive transistor 14 decreases, and the potential of the first storage node N1 also decreases. Therefore,
By increasing the ground potential VSM of the memory cell, the write level (the potential of the bit line BL at which the data held in the memory cell 11 can be inverted) becomes large, and the write operation is speeded up.

Of course, the voltage value of the ground potential VSM of the memory cell in the standby state is not limited as long as it can hold the data, but by matching with the write operation, the negative voltage is not applied to the word line WL. However, since the low threshold access transistors 18 and 19 can be used (if the potential of the bit line BL is higher than that of the word line WL in the off state, the gate-source voltage of the access transistors 18 and 19 becomes negative). Therefore, a faster read operation can be expected.

Thus, for example, the power supply potential VCM of the memory cell is constantly set to be higher than the power supply potential VCC of the peripheral circuit, while the ground potential VSM of the memory cell is set to the peripheral circuit during the write operation and the standby. Ground potential V
It is set to be higher than SS, and the ground potential VSM of the memory cell is set to the ground potential VS only during the read operation.
If S is set and a low threshold transistor is used as the access transistors 18 and 19, both high speed of data reading and low leak characteristics at the time of write operation and standby can be achieved.

If the access transistors 18 and 19 are PMOS transistors, the memory cell 1
Since the write operation is performed by inverting the row data held at 1 at the high level of the bit line BL, the ground potential VSM of the memory cell during the write operation is boosted as compared with the read operation, or the memory cell Power supply potential V
A high-speed write operation can be realized depending on whether the voltage of CM is stepped down. Also in this case, the power supply potential VCM of the memory cell in the standby state is set to be lower than the potential (= VCC) of the word line WL in the OFF state as in the write operation, so that the access transistors 18 and 19 are set. Even if a low threshold transistor is used, leakage current can be suppressed.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a circuit diagram showing an SRAM memory cell as a data holding circuit according to the third embodiment of the present invention. In FIG. 5, a memory cell 41 is one of a group of memory cells arranged in an array, and includes a first inverter 42, a second inverter 43, a first access transistor 18 and a second access transistor 19. It consists of When the precharge potential of the bit line BL is a low potential, the first inverter 42 is
It is composed of a first drive transistor which is a PMOS transistor shown by 4 and a first load transistor which is an NMOS transistor shown by 46. Second inverter 43 paired with first inverter 42
Is composed of a second drive transistor which is a PMOS transistor shown by reference numeral 45 and a second load transistor which is an NMOS transistor shown by reference numeral 47.

The output node of the first inverter 42, which is the first storage node N1 of the memory cell 41, has the second drive transistor 45 and the second load transistor 47, which are the input nodes of the second inverter 43, respectively. It is connected to the gate electrode. The output node of the second inverter 43, which is the second storage node N2 of the memory cell 41, has the first drive transistor 44 and the first load transistor 4 which are the input nodes of the first inverter 42.
6 to each gate electrode. The word line WL that enables access to the memory cells 41 in the row direction of the memory cell array is the gate of the first access transistor 18 connected between the bit line BL and the first storage node N1. The gate electrode of the second access transistor 19 connected between the electrode and the bit complementary line / BL and the second storage node N2 is connected thereto.

The first drive transistor 44 and the second
Each substrate of the drive transistor 45 of the first load transistor 4 is connected to the first well potential VNW.
Each substrate of 6 and the second load transistor 47 is connected to the second well potential VPW.

As described in the first embodiment, it is effective to lower the threshold voltage of the transistor in order to increase the read speed for the memory cell without increasing the area of the memory cell. This configuration could not be used because the leakage current at that time increases.

In the present embodiment, by controlling the well potential of each transistor constituting the memory cell 41, the threshold voltage of each transistor during the read operation or the write operation and the threshold value of each transistor in the standby state are controlled. The value voltage and the voltage are dynamically changed by using the substrate bias effect.

A large drive capacity is required for the first drive transistor 44 and the second drive transistor 45 during a read operation, but on the contrary, a large drive capacity is not required during a write operation, so that the drive transistors 44 and 45 have a large drive capacity. The first well potential VNW is controlled to be lower than that in the write operation.

Therefore, since the threshold voltage of each drive transistor 44, 45 made of the PMOS is lowered only during the read operation, the drive capability of each drive transistor 44, 45 is increased, so that the area of the memory cell 41 is increased. Moreover, the read operation can be performed at high speed without increasing the leak current during standby.

In the write operation, the first load transistor 46 and the second load transistor 47 are required to have a large driving capability in order to assist the write operation. Therefore, the second well of each load transistor 46, 47 is required. The potential VPW is controlled to be higher than that during the read operation.

Therefore, since the threshold voltage of each load transistor 46, 47 made of NMOS decreases only during the write operation, the drive capability of each load transistor 46, 47 increases, so that the area of the memory cell 41 should be increased. It is possible to speed up the writing operation without the need.

Since the respective well potentials VNW and VPW can be controlled independently, the respective effects can be obtained. Therefore, the first well potential VNW or the second well potential VP is controlled.
It may have a means for controlling only one of W.

When the precharge potential of the bit line is the high potential, the first load transistor 46 and the second load transistor 47 shown in FIG. 5 function as drive transistors, and the first drive transistor 4
The fourth drive transistor 45 and the second drive transistor 45 function as load transistors. Therefore, drive transistor 4
The second well potential VPW is boosted so that the driving capability of the transistors 6, 47 becomes large only during the read operation, and the PMO
The same effect can be obtained by lowering the first well potential VNW so that the drive capability of the load transistors 44 and 45 made of S increases only during the write operation.

The SRAM memory cell as the data holding circuit according to the first modification of the third embodiment of the present invention will be described below.

In this modification, the first well potential VNW or the second well potential VPW is controlled so as to increase the noise margin during the read operation.

Specifically, when the bit line BL is row precharged, the second well potential V, which is the well potential of the load transistors 46 and 47 made of NMOS.
Increase PW. As a result, the load transistor 46,
Since the threshold voltage of 47 is lowered, the load transistor of one of the inverters holding the row data is activated more. As a result, the drive transistor of the other inverter is activated more, so that the read current is increased and the noise margin is expanded.

If the bit line BL is high precharged, the load transistor 4 made of PMOS is used.
The first well potential VNW, which is the well potential of 4, 45, is lowered. As a result, the threshold voltages of the load transistors 44 and 45 are lowered, so that the load transistor of one of the inverters holding high data is more activated. As a result, the drive transistor of the other inverter is activated more, so that the read current is increased and the noise margin is expanded.

The SRAM memory cell as the data holding circuit according to the second modification of the third embodiment of the present invention will be described below.

In this modified example, P
The first well potential VNW, which is the well potential of the MOS transistor, is increased to increase the threshold voltage of the PMOS transistor. As a result, the driving capability of the PMOS transistor is lowered, and reverse writing is easily performed, so that high-speed writing can be performed.

The SRAM memory cell as the data holding circuit according to the third modification of the third embodiment of the present invention will be described below.

In this modification, N is set during the write operation.
The second well potential VPW, which is the well potential of the MOS transistor, is lowered to increase the threshold voltage of the NMOS transistor. As a result, the driving capability of the NMOS transistor is lowered, and reverse writing is easily performed, so that high-speed writing can be performed.

Needless to say, in the present embodiment, the same effect as that of the present invention can be obtained even if the data holding circuit is composed of transistors in which the polarities of the access transistors 18 and 19 are inverted.

[0108]

According to the data holding circuit of the first or second aspect of the present invention, the first and second inverters are CMOSF.
In the case of the ET, the gate-source voltage of the N-type drive transistor expands during the read period, and the read current increases, so that low voltage driving can be realized without increasing the area of the memory cell. At the same time, the reading speed can be increased. Further, if the read speed is set to an allowable level, the size of each transistor forming the memory cell can be reduced and the current consumption can be reduced.

Further, even in the standby state, if the power supply potential for driving the memory cell is set higher than the normal power supply potential, the gate-source potential of the transistor serving as the leak source is 0 V, so that the leak current Does not increase, and is less likely to be affected by noise such as soft error, so that the data retention characteristic is improved.

According to the data holding circuit of the third or fourth aspect of the present invention, the first and second inverters are CMOSFE.
In the case of being configured by T, the gate-source voltage of the P-type drive transistor increases during the read period, and the read current increases, so that low voltage driving can be realized without increasing the area of the memory cell. At the same time, the reading speed can be increased.

Furthermore, since the pre-charge potential applied to the data read line is applied to the low potential, the data read line serves as the source compared to the case where it is applied to the high potential, so that the read current further increases. As a result, the read speed can be further increased.

If the reading speed is set to an allowable level, the size of each transistor forming the memory cell can be reduced and the current consumption can be reduced.

According to the data holding circuit of the fifth or sixth aspect of the present invention, the first and second inverters are CMOSFE.
In the case of being configured by T, since the data latching ability of the drive transistor of the high-side data holding unit is reduced during the writing period, the reverse writing that requires the longest writing time can be easily performed, so that the writing operation is performed. Get faster.

According to the data holding circuit of the seventh or eighth aspect of the present invention, the first and second inverters are CMOSFE.
In the case of being composed of T, since the data latching ability of the drive transistor of the row side data holding unit becomes large during the writing period, the reverse writing which requires the longest writing time can be easily performed, so that the writing operation can be performed. Get faster.

According to the data holding circuit of the ninth aspect of the present invention, when the data read line for reading data from the data holding unit is high precharged, the threshold of the P-type load transistor during the read period is caused by the substrate bias effect. Since the value voltage becomes small, the driving ability of the load transistor becomes large. As a result, the driving capability of the N-type drive transistor during the read period is increased, so that high-speed read operation can be performed without increasing the leak current and the noise margin is expanded.

Even when the read line is row precharged, the threshold voltage of the P-type drive transistor decreases due to the substrate bias effect, and the drive capability of the drive transistor increases, so that high-speed read is possible. The operation can be performed and the noise margin is expanded.

According to the data holding circuit of the tenth aspect of the present invention, when the data read line for reading data from the data holding unit is pre-charged high, the threshold voltage of the N-type drive transistor is increased by the substrate bias effect. Since it becomes smaller, the drive capability of the drive transistor during the read period becomes larger, so that high-speed read operation can be performed.

Even when the read line is row precharged, the threshold voltage of the N-type load transistor is reduced due to the substrate bias effect, so that the data latching ability of the load transistor is increased. As a result, the driving capability of the P-type drive transistor during the read period increases, so that high-speed read operation can be performed without increasing the leak current, and the noise margin is expanded.

According to the data holding circuit of the eleventh aspect of the present invention, the threshold voltage of the P-type transistor in the writing period becomes small due to the substrate bias effect, so that the driving capability of the transistor becomes large.

According to the data holding circuit of the twelfth aspect of the invention, the threshold voltage of the P-type transistor during the writing period increases due to the substrate bias effect.
Since the driving capability of the type transistor is reduced, reverse writing is easily performed, and high-speed writing can be performed without increasing the size of the transistor.

According to the data holding circuit of the thirteenth aspect, the threshold voltage of the N-type transistor in the writing period increases due to the substrate bias effect.
Since the driving capability of the type transistor is reduced, reverse writing is easily performed, and high-speed writing can be performed without increasing the size of the transistor.

According to the data holding circuit of the fourteenth aspect of the present invention, the threshold voltage of the N-type transistor in the writing period becomes small due to the substrate bias effect, so that the driving capability of the transistor becomes large.

As described above, according to the data holding circuit of the present invention, the driving ability of each transistor during the read operation and the write operation can be optimized independently, so that the read speed is prioritized too much and the high data It is possible to avoid the phenomenon that the row data cannot be exchanged with the row data.

Furthermore, if the read speed and the write speed are set to an allowable level, the size of each transistor forming the memory cell can be reduced, and thus higher integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a data holding circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell of the data holding circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram comparing operating speeds related to a precharge potential of a bit line in the SRAM memory cell according to the first embodiment of the present invention, and FIG. 3A is a memory cell equivalent when the bit line is in high precharge. It is a circuit diagram,
(B) is a graph showing a simulation result of each voltage and time of the word line, the bit line, and the first storage node in the high precharge, and (c) is a memory cell equivalent circuit when the bit line is in the low precharge. Is a figure,
(D) is a graph showing a simulation result of each voltage and time of the word line, the bit line, and the first storage node in the row precharge.

FIG. 4 is a control sequence diagram in the data holding circuit according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a memory cell of a data holding circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional low voltage drive type SRAM memory cell.

[Explanation of symbols]

 11 Memory Cell 12 First Inverter 13 Second Inverter 14 First Drive Transistor 15 Second Drive Transistor 16 First Load Transistor 17 Second Load Transistor 18 First Access Transistor 19 Second Access Transistor 20 Switch transistor 21 Switch transistor 24 Drive transistor 26 Drive transistor 28 Access transistor 41 Memory cell 42 First inverter 43 Second inverter 44 First drive transistor 45 Second drive transistor 46 First load transistor 47 Second load Transistor N1 First storage node N2 Second storage node ICM Read current VCM Power supply potential of memory cell VSM Ground potential of memory cell VCMH Lee potential VCC power supply potential VSS ground potential PRE supply potential WL the word line BL bit line / BL complementary bit line tMA reading time VNW first well potential VPW second well potential

Claims (14)

[Claims] 1. A data holding unit comprising a first inverter and a second inverter in which one output node and the other input node are connected to each other, and the data holding unit is applied to the data holding unit during a data reading period. The data holding circuit is characterized in that the power supply potential is set to be higher than the power supply potential applied to the peripheral circuit of the data holding unit. 2. A data holding unit comprising a first inverter and a second inverter having one output node and the other input node connected to each other, the data holding unit being applied to the data holding unit during a data reading period. The data holding circuit is characterized in that the power supply potential is set to be higher than the power supply potential applied to the data holding unit during the data writing period. 3. A data holding section comprising a first inverter and a second inverter whose one output node and the other input node are connected to each other, and a data read line for reading data from the data holding section. The data read line is row-precharged so that a ground potential applied to the data holding unit during a data read period is lower than a ground potential applied to a peripheral circuit of the data holding unit. A data holding circuit characterized by being set. 4. A data holding unit comprising a first inverter and a second inverter, one output node and the other input node of which are connected to each other, and a data read line for reading data from the data holding unit. The data read line is row-precharged, and a ground potential applied to the data holding unit during a data reading period is lower than a ground potential applied to the data holding unit during a data writing period. A data holding circuit characterized by being set as follows. 5. A data holding unit comprising a first inverter and a second inverter in which one output node and the other input node are connected to each other, and is applied to the data holding unit during a data writing period. The data holding circuit is characterized in that the power supply potential is set to be lower than the power supply potential applied to the peripheral circuit of the data holding unit. 6. A data holding unit comprising a first inverter and a second inverter, one output node and the other input node of which are connected to each other, and which is applied to the data holding unit during a data writing period. The data holding circuit is characterized in that the power supply potential is set to be lower than the power supply potential applied to the data holding section during the data reading period. 7. A data holding unit comprising a first inverter and a second inverter in which one output node and the other input node are connected to each other, and is applied to the data holding unit during a data writing period. The data holding circuit is set such that the ground potential is higher than the ground potential applied to the peripheral circuit of the data holding unit. 8. A data holding unit comprising a first inverter and a second inverter, one output node and the other input node of which are connected to each other, and which is applied to the data holding unit during a data writing period. The data holding circuit is set such that the ground potential is higher than the ground potential applied to the data holding unit during the data reading period. 9. An output node on one side and an input node on the other side are connected to each other, and are provided with a first inverter and a second inverter, each of which is composed of a P-type transistor and an N-type transistor, respectively. A data holding circuit, wherein the well potential of the type transistor is set to be lower than the well potential of the P-type transistor in a data writing period. 10. An output node on one side and an input node on the other side are connected to each other, and are respectively a P-type transistor and an N-type transistor.
A first inverter and a second inverter each of which is composed of a transistor, and is set such that a well potential of the N-type transistor during a data read period is higher than a well potential of the N-type transistor during a data write period. A data holding circuit characterized by being provided. 11. An output node on one side and an input node on the other side are connected to each other, and are respectively a P-type transistor and an N-type transistor.
A first inverter and a second inverter each of which is composed of a P-type transistor, and is set such that a well potential of the P-type transistor during a data writing period is lower than a well potential of the P-type transistor during a data reading period. A data holding circuit characterized by being provided. 12. One output node and the other input node are connected to each other, and a P-type transistor and an N-type transistor are provided, respectively.
A first inverter and a second inverter each of which is composed of a P-type transistor, and is set such that a well potential of the P-type transistor in a data writing period is higher than a well potential of the P-type transistor in a data reading period. A data holding circuit characterized by being provided. 13. An output node on one side and an input node on the other side are connected to each other, and are respectively a P-type transistor and an N-type transistor.
A first inverter and a second inverter each of which is composed of a transistor, and is set so that a well potential of the N-type transistor during a data writing period is lower than a well potential of the N-type transistor during a data reading period. A data holding circuit characterized by being provided. 14. One output node and the other input node are connected to each other, and are a P-type transistor and an N-type, respectively.
A first inverter and a second inverter, each of which is formed of a transistor, and is set such that the well potential of the N-type transistor during the data writing period is higher than the well potential of the N-type transistor during the data reading period. A data holding circuit characterized by being provided.