JPH0918788A - Signal processing device, solid-state imaging device, and imaging method of this device - Google Patents

Abstract

An object of the present invention is to reduce carrier transfer time in a solid-state imaging device. SOLUTION: The signal output line 5, which converts light into an electric signal,
In the photoelectric conversion device including the photoelectric conversion pixel 1 for outputting to 9, the input portion of the amplifier is capacitively coupled to the signal output line 5 of the photoelectric conversion pixel 1, and the amplifier output portion is connected to the signal output line through a switch. It is characterized by doing. Further, the amplifier is characterized by being an emitter follower, a source follower or an operational amplifier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having a solid-state image pickup device, and more particularly to a solid-state image pickup device provided with a signal processing device for effectively processing an optical signal from the solid-state image pickup device.

[0002]

2. Description of the Related Art In recent years, with the remarkable development of semiconductor technology, the performance of solid-state image pickup devices typified by CCD and MOS type has been greatly improved and has been used in various products such as facsimiles and scanners. . With it,
In addition to the demand for improved characteristics such as higher sensitivity and higher resolution required for solid-state imaging devices, the demand for low-voltage driving is also gradually increasing.
Products that can be driven by a power supply have also appeared, and development for driving at a lower voltage is being actively done.

14 and 15 show an example of a bipolar type solid-state image pickup device which is one of the conventionally used XY address type amplification type photoelectric conversion elements. FIG. 14 is an equivalent circuit diagram of a unit pixel of the solid-state image sensor. In the figure, the NPN transistor 3, the PMOS transistor 1, and the capacitor 2 constitute a unit pixel which is also a photoelectric conversion element. Therefore, the base of the NPN transistor 3 receives photons, accumulates photoelectric carriers, and transfers the carriers to the emitter of the NPN transistor 3 in a floating state to provide a carrier output signal. Here, 101 is a reset pulse supply terminal for driving the base of the NPN transistor 3 at three levels, and 102 is a pulse supply terminal for turning on / off the PMOS transistor 1 to accumulate and discharge the base carrier.

In FIG. 15, each photoelectric conversion element has NPN transistors 3-1 to 3-4 and PMOS transistors 1-1 to 1.
It is composed of 1-4 and capacity 2-1 to 2-4,
This is a solid-state imaging device in which four bipolar photoelectric conversion elements are arranged one-dimensionally. Each pixel performs operations such as resetting and reading with a pulse given to the terminal 101, and those signals are output to the emitters of the NPN transistors 3-1 to 3-4 and the PMOS transistors 11-1 to 1-1.
After being read out once and stored in the storage capacitors 12-1 to 12-4 via 1-4, the scanning circuit SR30 sequentially turns on the PMOS transistors 13-1 to 13-4 of the switch means to generate a serial signal. Each storage capacity 12-1 to 1
The optical carrier signals 2-4 are transferred to the output terminal 111.

By the way, in this case, the time required for one cycle mainly includes pixel resetting, signal reading time and serial transfer time, but most of them are often used for the serial transfer time. Further, this time is longer as the number of pixels is larger, and most of the cycle time is transfer time in the case of an area sensor having a plurality of rows and columns for the line sensor. Therefore, when considering the application as a detector such as detecting the presence or absence of an image at high speed, how to shorten this time becomes a problem.

The present inventor has shown in Japanese Patent Laid-Open No. 6-268920 that this time can be shortened by outputting an averaged signal of a plurality of pixels. However, in the above-mentioned invention, although it is easy to average the signals in the horizontal direction of the area sensor, the average of the signals in the vertical direction is usually about 2 to 4 pixels, and if it is more than that, the chip size increases. It was difficult to do so. Therefore,
It was extremely difficult to use a high-speed, low-cost detector that uses an area sensor.

[0007]

The present invention has been made to solve the above-mentioned difficulties, and in the solid-state image pickup device of the present invention, a signal output obtained by pre-processing the signal of each pixel and an output for each pixel. In the solid-state imaging device having a function of outputting both of the above, the preprocessed signal output is output through an output unit that outputs a signal for each pixel.

The operation and action will be conceptually described below with reference to FIG. In FIG. 16, 51-1 to 51-8 are unit pixels, and 50-1 to 50-8 are unit pixels 51-1 to 5-5.
Transferring means 52-1 to 52-8 for holding the pixel signals 1-8 in the storage capacitor and then serially outputting them to the output line 55.
Are pre-processing means connected to the unit pixels 51-1 to 51-8 to perform pre-processing, 53-1 to 53-8 are buffer means for buffering signals of the pre-processing means, and 54-1 to 54-54.
-8 is transfer means 50-1 to 50-8 and buffer means 53
It is a switching means for connecting -1 to 53-8.
The buffer means 53-1 to 53-8 are not necessarily provided.

According to the present invention, the unit pixels 51-1 to 51-
The -8 signal is a transfer unit 50 that holds the signal for each pixel.
After being read by −1 to 50-8, it is output to the terminal 57 through the output circuit 56 via the output line 55. on the other hand,
After appropriate preprocessing is performed by the preprocessing means 52-1 to 52-8, the data is transferred to the transfer means 50-1 to 50-8 through the buffer means 53-1 to 53-8 and output to the terminal 57. . Here, as a matter of course, the output of the signal not subjected to the pre-processing and the output of the signal after the pre-processing must be output in different periods without overlapping. Further, it is also possible to perform a serial transfer after outputting after blocking and mixing in the transfer means 50-1 to 50-8 for holding the signal not pre-processed and the signal after pre-processing.

Here, for example, the holding and transferring means 50-1 to 50-1
50-8 is the storage capacitors 12-1 to 12- shown in FIG.
4 and the switch means 13-1 to 13-4 and the scanning circuit 30, and the preprocessing circuit is an FPN (Fixed Pattern) by a clamp circuit as described later.
Noise) removal circuit or the like can be applied.

In FIG. 17, the same parts as those in FIG. 16 are designated by the same reference numerals, but the preprocessing means 52-1 to 52-2 are provided.
-8 buffer signals 53-1 to 53-
After buffering in 8, block multiple columns, hold,
It is read out to the transfer means. With this configuration, the signal amount of the pixel can be reduced, the cycle time can be significantly reduced, and the holding, transfer circuit and output circuit can be shared with the signal without preprocessing. , Without a large increase in chip size. Therefore, normally, the output of this block is read out, the detection operation is performed based on this signal, and as a result, the signal of each pixel is read out one pixel at a time, thereby achieving high speed, low power consumption, and low power consumption. A low-cost solid-state imaging device can be provided. This is explained in more detail in the examples below.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings together with the operation and action thereof.

(Embodiment 1) FIG. 1 shows a first embodiment according to the present invention. In this embodiment, the bipolar type photoelectric conversion element shown in FIG. 14 is used as the photoelectric conversion element, and four photoelectric conversion elements are arranged one-dimensionally. In the figure, the same symbols as those in FIG. 15 have the same functions. In addition, the coupling capacitors 5-1 to 5-4 and the NMOS as the preprocessing means shown in FIG.
Transistors 6-1 to 6-4, buffer capacitors 7-1 to 7-4 as buffer means, and NMOS transistor 9
-1 to 9-4 and NMOS transistors 16-1 to 16-4 as switching means are provided.

The operation of this embodiment will be described below with reference to the timing chart of FIG. First, terminals 105 and 1
Input a high level pulse to 04 and 107, and
The OS transistors 9-1 to 9-4, 6-1 to 6-4 and 11-1 to 11-4 are turned on.

At time T0, when a low level pulse is applied to the terminal 101, the PMOS transistor 1-
1 to 1-4 become conductive, and the base region of each photoelectric conversion element is reset to the voltage applied to the terminal 102 (first reset). After that, the pulse of the terminal 101 is Middle
It becomes the level, and each PMOS transistor 1-1 to 1-4
When the gate-source voltage VGS of the transistor becomes equal to or lower than the threshold value Vth of the PMOS transistor, the PMOS transistor 1
-1 to 1-4 are turned off, and the first reset ends.

Further, at time T1, a high level pulse is applied to the terminal 106, the NMOS transistors 10-1 to 10-4 become conductive, and the emitter potential of the NPN transistor of each pixel is reset to the reset potential (GN in the figure).
D) is reset.

After that, at time T2, when a high level pulse is applied to the terminal 101, the PMOS transistors 1-1 to 1-4 remain in the non-conducting state and the capacitance 2-
The base potential of the NPN transistor rises due to capacitive coupling through 1 to 2-4, the base-emitter voltage is forward biased, and the NPN transistors 3-1 to 3-4 perform an emitter follower operation and are in a floating state. The holes on the base region are optically recombined, so that the base voltage is reset (second reset).

When this reset is completed, at time T3, the pulse of the terminal 101 falls to the Middle level, and the base potential of each pixel is shifted to the negative side this time.
The base-emitter voltage is in a reverse bias state, and the storage operation is started at this point (first storage operation).

Next, after a lapse of a predetermined accumulation time, at time T4, when the pulse of the terminal 106 falls to the Low level, the NMOS transistors 11-1 to 11-.
4 becomes non-conductive, and each pixel transistor 3-1 to 3-3
-4 emitter and capacitors 12-1 to 12-4 are in a floating state.

Then, at time T5, when a high-level pulse is applied to the terminal 101, the base potential of each pixel is shifted to the positive side via the capacitors 2-1 to 2-4, and the NPN transistor 3 of each pixel is applied. The base-emitter voltages of −1 to 3-4 are in a forward bias state, and therefore the signals photoelectrically converted in each pixel and stored in the base region are respectively storage capacitors 12-1 to 12-4 and a coupling capacitor 5-. 1
˜5-4.

After that, at time T6 immediately before the end of the read operation, the pulse at the terminal 105 falls, and N
MOS transistors 9-1 to 9-4 are turned off.

Then, at time T7, the terminal 101
Pulse of N falls through the capacitors 2-1 to 2-4
The PN transistors 3-1 to 3-4 are turned off, and the reading operation is completed.

After that, at time T8, a high level pulse is applied to the terminal 106 again, and each pixel NPN
When the emitters of the transistors 3-1 to 3-4 are reset to the reset voltage (GND in the figure), the buffer capacitance 7
The voltages of -1 to 7-4 are applied to the negative side due to capacitive coupling by the coupling capacitors 5-1 to 5-4. Here, the coupling capacitance 5-1
Let V _R be the signal read to 5-4 and V _R 'be the signal after being touched: V _R ' = -C _C × V _R / (C _C + C _T + C _S ) ... (1) C _C : Coupling capacitance 5-1 to 5-4 capacitance value C _T : Buffer capacitance 7-1 to 7-4 capacitance value C _S : Parasitic capacitance including gate capacitance of NMOS transistors 8-1 to 8-4 expressed. In addition, NMOS transistors 10-1 to 10
Since -4 is on, the signals read to the storage capacitors 12-1 to 12-4 are also reset.

Next, from time T9 to T14, there is a difference that the NMOS transistors 9-1 to 9-4 are off.
The same operation as T0 to T4 is performed, the photoelectric conversion element is reset again, and the photocarrier is accumulated (second accumulation), and then the read operation is performed at time T14. At that time (1)
Since the signal voltage is read out on top of the voltage of the formula, as a result, the difference signal between the signals photoelectrically converted in the first accumulation period and the second accumulation period is held in the buffer capacitors 7-1 to 7-4. It

Thereafter, at time T16, the terminal 106
High level pulse is applied to the storage capacitor 12-1 to
After resetting 12-4 again, at time T17,
High-level pulse is input to the terminal 113 and NMOS
When the transistors 16-1 to 16-4 are turned on, the signals of the buffer capacitors 7-1 to 7-4 are stored in the storage capacitors 12-1 to 12-12.
-4.

Thereafter, at time T18, the terminal 10
4, 107 becomes LOW level, the NMOS transistors 6-1 to 6-4 and 11-1 to 11-4 are turned off,
Then, the NMOS transistors 16-1 to 16-4 are turned off.

Then, after the time T19, the scanning circuit 30 is operated while the output line 40 is reset, and the storage capacitor 12
The signals from -1 to 12-4 are output serially in sequence.
To end the series of operations. If the first accumulation time is set to be very short here, in the first read operation,
Since the signal corresponding to the dark time is obtained, the FPN can be removed by performing the difference calculation with the signal obtained by the subsequent second accumulation and reading.

When the first accumulation time and the second accumulation time are set to be the same and the subject is illuminated with a light source such as an LED during the second accumulation period, the outside light component can be obtained even in an environment with outside light such as outdoors. Can be removed, and accurate object detection can be performed.

The above operation is an example of signal output when pre-processing is performed, but when the signal of each pixel is output as it is, the drive shown in the timing chart of FIG. 5 may be performed. FIG. 5 is a modification of FIG. 4 in that the accumulation is performed twice, the terminal 113 remains low even at T17, and the signal finally read is the signal in the second accumulation operation. There is no problem even if the period from T0 to time T9 is omitted.

In FIG. 5, since the terminal 113 is always at the Low level and the NMOS transistors 15-1 to 15-5 are always in the non-conducting state, the calculation performed in the clamp circuit section is the storage capacitors 12-1 to 12-. 4 is not affected at all and the signal of each pixel is stored in the storage capacitor 12-1 at the time of reading as usual.
12-4 are directly read out, are not reset, and are thereafter serially output by the scanning circuit 30. When the clamp process is performed, as shown in the equation (1), it is more effective to directly read the sensor signal in order to improve the detection sensitivity, for example, in the case of detecting a relatively low-luminance subject such as in a room because the output is reduced. .

Here, FIG. 1 shows an example in which the preprocessing circuit is a differential operation circuit using a clamp circuit.
As shown in FIG. 2, each vertical output line has a switch means 17-
1 to 17-4, two holding capacitors 18-1 to 18-8 are provided, and a switch means for electrically connecting the holding capacitors between adjacent pixels is provided, and the output thereof is transferred to the transfer switch 9-1.
9 to 4 through NPN transistors 3-1 to 3-4
The pre-processing can also be performed by averaging signals between adjacent pixels by connecting to the emitter terminal of.

In addition, as shown in FIG.
5-4 is eliminated, and the capacities 35-1 to 35-4 are replaced by the capacities 12
By holding the photoelectric conversion signals at different time points from the signals read by -1 to 12-4, signals with different storage times can be serially read out, and when the pixels are arranged two-dimensionally with this configuration, It is also possible to hold the maximum signals of the pixel columns in each vertical direction in the capacitors 35-1 to 35-4 and output these at timings different from the signals of the pixels.

An arithmetic circuit using an operational amplifier may be used as the preprocessing circuit.

(Embodiment 2) FIG. 6 shows a second embodiment according to the present invention. 6, those having the same reference numerals as those in FIG. 1 or FIG. 15 have the same functions, and detailed description thereof will be omitted. The photoelectric conversion element used in this embodiment is an NPN transistor 33 having two emitter terminals, as shown in FIG.
It is composed of a PMOS transistor 1 and a capacitance means 2, and one of the two emitter terminals is commonly connected between the other pixels forming the pixel block, and the maximum voltage of the pixels forming the block is the buffer capacitance 7-1, 7 -2 is stored in the storage capacitors 12-1, 12-3 and is transferred to the storage capacitors 12-1, 12-3, and the storage capacitors 12-1, 12-3 are scanned by the scanning circuit SR30.
The accumulated amount of is output from the terminal 111.

The driving method of the present embodiment is generally based on FIG. 4 or FIG. 5 of the first embodiment, and the terminal 103 is driven at the same timing as the terminal 106 to perform reset and accumulation. Therefore, normally, the output of this block is read and the accumulated carrier of the pixel having the highest sensitivity in the block is output, so that the detect operation is performed based on this signal.
As a result of this circuit operation, it is possible to read out the signal of each pixel one pixel at a time as required, and it is possible to obtain the output of the pixel having the highest sensitivity of a plurality of pixels as a block. The signal amount can be significantly compressed, which has a great effect on shortening the cycle time and reducing power consumption.

(Embodiment 3) FIG. 8 shows a third embodiment of the present invention. In FIG. 8, those having the same reference numerals as those in FIG. 1, FIG. 6 or FIG. This embodiment is a modification of the second embodiment, in which the capacitances 7-1 and 7-2 on the output side of the clamp circuit are N.
The PN transistors 8-1 and 8-2 are provided, their emitter terminals are commonly connected, and then the constant current source 15 is provided, and the terminal 112 is used as an output.

According to this embodiment, after the clamping operation, the signals output to the buffer capacitors 7-1 and 7-2 are the scanning circuit 3
Without operating 0, its maximum value is immediately terminal 1
Since it is output to 12, the cycle time is shorter than that in the second embodiment, and power consumption can be saved. Although the NPN transistor is used in this embodiment, the minimum value of the block signal can be obtained at the output terminal 112 by using the emitter follower circuit using the PNP transistor. Therefore, in this embodiment, it is possible to detect whether the signal amount is equal to or more than (or less than) a predetermined value, and as a result, drive such that the signal of each block or each pixel is read out only when necessary. Therefore, it is effective that the photoelectric conversion output can be obtained.

Further, in FIG. 8, the buffer capacity 7-
1, 7-2 are illustrated as being reset to the GND potential by the NMOS transistors 9-1 and 9-2, the reset power supply terminal 131 is provided and the NPN transistor 8-1 is provided as shown in FIG. , 8-2 is set to a voltage such that the base-emitter bias is sufficiently quasi-biased, the minute signal output can be sufficiently read.

Further, in FIG. 8, the buffer capacity 7-
Since the signals 1 and 7-2 are read using the emitter follower circuit using the constant current source 15, the current amplification factor of the NPN transistors 8-1 and 8-2 is β, and the current value of the constant current source 15 is If I0 and the capacity value of the buffer capacity are CB,
During the read time TR, the signal voltage of the buffer capacity is reduced by {(I0 / β) × TR} / CB (2). Therefore, if the emitter follower circuit is a Darlington connection emitter follower shown in FIG. 10, the signal voltage drop can be reduced to {(I0 / β ² ) × TR} / CB (3). For example, the current amplification factor β is 10
If I0 is several .mu.A and CB is several pF, the drop of the signal voltage can be virtually eliminated.

(Fourth Embodiment) FIG. 11 shows a fourth embodiment according to the present invention. In FIG. 11, the same reference numerals as those in FIGS. 1 and 15 have the same functions, and detailed description thereof will be omitted. In Examples 1 to 3, buffer capacities 7-1 to 7-
4 (7-1 to 7-2) and the storage capacitors 12-1 to 12-4 are connected via the switches 16-1 to 16-4 (16-1 to 16-2), the transfer gain is C _T / (C _T + C _T2 + C _S2 ) (4) C _T : capacity value of buffer capacity 7-1 to 7-4 C _T2 : capacity value of storage capacity 12-1 to 12-4 C _S2 : NMOS 16-1 to A buffer capacity including a gate capacity of 16-4 and 7-1 to 7-4 and a storage capacity 12-1 to
It becomes a parasitic capacitance between 12 and 4, and this value is usually about 0.3 to 0.4. In this embodiment, an emitter follower circuit including NPN transistors 8-1 and 8-2 is provided in the buffer capacitors 7-1 and 7-2, and the output of the emitter follower circuit is stored in the storage capacitors 12- through the switches 16-1 and 16-2. It was made to connect to 1 and 12-3.
Therefore, the capacitance value of the parasitic capacitance C _S2 is minimized, and the capacitance can be transferred to the storage capacitors 12-1 to 12-4 with almost no loss, which is effective when the signal amount from the sensor is small.

(Embodiment 5) FIG. 12 shows a fifth embodiment of the present invention. In FIG. 12, the same reference numerals as those in FIG. 1 and FIG. 15 have the same functions, and detailed description thereof will be omitted. This embodiment is a combination of the third and fourth embodiments. In the fourth embodiment, the NPN transistor 8-1,
The emitter of 8-2 is connected by the NMOS transistor 17, and the maximum value of the block output can be taken out from the terminal 112. As described in the third embodiment, the maximum output of the block can be immediately obtained for the light quantity carrier of the buffer capacity 7-1, and if a high voltage pulse is applied to the terminal 114 thereafter, the light quantity carrier of the buffer capacity 7-1 can be obtained. Can also be output, and the output of each block can be read without loss.

(Embodiment 6) FIG. 13 shows a sixth embodiment of the present invention. In FIG. 13, those having the same reference numerals as those in FIGS. 1 and 15 have the same functions, and detailed description thereof will be omitted. In this embodiment, photoelectric conversion elements are arranged two-dimensionally in comparison with the fifth embodiment, and a block is composed of two pixels in the vertical direction and two pixels in the horizontal direction, and two matrix blocks are shown as a 4 × 4 area sensor. The output is read to the capacitors 7-1 to 7-4 through the clamp circuit, while the signal of each pixel is read to the storage capacitors 12-1 to 12-4 driven by the vertical shift register 31. A three-level pulse is applied in time series from the terminal 1 to instruct the timing of resetting and accumulating each pixel described above, and the terminals 115 and 116
The pulse signal is sequentially output from the vertical shift register 31 to which the clock and the timing signal are input, and each switch is turned on / off to scan each pixel. According to the scanning signal and the pulse signal applied from each terminal, NPN transistors 3-1 to 3-3 each having two emitter terminals to be pixels
The optical carrier output signal stored in the base of the buffer 16 is stored in the storage capacitors 12-1 to 12-4 on the one hand, and the buffer capacity 7-through the coupling capacitors 5-1 to 5-4 by the block operation on the other hand. 1 to 7-4 are transferred and accumulated.

Then, the storage capacitors 12-1 to 12-4 are reset by the high pulse of the terminal 106, and the buffer capacitors 7-1 to 1-7, which are the maximum charges of the block, are switched via the switch means 16-116-4. Transfer the 7-4 capacity charge,
The signals are sequentially output from the terminal 111. Further, by the applied pulse from the terminal 114, the photoelectric conversion output corresponding to the maximum accumulated carriers of all 16 pixels can be obtained from the terminal 112.

According to this embodiment, a photoelectric conversion pixel and a vertical scanning circuit are added to obtain an image pickup area wider than that of the fifth embodiment as an area sensor. Therefore, a detection operation with higher accuracy and higher sensitivity can be obtained. Can be realized. Further, if the vertical column according to this embodiment is divided into blocks and the average value of each pixel is stored in the buffer capacity, the average value of the vertical pixels can be obtained in a short time without requiring any cycle time.

In the above embodiment, the signal of each block is NP.
Although the detection operation is performed by the peak signal using the N transistors 8-1 and 8-2, there is no problem even if the bottom signal is also detected by using the PNP transistor, and both are used according to the purpose of the photoelectric conversion device. With this, it becomes possible to perform more detailed detection.

Although all the above embodiments have been described using the bipolar type photoelectric conversion element, CMD, AMI, FG.
The same effect can be obtained by using a photoelectric conversion element such as A.

[0047]

As described above, according to the present invention,
Since it has a function of outputting both the signal output of pre-processing the signal of each pixel and the output of each pixel, it is of course possible to obtain photoelectric conversion output by conventional scanning, and of course serial transfer by the pre-processing signal output. You can save time. Further, even when the number of pixels is large, even in the case of an area sensor having a plurality of lines, the transfer time is not added, the cycle time is not extended, and the presence or absence of an image can be detected at high speed.

Further, FPN (Fixed Pattern Noise) can be effectively removed by the clamp circuit by the preprocessing circuit.

By dividing a plurality of columns into blocks, the signal amount of pixels can be reduced, the cycle time can be greatly reduced, and the holding, transfer circuit and output circuit can store signals for which no preprocessing is performed. It is possible to provide a solid-state imaging device that can be shared with other devices and that has high speed, low power consumption, and low cost without a large increase in chip size.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment according to the present invention.

FIG. 2 is a circuit diagram of an embodiment according to the present invention.

FIG. 3 is a circuit diagram of an embodiment according to the present invention.

FIG. 4 is a timing chart illustrating the operation of FIGS. 1 to 3 according to the present invention.

FIG. 5 is a timing chart explaining another operation of FIGS. 1 to 3 according to the present invention.

FIG. 6 is a circuit diagram of a block-type embodiment according to the present invention.

7 is a circuit diagram showing an example of a pixel of the photoelectric conversion element used in FIG. 6 according to the present invention.

FIG. 8 is a circuit diagram of another block-embodied embodiment according to the present invention.

FIG. 9 is a circuit diagram of another block-embodied embodiment according to the present invention.

FIG. 10 is a circuit diagram of another block-embodied embodiment according to the present invention.

FIG. 11 is a circuit diagram of another block-embodied embodiment according to the present invention.

FIG. 12 is a circuit diagram of another embodiment in which a block is formed according to the present invention.

FIG. 13 is a circuit diagram of another embodiment in which a block is formed according to the present invention.

FIG. 14 is a circuit diagram showing an example of a pixel of a conventional photoelectric conversion element.

FIG. 15 is a circuit diagram showing an example of a conventional line sensor.

FIG. 16 is a block diagram illustrating an operation principle according to the present invention.

FIG. 17 is a block diagram illustrating another operation principle according to the present invention.

[Explanation of symbols]

 1 PMOS Transistor 2 Capacitance 3 NPN Transistor 4 NMOS Transistor 5 Coupling Capacitance 6 NMOS Transistor 7 Buffer Capacitance 8 NPN Transistor 9 NMOS Transistor 10 NMOS Transistor 11 NMOS Transistor 12 Storage Capacitance 13 NMOS Transistor 14 NMOS Transistor for Output Line 15 Constant Current Source 16 Switching means NMOS transistor 17 NMOS transistor 30 Horizontal scanning circuit 31 Vertical scanning circuit 50 Holding / transfer means 51 Unit pixel 52 Pre-processing circuit 53 Buffer circuit 54 Switching means

Claims (12)

[Claims] 1. A solid-state imaging device comprising: a plurality of photoelectric conversion pixels for converting an optical signal into an electric signal; and a transfer unit for outputting an electric signal from the photoelectric conversion pixel, wherein the electric signal of the photoelectric conversion pixel is A solid-state imaging device comprising: preprocessing means for preprocessing; buffer means for transferring the output of the preprocessing means to the next stage; and switch means for transferring the output of the buffer means to the transfer means. apparatus. 2. The solid-state imaging device according to claim 1, wherein the pre-processing means is a clamp circuit. 3. The solid-state imaging device according to claim 1, wherein the buffer means has a buffer capacity. 4. The solid-state image pickup device according to claim 1, wherein the switch means turns on after discharging the electric signal accumulated in the transfer means. 5. The solid-state imaging device according to claim 1, wherein the switch means switches on a plurality of the buffer means as a block. 6. A photoelectric conversion means including a photoelectric conversion element for converting an optical signal into an electric signal, a transfer means having a storage capacitor for transferring the electric signal, and a scan for outputting electric charge of the storage capacitor to an output line. In the solid-state imaging device including a means, a pre-processing means having a coupling capacitance for temporarily storing the electric signal, a buffer means having a buffer capacitance for transferring a charge of the coupling capacitance, and a charge of the buffer capacitance A solid-state imaging device, comprising: a switch unit that transfers to a storage capacitor. 7. The solid-state imaging device according to claim 6, wherein the photoelectric conversion element has two emitter terminals.
A solid-state imaging device comprising a PN transistor, wherein one of the emitter terminals is connected to one end of the switch means and the transfer means, and the other one is connected to the preprocessing means. 8. The solid-state imaging device according to claim 6, further comprising buffer output means for outputting the buffer capacity. 9. The solid-state image pickup device according to claim 8, wherein the buffer output means outputs the electric charge of the buffer capacitance obtained by dividing a plurality of photoelectric conversion pixels into blocks by superimposing the plurality of blocks. A characteristic solid-state imaging device. 10. A signal processing device having a built-in processing circuit for processing a plurality of types of signals output from one signal source in parallel, wherein at least one of the outputs of the processing circuits is output from a common output circuit. A signal processing device characterized in that the signals are output in series. 11. The solid-state imaging device according to claim 10, wherein the signal source is a solid-state imaging device. 12. A photoelectric conversion unit including a photoelectric conversion element for converting an optical signal into an electric signal, a transfer unit including a storage capacitor for transferring the electric signal, and a scan for outputting electric charge of the storage capacitor to an output line. An image pickup method for a solid-state image pickup device, comprising: storing a charge of the electric signal in a temporary coupling capacitance, transferring a charge of the coupling capacitance to a buffer capacitance, discharging a charge of the storage capacitance, An image pickup method for a solid-state image pickup device, comprising: transferring charges in a buffer capacitance to the storage capacitance.