JPH09204412A - Microcomputer - Google Patents

Abstract

(57) [PROBLEMS] To enable mode setting by a plurality of bits from the outside of a microcomputer with a relatively simple circuit by using fewer input terminals and output terminals. SOLUTION: In order to perform the first mode setting at the timing when the reset is released and (RST bar) rises,
The first mode input from MOD is the D-type latch L
It is held at 1 and output as the output Q1. Then, the mode setting contents for the second mode setting are input from the MOD at the timing of the fall of the memory read signal (RD bar) that is also output to the outside of the microcomputer, and this is held by the D-type latch L2. And output as output Q2. Using the control signals ((RD bar) and (RST bar)) that the microcomputer originally has, one M
Multiple modes can be set from the OD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer adapted to process a program based on a plurality of instruction codes while sequentially fetching instruction codes from an external memory and inputting / outputting data to / from the outside as needed. In particular, a desired mode setting inside the microcomputer according to a plurality of bits from the outside of the microcomputer can be performed with a relatively simple circuit by using fewer input terminals and output terminals of the microcomputer. The present invention also relates to a microcomputer capable of easily maintaining compatibility with a microcomputer of the past that does not have such a function of setting a mode of a plurality of bits.

[0002]

2. Description of the Related Art A microcomputer widely used today fetches instruction codes sequentially from an external memory,
It has a function of processing a program based on the plurality of instruction codes while outputting data to the outside as needed. Such a microcomputer is
CPU (central processing unit) or MPU
(Micro processor unit) is also called, hereinafter, referred to as the microcomputer. Such a microcomputer is also used, for example, in an electronic device which is conventionally configured by hardware, and is also used for realizing a function by software. Also, A
SIC (application specific integrated circuit)
Conventionally, there is also one that provides an integrated circuit pattern of Z80 (MPU) manufactured by Zilog Corporation in the United States as a macro library.

Some of such microcomputers have a plurality of modes, for example, a plurality of operation modes. For example, as in the first and second embodiments described later, different types of memory access and I / O
(Input / output) Three operation modes that determine access,
That is, there are those having a mode A, a mode B1 and a mode B2. Further, some microcomputers having a self-diagnosis function have a normal operation mode and a test mode for performing self-diagnosis.

In such a microcomputer having a plurality of modes, it is necessary to select and specify one of the modes from the outside. The simplest mode selection input is to provide a microcomputer package with a sufficient number of mode selection signal input terminals for setting the required mode.

However, in the microcomputer, the total number of input terminals, output terminals, and input / output terminals is determined according to the type of package. Therefore, it is necessary to effectively use such a limited number of terminals, and it is desirable that the number of terminals for selectively inputting a mode such as an operation mode is as small as possible.

Therefore, in Japanese Patent Laid-Open No. 3-257685,
While the microcomputer is reset by delaying the external reset signal, the mode selection signal is sampled several times at the rising edge of the external reset signal while the microcomputer is in the reset state to set a plurality of mode settings to one. The mode selection signal input terminal can be used.

Here, the external reset signal is a signal input from the external reset signal input terminal, and is a signal for initializing the processing inside the microcomputer.
The mode selection signal is a signal input from the mode selection signal input terminal and is a signal for setting a mode such as an operation mode of the microcomputer.

Further, in Japanese Patent Laid-Open No. 3-191433, in order to sequentially set a plurality of modes, the contents of these mode settings are sequentially input from a single mode selection signal input terminal. In this Japanese Patent Laid-Open No. 3-191433, unlike the above-mentioned Japanese Patent Laid-Open No. 3-257685 in which a plurality of mode setting contents are sequentially input at each rising edge of an external reset signal,
A dedicated timing circuit for sequentially inputting and sampling a plurality of mode setting contents is provided inside.

Further, although an external circuit for sequentially inputting a plurality of mode setting contents to the mode selection signal input terminal is considered to be relatively complicated, in the embodiment of the Japanese Patent Laid-Open No. 3-191433, a microcomputer is used. Such a circuit is provided internally so that a signal for defining the mode setting content is output from the output terminals OA1 and OA2. For example, in FIG. 4 of JP-A-3-191433, an input terminal EA (considered to be the MOD terminal in FIG. 1)
By connecting any of the output terminals OA1 and OA2 to the power supply VDD or the ground GND, it is possible to set the internal mode as shown in FIG.

[0010]

However, in the above-mentioned Japanese Patent Laid-Open No. 3-257685, the external reset signal input to the microcomputer is raised a plurality of times according to the setting contents of the plurality of modes to be set, It is necessary to provide a relatively complicated circuit outside the microcomputer for setting a plurality of modes from a single mode selection signal input terminal in synchronization with the start-up. There is a problem in that such a complicated circuit imposes a burden on the user of the microcomputer.

Further, in this Japanese Patent Laid-Open No. 3-257685, since a plurality of modes are set while raising the external reset signal a plurality of times as described above, it is natural that the external reset signal is raised carelessly. However, unintended mode settings are made. Further, since the function of such a mode setting is added to the external reset signal input to the external reset signal input terminal, the compatibility with a past microcomputer having no such function is lost. There is also.

Next, in the above-mentioned Japanese Patent Laid-Open No. 3-191433, a microcomputer for sequentially inputting a plurality of mode setting contents into a single mode selection signal input terminal for sequentially setting a plurality of mode settings It requires an external, relatively complex circuit. There is a problem that such a complicated circuit imposes a burden on the user of the microcomputer.

Incidentally, as in the above-mentioned embodiment of Japanese Patent Laid-Open No. 3-191433, such a circuit which becomes relatively complicated can be provided inside the microcomputer.
However, in the case of providing the inside of the microcomputer as described above, the method disclosed in Japanese Patent Laid-Open No. 3-191433
Of the above-mentioned output terminals OA1 and OA as shown in FIG.
2 is required, and there is a problem that more terminals are required to be provided in the package of the microcomputer.

Further, if the output terminals OA1 and OA2 are provided, there is a problem that compatibility with past microcomputers that do not have such a plurality of mode setting functions is lost. JP-A-3-191433
It is stated that the output terminals OA1 and OA2 can be used for other purposes other than the mode setting, and can be used as a general-purpose output terminal, for example. However, in any case, these output terminals OA1 and OA2 cannot be used as general-purpose output terminals at least during the mode setting, which causes a problem in compatibility.

In the microcomputer, a new function may be added, and for example, a mode setting which is not available in the past may be performed. Even when a new function is added in this way, it is preferable to maintain compatibility with past microcomputers. However, as described above, JP-A-3-257685 and JP-A-3-257685
In 191433, there is a problem that compatibility with past microcomputers that do not require mode setting is lost.

The present invention has been made in order to solve the above-mentioned conventional problems, in which a desired mode setting in the microcomputer according to a plurality of bits from the outside of the microcomputer can be input with less input of the microcomputer. Using terminals and output terminals, it is possible to do it with a relatively simple circuit, and it is easier to maintain compatibility with past microcomputers that do not have the function of mode setting of multiple bits. It is an object of the present invention to provide a microcomputer capable of performing.

[0017]

According to the present invention, instruction codes are sequentially fetched from an external memory, and a program based on a plurality of the instruction codes is processed while inputting / outputting data to / from the outside as needed. In a microcomputer, an external reset signal input terminal for inputting an external reset signal for initializing processing inside the microcomputer, a first mode setting, and a second mode setting that can be set after the first mode setting Each of the mode setting contents is used for inputting a mode selection signal for sequentially transmitting in this order, and for controlling the fetching of the instruction code to the outside or controlling the input / output of the data to the outside. The initial logical state after release of the reset by the external reset signal is the second mode An external control signal output terminal that outputs an external control signal that changes before a fixed timing; and a timing that captures and stores the first mode setting indicated by the mode selection signal at the timing of a change in the logical state of the external reset signal. By providing a first mode setting storage element and a second mode setting storage element that captures and stores the second mode setting indicated by the mode selection signal at the timing of a change in the logical state of the external control signal, According to the contents stored in the first mode setting storage element and the contents stored in the second mode setting storage element, a desired mode setting in the microcomputer is performed, thereby solving the above problems. is there.

Further, in the above microcomputer,
Each of the first mode setting and the second mode setting is used as the mode selection signal by inputting a steady L state to the mode selection signal input terminal, or as the mode selection signal, the mode selection signal is input. Either a steady H state is input to the signal input terminal or a signal according to the external control signal is input to the mode selection signal input terminal as the mode selection signal. By doing so, the above problems can be solved, and the first mode setting and the second mode setting can be performed.
The signal for inputting to the mode selection signal input terminal for setting the mode setting is a signal in accordance with the steady L state, the steady H state, or the external control signal output from the microcomputer. Therefore, the circuit provided by the user outside the microcomputer is further reduced, and the burden on the user is reduced.

The present invention does not particularly limit the external control signal. The external control signal of the present invention only needs to change the initial logical state as described above. Many of these signals are originally provided in many microcomputers, and the signals that have been provided conventionally for controlling the fetching of the instruction code to the outside and the control of the input / output of data to the outside. Therefore, there is a signal that is conventionally provided.

For example, in the Z80 manufactured by Zylog,
In the reset state by the external reset signal, the memory read signal (RD bar) is in the H state, the instruction code take-in signal (M1 bar) is in the H state, and the address signals are all in the high impedance state. The address signal is "FFFF" in hexadecimal. After the reset is released, the memory read signal (RD bar) and the instruction code fetch signal (M1 bar) are both in the L state for fetching the first instruction code after the reset is released. Also, the address signal is "0000" in hexadecimal. Therefore, it is conceivable to use these memory read signal (RD bar), command code fetch signal (M1 bar) or address signal as the external control signal of the present invention. Further, when the address signal is used as the external control signal of the present invention, if the address signal is pulled up in Z80, all the bits of the address signal are fetched at the time of fetching the first instruction code after reset release. Since the logic state changes from the H state to the L state, it is possible to use any one bit, and in this case, it is not necessary to decode the address signal.

In the microcomputer,
The external control signal changes an initial logical state after release of reset by the external reset signal at the time of fetching the first instruction code after release of the reset,
With the signal used for controlling the fetching of the instruction code to the outside, the above problem is solved and
While it is possible to use the signal originally provided by the microcomputer for controlling the fetching of the instruction code to the outside, at the same time, the mode setting is completed at a relatively early stage of fetching the first instruction code. It was made possible.

The present invention is not specifically limited to the use for controlling the fetching of the instruction code to the outside of such a microcomputer. A signal used for controlling the fetching of such an instruction code is, for example, a memory read signal (R
D bar), command code fetch signal (M1 bar), address signal, etc.

In the above microcomputer,
The external control signal is at least two kinds of signals, that is, a mode-capturing external control signal and a mode-setting external control signal whose timings of change of the initial logic state are different from each other. It is a signal indicating the instruction code fetch timing when the logic state changes at the timing of fetching the first instruction code after the reset is released by the external reset signal, and the second mode setting storage A signal used to indicate the fetch timing of the second mode setting in the device, while the mode setting external control signal fetches the first instruction code after the reset is released by the external reset signal. Is a signal indicating that the instruction code is being fetched by changing the logic state before the timing of Since the signal is used by being input to the mode selection signal input terminal as the mode selection signal, it is possible to solve the problems described above and to make it easier to set the mode from the outside of the microcomputer. This is a more specific microcomputer that takes into consideration the timing of taking it into the microcomputer after the above. That is, the external control signal is of two types in which the timing of the mode acquisition external control signal and the timing of the mode setting external control signal are different from each other, and the timing design is sufficiently taken into consideration. The initial logic state of the mode fetching external control signal changes at an earlier timing than that of the mode setting external control signal. Therefore, the mode setting is performed at the timing of the change of the initial logical state of the mode setting external control signal that occurs at an early timing, and then the mode set at the timing of the change of the initial logical state of the mode acquisition external control signal is set. It can be captured, and the set mode can be captured reliably.

The principle of the present invention will be briefly described below.

The present invention has been made by finding and paying attention to the following facts.

That is, first, when setting the two modes of the microcomputer, it is not necessary to perform all of them at the same time during the reset by the external reset signal. Depending on the mode to be set, there is often no problem even if the setting timing is delayed after resetting. For example, in the mode B of the first and second embodiments described later, the setting of whether to set the mode B1 or the mode B2 may be performed before the I / O access, and the mode setting may be set a little after the reset is released. It doesn't matter if you are late.

Here, when a plurality of modes are set from a single mode selection signal input terminal, when the contents of each mode setting are sequentially input, a circuit inside the microcomputer for performing the setting and a microcomputer. It is necessary to establish some kind of synchronization with the external circuit. That is,
With the internal circuit of the microcomputer and the external circuit,
It is necessary to synchronize each input of the mode setting contents sequentially input from the mode selection signal input terminal.

In order to achieve such synchronization, it is necessary for the internal circuit side of the microcomputer to take the initiative in timing and output a signal for achieving timing synchronization from the inside of the microcomputer to the outside. Alternatively, it is necessary for the circuit side outside the microcomputer to take the initiative in timing control, and to input some signal from outside the microcomputer to inside for timing synchronization.

However, it is not preferable to provide a dedicated terminal in the package of the microcomputer in order to input and output such a signal for synchronizing the timing because the number of terminals on the package is reduced.
Therefore, in the present invention, the microcomputer is originally designed to realize the function originally possessed by the microcomputer, that is, sequentially fetching the instruction code from the external memory and inputting / outputting the data to / from the outside when necessary. The external control signal that is held is also used for such timing synchronization.

That is, in order to set the mode, the operation timing inside the microcomputer is controlled based on the external reset signal and the external control signal. On the other hand, the timing of the operation of the circuit outside the microcomputer for setting the mode is similarly performed according to the external reset signal and the external control signal. Since both the external reset signal and the external control signal are input signals or output signals to the outside of the microcomputer originally provided in the microcomputer, the internal and external of the microcomputer must be synchronized to synchronize the timing of mode setting. No new signal need be provided, and no new terminal need be provided in the package of the microcomputer.

As described above, in the present invention, the operation timing is controlled in accordance with the external reset signal and the external control signal, and the first mode setting storage element and the second mode setting storage element included in the present invention have these external reset signals. And the external control signal controls the operation timing. or,
This control does not particularly require a new input signal or output signal to the outside of the microcomputer. Therefore, according to the present invention, a desired mode setting inside the microcomputer can be performed according to the contents stored in the first mode setting storage element and the contents stored in the second mode setting storage element. , According to a plurality of bits from the outside of the microcomputer, a desired mode setting inside the microcomputer, using a smaller number of input terminals and output terminals of the microcomputer, with a relatively simple circuit, It is possible to more easily maintain compatibility with past microcomputers that do not have the function of mode setting of multiple bits.

Among the mode settings made by the microcomputer, the setting of the priority order of non-maskable interrupts and the prohibition of use of the internal ROM (read only memory) as mentioned in the above-mentioned Japanese Patent Laid-Open No. 3-191433. Basically, it needs to be decided before the microcomputer starts normal operation. Therefore, in the present invention, those that need to be set before the normal operation of the microcomputer is set in the first mode setting in the present invention.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

First, modes to be set in the microcomputers of the first and second embodiments to which the present invention is applied will be described.

The modes of the microcomputers of the first and second embodiments of the present invention are roughly classified into two modes, mode A and mode B. The mode B is composed of two types, mode B1 and mode B2. Therefore,
In addition to the mode A, the modes of the microcomputers of these embodiments are the mode 3 of the mode B1 and the mode B2.
Mode. Also, these modes A, B1 and B
2 each have a memory access timing and I / O
The access timing is shown in Table 1 below. That is, first, in mode A, the memory access timing is 3 clocks and the I / O access timing is 4 clocks. In mode B1, the memory access timing is 3 clocks and the I / O access timing is 4 clocks. In the mode B2, the memory access timing is 3 clocks and the I / O access timing is 6 clocks.

[0036]

[Table 1]

Further, in the microcomputers of the first and second embodiments, the Z-log manufactured by Zilog Co. is basically used.
The same external control signal as 80 is output. That is, in the microcomputers of the first and second embodiments, the external control signal used for controlling the fetching of the instruction code to the outside or controlling the input / output of the data to the outside is the same as Z80. . For example, when an instruction code or data is input from the external memory, the memory read signal (RD bar) becomes an active state (active Low) in the L state. Further, if the instruction code to be fetched from the external memory is a particular instruction code, the instruction code fetch signal (M1 bar) also becomes the active state (active Low) in the L state.

In each of the first and second embodiments, the setting contents of the three modes shown in Table 1 above, that is, the mode A, the modes B1 and B2, are set as follows.
Sampling is performed twice from a single mode selection signal input terminal, and thus mode setting is performed twice.

That is, as shown in Table 2 below, in the first mode setting, mode A or mode B (including mode B1 and mode B2) is set. In the first mode setting, when the L state is input to the mode selection signal input terminal, the mode A
Is set, and when the H state is input to the mode selection signal input terminal, the mode B is set. When the mode B is set in the first mode setting, then either the mode B1 or the mode B2 is set in the second mode setting. In the second mode setting, when the H state is input to the mode selection signal input terminal, the mode B1 is set, and the mode selection signal input terminal is set to L.
When the state is input, the mode B2 is set.

[0040]

[Table 2]

Further, these first and second embodiments of the present invention
In the embodiment, such a first mode setting is performed at the rising edge of the external reset signal (RST bar). This external reset signal (RST bar) is active low, and when it is in the L state, it is in the reset state.
Further, in the first and second embodiments, the second mode setting is performed at the rising timing of the memory read signal (RD bar), and the mode B1 or the mode B2 is set. This memory read signal (RD bar) is active low, and is in the L state when the instruction code or the data is fetched from the external memory.

Particularly, the first memory read signal (R) after the external reset signal (RST bar) once rises.
The falling timing of (D bar) is the address "00
The first instruction code is fetched from the address "00 (hexadecimal)". Therefore, at this time, the instruction code fetch signal (M1 bar) is also in the L state.

As described above, the access made to the outside after the reset is released is the fetching of the instruction code and the reading access to the external memory. Therefore, mode A
It is necessary that the mode setting of whether the mode is the mode B or the mode B is set promptly after the reset is released. Therefore, in the first and second embodiments of the present invention, the mode setting of the mode A or the mode B is performed at the first time when the reset is released, that is, when the external reset signal (RST bar) rises. This is done as a mode setting. The first mode setting is performed by sampling the logical state of the rising timing of the external reset signal (RST bar).

On the other hand, in mode B1 or mode B2,
The mode selection of the I / O access timing may be decided before entering the I / O access. Therefore, at the timing when the memory read signal (RD bar) falls and the first instruction code is fetched, mode setting is performed from the mode selection signal input terminal as the second mode setting.

First, the first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a mode setting circuit of the microcomputer of the first embodiment to which the present invention is applied.

In the first embodiment, the external control signals of the present invention are two kinds of signals, that is, a mode-capturing external control signal and a mode-setting external control signal, which are different in the timing of change of the initial logic state. . In this embodiment, the mode capture external control signal is a memory read signal (RD bar). The mode setting external control signal is an instruction code fetch signal (M1 bar). The memory read signal (RD bar) and the instruction code fetch signal (M1 bar) are control signals originally possessed by the microcomputer of this embodiment.

In FIG. 1, the first mode setting memory element of the present invention is composed of an inverter I1 and a D-type latch L1. In such a first mode setting memory element, when the reset is released and the external reset signal (RST bar) rises, the D-type latch L1 holds the logic state of the mode selection signal input terminal MOD at the timing of this rise. . This held logical state is the first mode setting, and either mode A or mode B is set.

Next, referring to FIG. 1, the second mode setting memory element of the present invention comprises RS flip-flops FF1 and D.
It is constituted by a mold latch L2. First, when the external reset signal (RST bar) is in the L state and is in the reset state, the signal G2 output from the RS flip-flop FF1 is output.
Is in the L state. After this, when the memory read signal (RD bar) falls in order to fetch the first instruction code, the signal G2 output from the RS flip-flop FF1
Falls. Therefore, in the second mode setting storage element, when the first instruction code that changes the initial logical state at the reset state of the memory read signal (RD bar) which is an external control signal is fetched The logic state of the mode selection signal input terminal MOD at that time is held in the D-type latch L2. The logic state held in this way becomes the second mode setting, which is the second mode setting for setting the mode B1 or the mode B2.

As described above, the mode selection signal input terminal MOD
The mode A or the mode B is set by the signal Q1 output from the D-type latch L1 which holds the first sample of the logic state. Also, the mode selection signal input terminal MO
The mode B1 or the mode B2 is set by the signal Q2 output from the D-type latch L2 that holds the second sample of the D logic state.

Therefore, in this embodiment, as shown in Table 2 above, when setting the mode A, a steady L state is input to the mode selection signal input terminal MOD as a mode selection signal. That is, as shown in FIG. 2, the mode selection signal input terminal MOD is connected to the ground GND. As a result, the logic state of the mode selection signal input terminal MOD used for the first mode setting, which is sampled at the rising edge of the external reset signal (RST bar), is L.
State. Further, the logic state of the mode selection signal input terminal MOD used in the second mode setting, which is sampled at the falling edge of the memory read signal (RD bar), also becomes the L state.

Next, when setting the mode B1, since a steady H state is input to the mode selection signal input terminal MOD as a mode selection signal, the mode selection signal input terminal MOD is connected to the power supply VDD as shown in FIG. To do. Then
Mode selection signal input terminal M for the first mode setting
The logic state of OD becomes the H state, the logic state of the mode selection signal input terminal MOD at the time of the second mode setting becomes the H state, and the mode B1 is set.

Next, when setting the mode B2, an instruction code fetch signal (M1 bar) corresponding to the external control signal of the present invention is input to the mode selection signal input terminal MOD as a mode selection signal as shown in FIG. Enter as shown. This command code fetch signal (M1 bar) is an output signal originally possessed by the microcomputer of this embodiment. By inputting the instruction code fetching signal (M1 bar) to the mode selection signal input terminal MOD in this manner, the first
The H state is fetched in the second mode setting, and the L state is fetched in the second mode setting.
Is set.

FIG. 5 is a time chart showing the operation of this embodiment.

FIG. 5 shows the timing when the instruction code fetch signal (M1 bar) is input to the mode selection signal input terminal MOD to set the mode B2.

In FIG. 5, the external reset signal (RST bar) is first in the L state, and the microcomputer of this embodiment is in the reset state. After this, when the external reset signal (RST bar) rises to release the reset, the inverter I1
The signal G1 output from the device falls. When the signal G1 falls, the logic state of the mode selection signal input terminal MOD at this time, that is, the H state is fetched and held in the D-type latch L1. Therefore, the signal Q1 output from the D-type latch L1 thereafter is held in the H state. This signal Q1 is for setting the mode A or the mode B. When the signal Q1 is in the H state, the mode B is selected.

After this, the mode selection signal input terminal MOD to which the instruction code fetch signal (M1 bar) is input.
Falls at time t12. This is to capture the first instruction code. Then, the time t12
After that, the signal Q2 output from the D-type latch L2 also becomes the L state. However, at the time t12, the D-type latch L2 does not hold the logic state.

After this, the memory read signal (RD bar) falls. This is to capture the first instruction code. When the memory read signal (RD bar) falls in this way, the signal G2 falls at time t13. When the signal G2 falls, the logic state of the mode selection signal input terminal MOD at this time, that is, the L state is held by the D-type latch L2. Because it is held in this way, D
The signal Q2 output from the mold latch L2 is then in the L state. The signal Q2 is used to set the mode B1 or the mode B2. In the time chart of FIG. 5, since the signal Q2 is in the L state, the mode B2 is selected.

As described above, according to this embodiment,
The mode A, B1, or B2 can be set depending on whether the mode selection signal input terminal MOD is connected to the ground GND, the power supply VDD, or the instruction code fetch signal (M1 bar) is input. Thus, in this embodiment, the three modes A, B1 and B are
The terminal of M1 provided for setting 2 is only the mode selection signal input terminal MOD. As described above with reference to FIGS. 2 to 4, the circuit outside the microcomputer for setting the mode is only the wiring for the ground GND, the power supply VDD, or the command code capture signal (M1 bar), and It is very easy to use. Therefore, according to the present invention, a desired mode setting inside the microcomputer according to a plurality of bits from the outside of the microcomputer can be performed by using a relatively simple circuit using less input terminals and output terminals of the microcomputer. It is also possible to obtain an excellent effect that it is possible to easily maintain compatibility with past microcomputers that do not have the function of mode setting of multiple bits like this. .

Here, the compatibility of the present embodiment with a conventional microcomputer in which the mode A, B1 or B2 is not set will be considered. Then, the difference of this embodiment from the conventional one is only the presence or absence of the mode selection signal input terminal MOD. The mode of the conventional microcomputer is assigned to the mode A, and the mode selection signal input terminal MOD is set to the H state. If fixed, the microcomputer of the present embodiment can be used in the same manner as such a conventional microcomputer, and it is possible to maintain complete compatibility in terms of operation and the like.

The second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is a circuit diagram of a mode setting circuit of the microcomputer of the second embodiment to which the present invention is applied.

In the second embodiment, the external control signal of the present invention is a memory read signal (RD bar).
This memory read signal (RD bar) is a signal originally included in the microcomputer of this embodiment. In this embodiment, the memory read signal (RD bar) determines the timing of the second mode setting, and when setting the mode B2, the memory read signal (RD bar) is set to the mode selection signal input terminal MOD. I also try to enter.

In FIG. 6, the first mode setting memory element of the present invention is composed of an inverter I2 and a D-type latch L5. The configuration and operation of the first mode setting storage element of this embodiment are the same as those of the first embodiment described above.

Next, in FIG. 6, the second mode setting storage element of the present invention is composed of D-type latches L3 and L4, an AND logic gate D1, an RS flip-flop FF2, and a D-type latch L6. .

Here, the RS flip-flop FF2 and the D-type latch L6 of the present embodiment operate in the same manner as the RS flip-flop FF1 and the D-type latch L2 of the first embodiment described above.

Further, the D-type latches L3 and L4 and the AND logic gate D1 of the present embodiment delay the fall of the memory read signal (RD bar) until the next rise of the clock signal CLK (R1 bar). Is a circuit for generating. In this way, in order to set the mode B2, the memory read signal (RD bar) is input to the mode selection signal input terminal MOD in order to delay the fall of the signal (R1 bar). In addition, the D-type latch L6 can correctly take in the logic state of the mode selection signal input terminal MOD. Memory read signal (RD) input to mode selection signal input terminal MOD
If the logic state of the bar) is read at the trailing edge of the memory read signal (RD bar) itself, it may not be read correctly, so such a delay is performed. By delaying the falling timing of the signal (R1 bar), the timing held by the D-type latch L6 is delayed, and the logical state of the mode selection signal input terminal MOD is stabilized, and the D-type latch L6 changes the logical state. Can be captured and retained.

In the present embodiment, when the mode A is set, a steady L state is input to the mode selection signal input terminal MOD as a mode selection signal, so that the mode selection signal input terminal is input as shown in FIG. MOD to Grand GND
Connect to As a result, the logic state of the mode selection signal input terminal MOD at the time of the first mode setting becomes the L state, and the logic state of the mode selection signal input terminal MOD at the time of the second mode setting becomes the L state. Mode A
Is set.

Next, when setting the mode B1 in the present embodiment, since a steady H state is input to the mode selection signal input terminal MOD as a mode selection signal, the mode selection signal input terminal MOD is input as shown in FIG. Is connected to the power supply VDD. As a result, the mode selection signal input terminal MOD is in the H state during the first mode setting, and the mode selection signal input terminal MOD is in the H state during the second mode setting, so that the mode B1 is set. .

Next, when setting the mode B2 in the present embodiment, as a mode selection signal, a memory read signal (RD) corresponding to the external control signal of the present invention is input to the mode selection signal input terminal MOD as shown in FIG. Bar). Then, in the first mode setting performed at the timing when the signal G1 falls, the mode selection signal input terminal MOD is in the H state. At the time of the second mode setting performed at the timing when the signal G2 falls, the mode selection signal input terminal MOD is in the L state. Therefore, mode B2
Is set.

FIG. 10 is a time chart showing the mode setting operation of this embodiment.

In the time chart of FIG. 10, the memory read signal (R
The operation when inputting (D bar) to set the mode B2 is shown.

In FIG. 10, first in the initial stage,
When the external reset signal (RST bar) is in the L state, the microcomputer of this embodiment is in the reset state. After this, at time t21, an external reset signal (RST bar)
Is reset and the reset is released, the inverter I
The signal G1 output by 2 falls, and the D-type latch L5 captures the logic state (H state) of the mode selection signal input terminal MOD at the time t21. Therefore, the time t2
After 1, the D-type latch L5 holds the H state and outputs the signal Q1 in the H state.

Thereafter, at time t22, the memory read signal (RD bar) falls (active Lo) in order to fetch the first instruction code after reset release.
w). Since the memory read signal (RD bar) is also input to the mode selection signal input terminal MOD, the mode selection signal input terminal MOD also falls at the time t22. When the mode selection signal input terminal MOD falls, the output Q2 of the D-type latch L6 also falls. The D-type latch L5 receives the signal G1 input to the input G as L
Since it is in the state, it keeps the H state and outputs its output Q1.
Remains in the H state.

At time t23, the clock signal CLK rises. Then, since the D-type latch L3 takes in the memory read signal (RD bar) in the L state, the D-type latch L3
The signal (SRD bar) output by 3 falls. At this time, the signal (SSRD bar) is in the H state, and the signal (SRD bar) is
The signal (R1 bar) output from the AND logic gate D1 falls due to the logical operation with the bar. Further, when the signal (R1 bar) falls, the RS flip-flop F
The signal G2 output by F2 falls. Then, the D-type latch L6 which inputs the signal G2 holds the logic state of the mode selection signal input terminal MOD at the falling timing of the signal G2 at time t24, and outputs the held logic state as the signal Q2. .

At the time t21, the output Q1 for setting the mode A or the mode B is held and the time t2 is reached.
When the output Q2 for setting the mode B1 or the mode B2 is held in 4, the mode setting in the present embodiment is almost completed. That is, the mode B2 is set correctly.

The operation of this embodiment after this is as follows.

At time t25, the clock signal CLK rises. Then, the D-type latch L4 receives the L-state signal (SR
Since D bar is taken in, the signal (SSRD bar) output from the D-type latch L4 falls. At this time, the signal (SRD bar) is in the L state, and the signal (SSRD bar) is
Is in the L state, the signal (R1 bar) output from the AND logic gate D1 rises.

At time t26, the memory read signal (RD bar) rises due to the end of the fetching of the first instruction code after the reset release. Since the memory read signal (RD bar) is input to the mode selection signal input terminal MOD, the signal of the mode selection signal input terminal MOD also rises at time t26. When the clock signal CLK rises at time t27, the signal (SRD bar) also rises. When the clock signal CLK rises at time t28, the signal (SSRD bar) also rises.

As described above, in the present embodiment, the present invention can be applied while using the memory read signal (RD bar) as the external control signal of the present invention. In the present embodiment, in the D-type latches L3 and L4 and the AND logic gate D1, the memory read signal (RD bar) is sampled twice at the rising edge of the clock signal CLK, and the RS flip-flop FF2 is reset depending on the difference between the logic states. As a result, the signal G2 falls, and when the signal G2 falls, the D-type latch L6 is used to select the mode selection signal input terminal MO.
D is sampled and the output Q2 is held.
Also in this embodiment, a desired mode setting in the microcomputer according to a plurality of bits from the outside of the microcomputer can be performed relatively easily by using less input terminals and output terminals of the microcomputer. It is possible to obtain an excellent effect that it can be performed by a circuit and can easily maintain compatibility with past microcomputers that do not have such a function of setting a mode of multiple bits. it can.

In the first and second embodiments described above, a total of three mode settings of modes A, B1 and B2 are required. Here, in these embodiments, for example, when a total of four modes need to be set, it is also considered to distinguish and set such four modes. That is, in addition to the three modes shown in Tables 1 and 2, the L state is input to the mode selection signal input terminal in the first mode setting and the H state is input to the mode selection signal input terminal in the second mode setting. Consider also the fourth mode setting of inputting. Here, the L state is set in the fourth mode, that is, the first mode setting, and the H state is set in the second mode setting.
For the mode setting for setting the state, one inverter gate is used outside the microcomputer, and the instruction code fetch signal (M1 bar) output from the microcomputer is inverted by the inverter and input to the mode selection signal input terminal MOD. Just do it.

[0082]

As described above, according to the present invention, a desired mode setting inside the microcomputer can be set in accordance with a plurality of bits from the outside of the microcomputer by using less input terminals and output terminals of the microcomputer. Microcomputers that can be used with a relatively simple circuit and can more easily maintain compatibility with past microcomputers that do not have such multi-bit mode setting function. The excellent effect of being able to provide a computer can be obtained. In the present invention, one mode selection signal input terminal can be used to select three modes or four modes. At this time, the control signal originally included in the microcomputer used for fetching the first instruction code after the reset is released is effectively used as the external control signal of the present invention, and is input to the mode selection signal input terminal. The timing generation circuit for sampling the mode selection signal can be simplified and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a mode setting circuit of a microcomputer of a first embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram showing a connection when setting a mode A in the first embodiment.

FIG. 3 is a circuit diagram showing a connection when setting a mode B1 in the first embodiment.

FIG. 4 is a circuit diagram showing a connection when setting a mode B2 in the first embodiment.

FIG. 5 is a time chart showing the operation of the mode setting circuit of the first embodiment.

FIG. 6 is a circuit diagram of a mode setting circuit of a microcomputer according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing connections when setting a mode A in the second embodiment.

FIG. 8 is a circuit diagram showing a connection when setting a mode B1 in the second embodiment.

FIG. 9 is a circuit diagram showing a connection when setting a mode B2 in the second embodiment.

FIG. 10 is a time chart showing the operation of the mode setting circuit of the second embodiment.

[Explanation of symbols]

L1 to L6 ... D-type latch FF1, FF2 ... RS flip-flop I1, I2 ... Inverter D1 ... AND logic gate MOD ... Mode selection signal input terminal (RD bar) ... Memory read signal (M1 bar) ... Instruction code fetch signal (RST Bar) ... external reset signal CLK ... clock signal G1, G2, Q1, Q2, (SRD bar), (SSRD)
Bar), (R1 bar) ... signal

Claims (4)

[Claims] 1. A microcomputer in which instruction codes are sequentially fetched from an external memory, and a program by a plurality of the instruction codes is processed while inputting / outputting data to / from the outside as necessary, the inside of the microcomputer. An external reset signal input terminal for inputting an external reset signal for initializing the processing of step 1, and a second mode setting that can be set after the first mode setting and the first mode setting. A mode selection signal input terminal for inputting a mode selection signal sequentially transmitted in this order, and a reset by the external reset signal used for controlling the fetching of the instruction code to the outside or the input / output of the data to the outside. The initial logic state after release is changed before the timing of the second mode setting. And the external control signal output terminal for outputting an external control signal, the timing of the logic state change of the external reset signal,
A first mode setting storage element that captures and stores the first mode setting indicated by the mode selection signal; and a second mode setting indicated by the mode selection signal at the timing of a change in the logical state of the external control signal. By including a second mode setting storage element for capturing and storing, according to the content stored in the first mode setting storage element and the content stored in the second mode setting storage element,
A microcomputer characterized in that a desired mode is set in the microcomputer. 2. A constant L state is input to the mode selection signal input terminal as the mode selection signal according to each of the first mode setting and the second mode setting. , A steady H state is input to the mode selection signal input terminal as the mode selection signal, or a signal according to the external control signal is input to the mode selection signal input terminal as the mode selection signal. The microcomputer characterized by performing either of the selective inputs. 3. The external control signal according to claim 1 or 2, wherein the external control signal has an initial logic state after release of reset by the external reset signal when the first instruction code is taken after release of the reset. Changes to
A microcomputer used as a signal for controlling the fetching of the instruction code to the outside. 4. The external control signal according to claim 2, wherein the external control signal is at least two types of signals, a mode-capturing external control signal and a mode-setting external control signal, the timings of changes in the initial logical states differ from each other. The mode fetch external control signal is a signal indicating the instruction code fetch timing when the logic state changes at the timing of fetching the first instruction code after the reset is canceled by the external reset signal. hand,
In addition, the second mode setting storage element is a signal used to indicate the timing of loading the second mode setting, and the mode setting external control signal is a signal after the reset release by the external reset signal. It is a signal indicating that the logic state has changed before the first fetching of the instruction code and the instruction code is being fetched, and is also input to the mode selection signal input terminal as the mode selection signal. A microcomputer characterized by being a signal to be used.