JPH09213738A - Method for manufacturing semiconductor device and substrate holder for mounting semiconductor element - Google Patents
Method for manufacturing semiconductor device and substrate holder for mounting semiconductor elementInfo
- Publication number
- JPH09213738A JPH09213738A JP8014951A JP1495196A JPH09213738A JP H09213738 A JPH09213738 A JP H09213738A JP 8014951 A JP8014951 A JP 8014951A JP 1495196 A JP1495196 A JP 1495196A JP H09213738 A JPH09213738 A JP H09213738A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- mounting
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】 (修正有)
【課題】 半導体素子と回路基板とをより確実に安定し
て電気的に接続することで、極めて品質の安定した、生
産性の良い半導体装置及びその製造方法を提供する。
【解決手段】 回路基板1と、先端に未硬化の導電性接
着剤5が塗布された突起電極4が電極端子3a上に形成
された半導体素子3を予め準備し、半導体素子3を実装
しようとする回路基板1の半導体素子実装領域の形状を
平坦化するために回路基板1を基板保持具2a,2bに
装着した後、半導体素子3を回路基板1上の半導体素子
実装領域にフェースダウンで実装し、未硬化の導電性接
着剤5を硬化させ、さらに半導体素子3と回路基板1の
表面との間を封止材料により被覆し硬化した後に、回路
基板1を基板保持具2a,2bから取り外す逐次的工程
からなる半導体装置の製造方法。
(57) [Abstract] (Modified) [PROBLEMS] Semiconductor device and circuit board are more reliably and stably electrically connected to each other, whereby a semiconductor device having extremely stable quality and high productivity, and a manufacturing method thereof. I will provide a. A semiconductor device (3) having a circuit board (1) and a protruding electrode (4) having an uncured conductive adhesive (5) applied on its tip is formed on an electrode terminal (3a) in advance, and the semiconductor device (3) is mounted. After mounting the circuit board 1 on the board holders 2a and 2b in order to flatten the shape of the semiconductor element mounting area of the circuit board 1, the semiconductor element 3 is mounted face down on the semiconductor element mounting area on the circuit board 1. Then, the uncured conductive adhesive 5 is cured, and the space between the semiconductor element 3 and the surface of the circuit board 1 is covered with a sealing material and cured, and then the circuit board 1 is removed from the board holders 2a and 2b. A method for manufacturing a semiconductor device, which comprises sequential steps.
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にフリップチップ実装技術を用いた半導体装置の製造
方法及び半導体装置実装用の回路基板を保持するための
保持具に関するものである。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device manufacturing method using a flip chip mounting technique and a holder for holding a circuit board for mounting the semiconductor device.
【0002】[0002]
【従来の技術】近年、半導体素子の集積度が高くなり、
半導体装置の小型化及び接続端子の狭ピッチ化が進み、
そのためフリップチップ実装技術用いた半導体装置の開
発が盛んに行われている。以下図面を参照しながら、従
来のフリップチップ実装技術を用いた半導体装置の一例
について説明する。2. Description of the Related Art In recent years, the degree of integration of semiconductor elements has increased,
As the miniaturization of semiconductor devices and the narrower pitch of connection terminals have progressed,
For this reason, semiconductor devices using flip chip mounting technology have been actively developed. Hereinafter, an example of a semiconductor device using a conventional flip chip mounting technique will be described with reference to the drawings.
【0003】図7に、従来のフリップチップ実装技術を
用いた半導体装置の断面図を示す。半導体素子101の
素子形成面上にはアルミ電極端子102が形成され、ア
ルミ電極端子102以外の部分はSi酸化膜あるいは窒
化膜等からなる絶縁膜103で覆われている。アルミ電
極端子102面上には、Au、Cu等の導電性金属材料
からなるバンプ(突起電極)104が形成されている。
一方、回路基板105の主面上には、所望の回路パター
ン106及び電極端子107が形成されている。なお、
回路基板105の基板材質としては、絶縁性及び剛性を
有し変形が生じにくい(0.4mm 以上の厚みを有す
る)、良好な平坦精度を有すセラミック材料が主に使用
される。端子電極107は回路パターン106に接続さ
れ、フリップチップ実装の際、半導体素子101と電気
的接続を行う。バンプ(突起電極)104と電極端子1
07とは、導電性接着剤108により電気的に接続され
ている。導電性接着剤108はAg、Cu、Ni等の導
電性金属材料の粉体を樹脂中に含んだ接着剤である。半
導体素子101と回路基板105の間の隙間部は、絶縁
樹脂(封止材料)109が充填されている。絶縁樹脂1
09が硬化されると、その硬化収縮応力により半導体素
子101と回路基板105を接着した後、強力に引きつ
けて固定する。そのため、半導体装置における半導体素
子101と回路基板105の接続の機械的強度を高めら
れ、安定を保たれる。FIG. 7 shows a sectional view of a semiconductor device using a conventional flip-chip mounting technique. Aluminum electrode terminals 102 are formed on the element formation surface of the semiconductor element 101, and the portions other than the aluminum electrode terminals 102 are covered with an insulating film 103 made of a Si oxide film, a nitride film, or the like. Bumps (projection electrodes) 104 made of a conductive metal material such as Au or Cu are formed on the surface of the aluminum electrode terminal 102.
On the other hand, a desired circuit pattern 106 and electrode terminals 107 are formed on the main surface of the circuit board 105. In addition,
As a substrate material of the circuit board 105, a ceramic material having insulation and rigidity, which is unlikely to be deformed (having a thickness of 0.4 mm or more), and having good flatness accuracy is mainly used. The terminal electrode 107 is connected to the circuit pattern 106 and electrically connected to the semiconductor element 101 during flip-chip mounting. Bump (projection electrode) 104 and electrode terminal 1
07 is electrically connected by a conductive adhesive 108. The conductive adhesive 108 is an adhesive containing a powder of a conductive metal material such as Ag, Cu or Ni in a resin. The gap between the semiconductor element 101 and the circuit board 105 is filled with an insulating resin (sealing material) 109. Insulating resin 1
When 09 is hardened, the hardening shrinkage stress bonds the semiconductor element 101 and the circuit board 105, and then strongly attracts and fixes them. Therefore, the mechanical strength of the connection between the semiconductor element 101 and the circuit board 105 in the semiconductor device can be increased and the stability can be maintained.
【0004】以上のように構成された従来の半導体装置
の製造方法を、図8のプロセスを示す工程図を用いて説
明する。まず、通常の半導体プロセスにおいて所望の素
子や配線及び絶縁膜103を形成した半導体素子101
を多数個形成した半導体ウエハを作製する。次に、アル
ミ電極端子102にプローブを接触させ電気的検査を行
い半導体素子101の良否を判定したうえで、バンプ
(突起電極)104を形成した後、良好な平面精度を有
す平板に押し当てる等して、バンプの高さを均一にする
平坦化加工を行う。さらに、半導体ウエハを個々の半導
体素子101に切断する。一方、予めAuやCu等の導
電性金属材料を用いて、絶縁物からなる回路基板105
上に所望の回路パターン106や電極端子107を形成
しておき、この回路基板105上に導電性接着剤108
を介して、所定の電極端子107とバンプ(突起電極)
104が当接して電気的接続が行えるように半導体素子
101をフェースダウンにて配置する。その後、加熱処
理を行い導電性接着剤108を硬化させ、電気検査を行
い動作状態を確認する。そして正常な動作を確認した
後、半導体素子101と回路基板105の間に液状のエ
ポキシ系等の絶縁性を有する樹脂109を毛細管現象を
利用して充填する。充填完了後、加熱処理等を行い絶縁
樹脂109を硬化させてフリップチップ実装を行う。A conventional method of manufacturing a semiconductor device having the above structure will be described with reference to the process diagram of FIG. First, a semiconductor element 101 in which a desired element or wiring and an insulating film 103 are formed in a normal semiconductor process
A semiconductor wafer having a large number of formed is manufactured. Next, after a probe is brought into contact with the aluminum electrode terminal 102 to perform an electrical inspection to determine the quality of the semiconductor element 101, a bump (protruding electrode) 104 is formed, and then pressed against a flat plate having good plane accuracy. Then, flattening processing is performed to make the bump height uniform. Further, the semiconductor wafer is cut into individual semiconductor elements 101. On the other hand, the circuit board 105 made of an insulating material is used in advance by using a conductive metal material such as Au or Cu.
A desired circuit pattern 106 and an electrode terminal 107 are formed on the circuit board 105, and a conductive adhesive 108 is formed on the circuit board 105.
Via a predetermined electrode terminal 107 and bump (projection electrode)
The semiconductor element 101 is arranged face down so that the semiconductor elements 101 can be brought into contact with each other for electrical connection. After that, heat treatment is performed to cure the conductive adhesive 108, and an electrical inspection is performed to confirm the operating state. After confirming the normal operation, a liquid epoxy resin 109 having an insulating property is filled between the semiconductor element 101 and the circuit board 105 by utilizing the capillary phenomenon. After the filling is completed, heat treatment or the like is performed to cure the insulating resin 109 and flip-chip mounting is performed.
【0005】以上のようにしてフリップチップ実装技術
を用いた半導体装置を製造していた。As described above, the semiconductor device using the flip chip mounting technique has been manufactured.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置の構成及び製造方法では、図9に示すよ
うに、回路基板105aの基材として、有機材質から成
る樹脂基板や、無機材質からなるセラミック基板等にお
いても比較的、板厚の薄い基板(0.4mm より厚みの
薄い基板)においては、従来使用されている板厚の厚い
回路基板105に比べ、剛性が弱く容易に変形するの
で、例えば回路パターン106等のような非対称で不均
一に描かれたような、不均一に存在する形成物により発
生する不均一な熱応力による変形が生じ、局所的な反り
やうねりとなることが知られている。However, in the above-described conventional semiconductor device structure and manufacturing method, as shown in FIG. 9, the base material of the circuit board 105a is made of a resin substrate made of an organic material or an inorganic material. Even in the case of a ceramic substrate or the like, a relatively thin plate (a substrate having a thickness smaller than 0.4 mm) is less rigid and easily deformed as compared with the conventionally used thick circuit board 105, For example, it is known that deformation due to uneven thermal stress generated by unevenly existing formations such as asymmetrically and non-uniformly drawn such as the circuit pattern 106 causes local warpage or undulation. Has been.
【0007】図10(a)に回路基板105上の半導体
素子実装領域110の反り量の模式図、図10(b)に
従来基板(セラミック基板)における半導体素子実装領
域内の反り量のヒストグラム、図10(c)に樹脂基板
(ガラスエポキシ基板)における半導体素子実装領域内
の反り量のヒストグラムをそれぞれ示す。ここで、反り
量とは図10(a)に示す通り、回路基板105上の半
導体素子実装領域110が、水平面から、どれだけ垂直
方向へ反っているかを表す値である。FIG. 10A is a schematic diagram of the warp amount of the semiconductor element mounting region 110 on the circuit board 105, and FIG. 10B is a histogram of the warp amount in the semiconductor element mounting region of the conventional substrate (ceramic substrate). FIG. 10C shows a histogram of the amount of warpage in the semiconductor element mounting region on the resin substrate (glass epoxy substrate). Here, as shown in FIG. 10A, the warp amount is a value indicating how much the semiconductor element mounting region 110 on the circuit board 105 is warped in a vertical direction from a horizontal plane.
【0008】また図10(b)と図10(c)におい
て、グラフの横軸は反り量を示し、縦軸はその分布の割
合を百分率で示している。これらの図からわかるよう
に、従来基板(例えば、0.4mm 以上の厚みを有する
セラミック基板)の反り量は、すべて10ミクロン以下
であるが、樹脂基板(例えば、ガラスエポキシ基板や、
0.4mmより薄いセラミック基板)では、8ミクロンか
ら30ミクロンという比較的大きな反り量の分布を示し
た。In FIGS. 10 (b) and 10 (c), the horizontal axis of the graph shows the amount of warpage, and the vertical axis shows the distribution ratio in percentage. As can be seen from these figures, the warp amount of the conventional substrate (for example, a ceramic substrate having a thickness of 0.4 mm or more) is 10 μm or less, but the resin substrate (for example, a glass epoxy substrate or
Ceramic substrates thinner than 0.4 mm) exhibited a relatively large warpage distribution of 8 to 30 microns.
【0009】この回路基板105aにおいて局在する反
りやうねりのために、半導体素子実装領域内に位置する
回路基板側の電極端子107間における高さのばらつき
が大きくなる。このため半導体素子101をフェースダ
ウンにて実装した際に、凹部に位置する電極端子107
面に導電性接着剤108の接合層が到達する事ができ
ず、電気的な接続不良になるという問題点を有してい
た。図11に、回路基板の反り量に対する半導体素子と
回路基板との接続不良の発生率の一例を示す。図11の
実験結果より、図10(c)に示すような反り量が10
ミクロン以上の大きな反りやうねりを有する回路基板を
用いる場合では、半導体素子の接続不良発生率が急激に
多くなり、半導体素子実装には適さないことが分かる。Due to the warp and undulation localized in the circuit board 105a, the height variation between the electrode terminals 107 on the circuit board side located in the semiconductor element mounting region becomes large. Therefore, when the semiconductor element 101 is mounted face down, the electrode terminals 107 located in the recesses are placed.
There is a problem that the bonding layer of the conductive adhesive 108 cannot reach the surface, resulting in poor electrical connection. FIG. 11 shows an example of the incidence of connection failure between the semiconductor element and the circuit board with respect to the warp amount of the circuit board. From the experimental result of FIG. 11, the warp amount as shown in FIG.
It can be seen that when a circuit board having a large warp or waviness of a micron or more is used, the incidence of defective connection of semiconductor elements increases rapidly, which is not suitable for mounting semiconductor elements.
【0010】なお、この図11に示すグラフの値は、バ
ンプ形状や導電性接着剤の性質及び転写量等の様々な要
因にて変化する値である。The values in the graph shown in FIG. 11 are values that change due to various factors such as the bump shape, the properties of the conductive adhesive, and the transfer amount.
【0011】また、熱応力による局所的な反りやうねり
の発生は、回路基板作製工程だけでなく、フリップチッ
プ工程中における導電性接着剤や封止材料硬化等の加熱
工程においても発生するため、例えば一旦は半導体素子
実装時に、導電性接着剤108の接合層の到達が良好に
行えた後において、封止材料の硬化が終了するまでの間
で、限度を超えた局所的な反りやうねりにより、接続不
良が発生する場合もあるという問題点も有している。Further, the occurrence of local warpage or undulation due to thermal stress occurs not only in the circuit board manufacturing process but also in the heating process such as hardening of the conductive adhesive or the sealing material during the flip chip process. For example, at the time of mounting a semiconductor element, after the bonding layer of the conductive adhesive 108 has been successfully reached, until the curing of the sealing material is completed, local warping or swell exceeding the limit may occur. However, there is also a problem that connection failure may occur.
【0012】本発明は上記従来の問題点を解決するため
になされたものであり、半導体素子と回路基板をより確
実に安定して電気的に接続することで、極めて品質の安
定した、生産性の良い半導体装置及びその製造方法を提
供することを目的としている。The present invention has been made to solve the above-mentioned problems of the prior art, and by electrically connecting the semiconductor element and the circuit board more reliably and stably, the productivity is extremely stable and the quality is high. It is an object of the present invention to provide a good semiconductor device and a manufacturing method thereof.
【0013】[0013]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置の製造方法は、回路基板と、先
端に未硬化の導電性接着剤が塗布された突起電極が電極
端子上に形成された半導体素子を予め準備する工程と、
前記半導体素子を実装しようとする前記回路基板の実装
領域の面形状が、前記半導体素子の前記電極端子形成面
と略平行で、かつ平坦面となるように、前記回路基板を
保持する工程と、前記回路基板を保持した状態で、前記
半導体素子を前記回路基板上の前記実装領域内に設けら
れた入出力電極端子に、前記未硬化の導電性接着剤によ
りフェースダウンで実装する工程と、前記未硬化の導電
性接着剤を硬化させる工程と、さらに、前記半導体素子
と前記回路基板間に封止材料を充填する工程と、前記封
止材料を硬化する工程を行い、前記封止材料を硬化した
後、前記回路基板の平坦化のための保持を解除すること
を特徴とするものである。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a circuit board and a protruding electrode having an uncured conductive adhesive applied to the tip thereof on an electrode terminal. A step of preparing the formed semiconductor element in advance,
A surface shape of a mounting region of the circuit board on which the semiconductor element is to be mounted is substantially parallel to the electrode terminal forming surface of the semiconductor element, and a step of holding the circuit board so as to be a flat surface, Mounting the semiconductor element on the input / output electrode terminals provided in the mounting area on the circuit board face down with the uncured conductive adhesive while holding the circuit board; The step of curing an uncured conductive adhesive, the step of filling a sealing material between the semiconductor element and the circuit board, and the step of curing the sealing material are performed to cure the sealing material. After that, the holding for flattening the circuit board is released.
【0014】またさらに、回路基板の平坦化のための保
持方法として、回路基板を載置するための凹部を有する
基板支持台に、前記回路基板を載置し、少なくとも前記
回路基板の実装領域分の大きさの開口部を有する基板固
定蓋を前記回路基板の前記実装領域部を塞がないようし
て、前記基板支持台と位置合わせを行って固定すること
により、前記回路基板の平坦化を保持することを特徴と
するものである。Further, as a holding method for flattening the circuit board, the circuit board is placed on a board supporting base having a recess for mounting the circuit board, and at least the mounting area of the circuit board is provided. The circuit board is flattened by aligning and fixing the circuit board fixing base having the opening of the size with the circuit board supporting base so as not to block the mounting area of the circuit board. It is characterized by holding.
【0015】また、本発明の半導体素子実装用基板保持
具は、半導体素子をフェースダウンで実装するための回
路基板であって、前記回路基板の前記半導体素子の実装
領域面が、前記半導体素子の電極端子形成面と略平行か
つ、平坦となるように前記回路基板を保持することを特
徴とする。The semiconductor element mounting substrate holder of the present invention is a circuit board for mounting a semiconductor element face down, wherein the semiconductor element mounting area surface of the circuit board is the semiconductor element mounting surface. It is characterized in that the circuit board is held so as to be substantially parallel and flat with the electrode terminal forming surface.
【0016】また、本発明の半導体素子実装用基板保持
具は、回路基板を載置するための凹部を有する基板支持
台と、少なくとも前記回路基板の実装領域分の大きさの
開口部を有する基板固定蓋とからなることを特徴とする
ものである。Further, the substrate holder for mounting a semiconductor element of the present invention has a substrate support having a recess for mounting a circuit board, and a substrate having at least an opening having a size corresponding to the mounting area of the circuit board. It is characterized by comprising a fixed lid.
【0017】[0017]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面に基づき説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【0018】(実施の形態1)図1は本発明の実施の形
態1における半導体素子実装用基板保持具を用いた回路
基板の保持方法を示す概略図である。(Embodiment 1) FIG. 1 is a schematic diagram showing a method of holding a circuit board using a semiconductor device mounting board holder according to Embodiment 1 of the present invention.
【0019】この方法は、回路基板1を2枚の金属板か
らなる基板支持台2a,基板固定蓋2bからなる基板保
持具に挟み、回路基板1に垂直方向の圧力を加え、回路
基板1を平坦に保持する方法である。According to this method, the circuit board 1 is sandwiched between a board support 2a made of two metal plates and a board holder made of a board fixing lid 2b, and vertical pressure is applied to the circuit board 1 to fix the circuit board 1 in place. It is a method of holding it flat.
【0020】図1における基板保持具の基板支持台2a
は、回路基板1を定位置に固定し易くするための溝(凹
部)を設けた構造をしており、基板固定蓋2bは、回路
基板1の半導体実装領域1aに当たる部分に開口部を設
けた構造を有している。また、基板支持台2a,基板固
定蓋2bのそれぞれの外周部には、ネジ穴が設けられて
いる。The substrate support base 2a of the substrate holder shown in FIG.
Has a structure in which a groove (recess) for easily fixing the circuit board 1 in a fixed position is provided, and the board fixing lid 2b has an opening provided in a portion corresponding to the semiconductor mounting area 1a of the circuit board 1. It has a structure. Further, screw holes are provided in the outer peripheral portions of the substrate support base 2a and the substrate fixing lid 2b.
【0021】以下に、本実施の形態1の基板保持具を用
いた回路基板の保持方法について説明する。A method of holding a circuit board using the board holder of the first embodiment will be described below.
【0022】まず、基板支持台2aの中央部に設けた溝
(凹部)に、半導体素子実装面を上向きにして回路基板
1を置き、その上から、基板固定蓋2bに設けた開口部
が回路基板1の実装領域1aの外側を囲むように基板固
定蓋2bを置く。First, the circuit board 1 is placed with the semiconductor element mounting surface facing upward in a groove (recess) provided in the central portion of the board support base 2a, and the opening provided in the board fixing lid 2b is positioned above the circuit board 1. The board fixing lid 2b is placed so as to surround the outside of the mounting area 1a of the board 1.
【0023】その後、基板支持台2a,基板固定蓋2b
の外周部に設けたネジ穴にネジ2cを差し込み、ネジ2
cを締め込むことによって、垂直方向に圧力を加え、回
路基板1を保持する。After that, the substrate support base 2a and the substrate fixing lid 2b
Insert the screw 2c into the screw hole provided on the outer periphery of the
By tightening c, pressure is applied in the vertical direction to hold the circuit board 1.
【0024】図2は、回路基板1を基板保持具に固定し
た状態の断面図である。この状態での回路基板1の半導
体素子実装領域1a内の反り量と基板保持具固定前の回
路基板1の半導体素子実装領域1a内の反り量を測定し
た結果を図3に示す。FIG. 2 is a sectional view of the circuit board 1 fixed to a board holder. FIG. 3 shows the results of measuring the amount of warp in the semiconductor element mounting region 1a of the circuit board 1 in this state and the amount of warp in the semiconductor element mounting region 1a of the circuit board 1 before fixing the substrate holder.
【0025】図3は、基板保持具固定前後の回路基板1
(厚さ0.8mm のガラスエポキシ基板)の半導体素子
実装領域1a内の反り量分布を示したもので、基板保持
具にて保持することにより、回路基板1の半導体素子実
装領域1a内の反り量が小さくなっていることを示して
いる。FIG. 3 shows the circuit board 1 before and after fixing the board holder.
The warp amount distribution in the semiconductor element mounting area 1a of (0.8 mm thick glass epoxy substrate) is shown, and the warp in the semiconductor element mounting area 1a of the circuit board 1 is held by holding the board holder. It shows that the quantity is getting smaller.
【0026】次に、基板保持具で保持した回路基板1の
半導体素子実装領域1aに、導電性接着剤を塗布した半
導体素子をフェースダウンで実装し、その後、オーブン
中130℃の温度で導電性接着剤を硬化する。図4(a)
は、基板保持具で保持した回路基板1の半導体素子実装
領域1aに半導体素子3を実装した状態の断面図で、図
4(b)は、図4(a)において回路基板1と半導体素
子3の接続箇所の一部を拡大した図である。Next, a semiconductor element coated with a conductive adhesive is mounted face down on the semiconductor element mounting area 1a of the circuit board 1 held by the board holder, and then the semiconductor element is electrically conductive at a temperature of 130 ° C. in an oven. Cure the adhesive. FIG. 4 (a)
4B is a cross-sectional view showing a state in which the semiconductor element 3 is mounted in the semiconductor element mounting region 1a of the circuit board 1 held by the board holder, and FIG. 4B is the same as the circuit board 1 and the semiconductor element 3 in FIG. It is the figure which expanded a part of connection part of.
【0027】図4(b)において、半導体素子3上のア
ルミ電極端子3aに形成されたバンプ(突起電極)4と
回路基板1上に形成された入出力電極端子1bとは導電
性接着剤5を介して接合される。ここで、基板保持具で
保持しない場合は、回路基板1の実装領域1aの表面精
度が良くないために、半導体素子3の実装時に、導電性
接着剤5が回路基板1上の入出力電極端子1bに接触し
ない箇所が発生する。In FIG. 4B, the bumps (projection electrodes) 4 formed on the aluminum electrode terminals 3a on the semiconductor element 3 and the input / output electrode terminals 1b formed on the circuit board 1 are made of a conductive adhesive 5. Are joined through. Here, when not held by the board holder, the surface accuracy of the mounting area 1a of the circuit board 1 is not good, so that the conductive adhesive 5 is applied to the input / output electrode terminals on the circuit board 1 when the semiconductor element 3 is mounted. There is a portion that does not contact 1b.
【0028】また、わずかに接触した状態では、導電性
接着剤5が硬化時の回路基板1の熱変形によって、接触
箇所が離れ、電気的接続が得られない。Further, in the state where the conductive adhesive 5 is slightly contacted, the contact portion is separated due to thermal deformation of the circuit board 1 when the conductive adhesive 5 is cured, and electrical connection cannot be obtained.
【0029】しかしながら、本実施の形態1に示す方法
にて、半導体素子を実装することにより、上記問題は解
決される。However, the above problem can be solved by mounting the semiconductor element by the method shown in the first embodiment.
【0030】次に、導電性接着剤5が硬化後の回路基板
1の半導体素子3と回路基板1表面との間に封止剤料を
注入し、オーブン中130℃の温度で封止剤料を硬化して
被覆する。Next, a sealant material is injected between the semiconductor element 3 of the circuit board 1 and the surface of the circuit board 1 after the conductive adhesive 5 is cured, and the sealant material is heated in an oven at a temperature of 130 ° C. To cure and coat.
【0031】封止剤料硬化後は、半導体素子3と回路基
板1との接着力が高くなるため、回路基板1を基板保持
具から外しても接続箇所の電気的な接続が確保される。After the encapsulant material is hardened, the adhesive force between the semiconductor element 3 and the circuit board 1 increases, so that the electrical connection at the connection point is secured even if the circuit board 1 is removed from the board holder.
【0032】本実施の形態1では、基板保持具の材質と
してSUS-304を用いたが、銅、アルミ、などの金属材料
でも良く、アルミナなどのセラミック材料でも良い。In the first embodiment, SUS-304 is used as the material of the substrate holder, but a metal material such as copper or aluminum may be used, or a ceramic material such as alumina may be used.
【0033】(実施の形態2)図5は、本発明の実施の
形態2における半導体素子実装用基板保持具で回路基板
を保持した状態を示す図で、(a)は断面図、(b)は
上面図である。(Second Embodiment) FIG. 5 is a view showing a state in which a circuit board is held by a semiconductor element mounting substrate holder according to the second embodiment of the present invention, (a) is a sectional view, and (b) is a sectional view. Is a top view.
【0034】本実施の形態2における基板保持具は、複
数個の半導体素子実装領域が形成された回路基板を平坦
に保持するためのものである。The board holder according to the second embodiment is for holding the circuit board on which a plurality of semiconductor element mounting regions are formed flat.
【0035】図5における基板保持具の基板支持台2a
は、実施の形態1と同様に回路基板1が定位置に固定し
易くするための溝(凹部)を設けた構造をしており、基
板固定蓋2bは、回路基板1に形成されている複数個の
半導体素子実装領域1aに対応して、それぞれの実装領
域1aに当たる部分に開口部を設け、さらに、回路測定
端子部にも開口部を設けた構造をしている。また、基板
支持台2a、基板固定蓋2bの外周部には、ネジ穴が設
けられている。The substrate support base 2a of the substrate holder shown in FIG.
Has a structure in which a groove (recess) for facilitating fixing of the circuit board 1 at a fixed position is provided as in the first embodiment, and the board fixing lids 2b are formed on the circuit board 1. Corresponding to each semiconductor element mounting region 1a, an opening is provided in a portion corresponding to each mounting region 1a, and an opening is also provided in the circuit measurement terminal portion. Further, screw holes are provided in the outer peripheral portions of the substrate support base 2a and the substrate fixing lid 2b.
【0036】本実施の形態2における基板保持具を用い
た回路基板1の保持方法は、実施の形態1と同様に、基
板支持台2aの中央部に設けた溝に、半導体素子実装面
を上向きにして回路基板1を置き、その上から、基板固
定蓋2bに設けた開口部が回路基板1の半導体素子実装
領域1aのそれぞれの外側を囲むように基板固定蓋2b
を置く。その後、基板支持台2a、基板固定蓋2bの外
周部に設けたネジ穴にネジ2cを差し込み、ネジ2cを
締め込むことによって、回路基板1に垂直方向に圧力を
加え、回路基板1を保持する。The method of holding the circuit board 1 using the board holder according to the second embodiment is similar to that of the first embodiment in that the semiconductor element mounting surface faces upward in the groove provided in the central portion of the board support base 2a. The circuit board 1 is placed on the board fixing lid 2b so that the openings provided in the board fixing lid 2b surround the outsides of the semiconductor element mounting regions 1a of the circuit board 1 respectively.
Put. After that, the screw 2c is inserted into the screw holes provided on the outer peripheral portions of the substrate support base 2a and the substrate fixing lid 2b, and the screw 2c is tightened to apply pressure in the vertical direction to the circuit substrate 1 to hold the circuit substrate 1. .
【0037】図6は、基板保持具固定前後の回路基板1
(厚さ0.8mm のガラスエポキシ基板)の半導体素子
実装領域1a内の反り量を視覚的に分かるように回路基
板1の半導体素子実装面を拡大した図である。図6から
明かなように、基板保持具にて保持することにより、回
路基板1の半導体素子実装領域1a内の反り量が小さく
なり、平坦化が実現されている。FIG. 6 shows the circuit board 1 before and after fixing the board holder.
FIG. 3 is an enlarged view of the semiconductor element mounting surface of the circuit board 1 so that the warp amount in the semiconductor element mounting region 1a of (0.8 mm thick glass epoxy substrate) can be visually recognized. As is clear from FIG. 6, the amount of warpage in the semiconductor element mounting region 1a of the circuit board 1 is reduced by holding the substrate by the substrate holder, and flattening is realized.
【0038】次に、基板保持具にて保持した回路基板1
の半導体素子実装領域1aに、導電性接着剤を塗布した
半導体素子をフェースダウンで実装し、その後、オーブ
ン中130℃の温度で導電性接着剤を硬化する。次に、導
電性接着剤硬化後の回路基板の半導体素子と回路基板表
面との間に封止剤を注入し、オーブン中130℃の温度で
封止剤料を硬化して被覆する。封止剤料硬化後は、半導
体素子と回路基板との接着力が高くなるため、回路基板
を基板保持具から外しても接続箇所の電気的な接続が保
持される。Next, the circuit board 1 held by the board holder.
The semiconductor element coated with the conductive adhesive is mounted face down on the semiconductor element mounting region 1a, and then the conductive adhesive is cured at a temperature of 130 ° C. in an oven. Next, a sealant is injected between the semiconductor element of the circuit board after the conductive adhesive is cured and the surface of the circuit board, and the sealant material is cured and coated at a temperature of 130 ° C. in an oven. After the encapsulant material is cured, the adhesive force between the semiconductor element and the circuit board increases, so that the electrical connection at the connection point is maintained even if the circuit board is removed from the board holder.
【0039】本実施の形態では、基板保持具の材質にア
ルミニウムを用い、表面をアルマイト処理を施し、絶縁
性をもたせて回路基板の導通検査を保持具に保持した状
態で行える構造としたが、絶縁樹脂などで被服しても良
い。In this embodiment, aluminum is used as the material of the substrate holder, and the surface is subjected to alumite treatment so that the circuit board has an insulating property and the circuit board can be inspected for continuity while being held. You may coat with insulating resin.
【0040】なお、本実施の形態では、回路基板を平坦
化するために基板支持台2a、基板固定蓋2bからなる
基板保持具を使用して、ネジを締め込むことによって回
路基板に垂直方向に圧力を加えて保持を行ったが、回路
基板を平坦化するための手段は、何等この基板保持具に
限らず、例えば、基板支持台の上に回路基板を載置した
状態で、基板支持台の下方より空気等で吸引したり、磁
気力によって回路基板の半導体素子実装領域を平坦化す
るなどの方法によるものでも良い。In this embodiment, a board holder made up of a board support base 2a and a board fixing lid 2b is used to flatten the circuit board, and the screws are tightened in the direction perpendicular to the circuit board. Although pressure was applied to hold the circuit board, the means for flattening the circuit board is not limited to this board holder, and for example, the circuit board is placed on the board support table while the circuit board is placed on the board support table. It is also possible to use a method of sucking with air or the like from below, or flattening the semiconductor element mounting region of the circuit board by magnetic force.
【0041】[0041]
【発明の効果】以上のように本発明の半導体装置の製造
方法は、回路基板と、先端に未硬化の導電性接着剤が塗
布された突起電極が電極端子上に形成された半導体素子
を予め準備する工程と、前記半導体素子を実装しようと
する前記回路基板の実装領域の面形状が、前記半導体素
子の前記電極端子形成面と略平行で、かつ平坦面となる
ように、前記回路基板を保持する工程と、前記回路基板
を保持した状態で、前記半導体素子を前記回路基板上の
前記実装領域内に設けられた入出力電極端子に、前記未
硬化の導電性接着剤によりフェースダウンで実装する工
程と、前記未硬化の導電性接着剤を硬化させる工程と、
さらに、前記半導体素子と前記回路基板間に封止材料を
充填する工程と、前記封止材料を硬化する工程を行い、
前記封止材料を硬化した後、前記回路基板の平坦化のた
めの保持を解除することを特徴とし、また、本発明の半
導体素子実装用基板保持具は、半導体素子をフェースダ
ウンで実装するための回路基板であって、前記回路基板
の前記半導体素子の実装領域面が、前記半導体素子の電
極端子形成面と略平行かつ、平坦となるように前記回路
基板を保持することを特徴とするものであり、これによ
り、回路基板の半導体実装領域面の局所的な反りやうね
りをなくすことができ、半導体素子側と回路基板側に設
けられたそれぞれの電極端子間における高さばらつきを
少なくし、半導体素子実装時の電気的接続不良をなくす
ことができる。As described above, the method of manufacturing a semiconductor device according to the present invention includes a circuit board and a semiconductor element in which a protruding electrode having an uncured conductive adhesive applied to the tip thereof is formed on an electrode terminal in advance. The step of preparing and the surface shape of the mounting region of the circuit board on which the semiconductor element is to be mounted are substantially parallel to the electrode terminal formation surface of the semiconductor element, and the circuit board is formed so as to be a flat surface. The step of holding, and the state where the circuit board is held, the semiconductor element is mounted face down on the input / output electrode terminals provided in the mounting area on the circuit board with the uncured conductive adhesive. And a step of curing the uncured conductive adhesive,
Further, a step of filling a sealing material between the semiconductor element and the circuit board, and a step of curing the sealing material,
After hardening the sealing material, the holding for flattening the circuit board is released, and the substrate holder for mounting a semiconductor element of the present invention is for mounting a semiconductor element face down. The circuit board of claim 1, wherein the circuit board is held so that a surface of the circuit board on which the semiconductor element is mounted is substantially parallel to and flat with an electrode terminal forming surface of the semiconductor element. With this, it is possible to eliminate the local warp and undulation of the semiconductor mounting region surface of the circuit board, reduce the height variation between the respective electrode terminals provided on the semiconductor element side and the circuit board side, It is possible to eliminate a defective electrical connection when mounting a semiconductor element.
【0042】また、フリップチップ実装工程における加
熱処理時に発生していた局所的な反りやうねりも、本発
明の方法により抑制される。Further, the local warpage and undulation that occur during the heat treatment in the flip chip mounting process are also suppressed by the method of the present invention.
【0043】そのため、極めて安定して電気的接続が行
えるため、生産性良く品質の高い半導体装置を作製でき
る。Therefore, electrical connection can be made extremely stably, and a semiconductor device with high productivity and high quality can be manufactured.
【図1】本発明の実施の形態1における半導体素子実装
用基板固定治具を用いた回路基板の固定方法を示す概略
図FIG. 1 is a schematic diagram showing a method of fixing a circuit board using a semiconductor element mounting board fixing jig according to a first embodiment of the present invention.
【図2】本発明の実施の形態1における回路基板を固定
治具に固定した状態の断面図FIG. 2 is a cross-sectional view showing a state in which the circuit board according to Embodiment 1 of the present invention is fixed to a fixing jig.
【図3】本発明の実施の形態1における基板保持具固定
前後の回路基板(厚さ0.8mmのガラスエポキシ基板)
の半導体素子実装領域内の反り量分布を示した図FIG. 3 is a circuit board before and after fixing the board holder according to Embodiment 1 of the present invention (a glass epoxy board having a thickness of 0.8 mm).
Figure showing the warp amount distribution in the semiconductor element mounting area of
【図4】(a)は本発明の実施の形態1における治具固
定した回路基板の半導体素子実装領域に半導体素子を実
装した状態の断面図 (b)は回路基板と半導体素子の接続箇所の一部を拡大
した図FIG. 4A is a sectional view showing a state in which a semiconductor element is mounted in a semiconductor element mounting region of a circuit board fixed by a jig according to the first embodiment of the present invention. FIG. Partly enlarged view
【図5】(a)は本発明の実施の形態2における半導体
素子実装用基板固定治具で回路基板を固定した状態の断
面図 (b)は同状態の上面図5A is a cross-sectional view of a state in which a circuit board is fixed by a semiconductor element mounting board fixing jig according to Embodiment 2 of the present invention, and FIG. 5B is a top view of the same state.
【図6】本発明の実施の形態2における基板保持具固定
前後の回路基板(厚さ0.8mmのガラスエポキシ基板)
の半導体素子実装領域1a内の反り量を視覚的に分かる
ように回路基板の半導体素子実装面を拡大した図FIG. 6 is a circuit board before and after fixing the board holder according to Embodiment 2 of the present invention (a glass epoxy board having a thickness of 0.8 mm).
FIG. 2 is an enlarged view of the semiconductor element mounting surface of the circuit board so that the amount of warp in the semiconductor element mounting area 1a can be visually recognized.
【図7】従来のフリップチップ実装技術を用いた半導体
装置の断面図FIG. 7 is a sectional view of a semiconductor device using a conventional flip chip mounting technique.
【図8】従来の半導体装置の製造方法をを示す工程図FIG. 8 is a process diagram showing a conventional method for manufacturing a semiconductor device.
【図9】従来のフリップチップ実装技術を用いた半導体
装置における回路基板の反りによる半導体素子の実装不
良を示す断面図FIG. 9 is a cross-sectional view showing a mounting failure of a semiconductor element due to a warp of a circuit board in a semiconductor device using a conventional flip chip mounting technique.
【図10】(a)は回路基板上の半導体素子実装領域に
おける反り量を表す模式図 (b)は従来基板(セラミック基板)における半導体素
子実装領域内の反り量のヒストグラムを示す図 (c)は樹脂基板(ガラスエポキシ基板)における半導
体素子実装領域内の反り量のヒストグラムを示す図10A is a schematic diagram showing the amount of warpage in a semiconductor element mounting region on a circuit board, and FIG. 10B is a diagram showing a histogram of the amount of warpage in a semiconductor device mounting region on a conventional substrate (ceramic substrate). Shows a histogram of the amount of warp in the semiconductor element mounting area on the resin substrate (glass epoxy substrate)
【図11】回路基板の反り量に対する半導体素子と回路
基板との接続不良の発生率の一例を示す図FIG. 11 is a diagram showing an example of a rate of occurrence of defective connection between a semiconductor element and a circuit board with respect to a warp amount of the circuit board.
1 回路基板 1a 半導体素子実装領域 1b 入出力端子電極 2a 基板支持台 2b 基板固定蓋 2c ネジ 3 半導体素子 3a アルミ電極端子 4 バンプ(突起電極) 5 導電性接着剤 DESCRIPTION OF SYMBOLS 1 circuit board 1a semiconductor element mounting area 1b input / output terminal electrode 2a board support 2b board fixing lid 2c screw 3 semiconductor element 3a aluminum electrode terminal 4 bump (protruding electrode) 5 conductive adhesive
───────────────────────────────────────────────────── フロントページの続き (72)発明者 別所 芳宏 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 戸村 善広 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 小野 正浩 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Bessho 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yoshihiro Tomura, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Masahiro Ono 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (11)
が塗布された突起電極が電極端子上に形成された半導体
素子を予め準備する工程と、 前記半導体素子を実装しようとする前記回路基板の実装
領域の面形状が、前記半導体素子の前記電極端子形成面
と略平行で、かつ平坦面となるように、前記回路基板を
保持する工程と、 前記回路基板を保持した状態で、 前記半導体素子を前記回路基板上の前記実装領域内に設
けられた入出力電極端子に、前記未硬化の導電性接着剤
によりフェースダウンで実装する工程と、 前記未硬化の導電性接着剤を硬化させる工程と、 さらに、前記半導体素子と前記回路基板間に封止材料を
充填する工程と、 前記封止材料を硬化する工程を行い、 前記封止材料を硬化した後、前記回路基板の平坦化のた
めの保持を解除することを特徴とする半導体装置の製造
方法。1. A step of preparing a semiconductor device in which a circuit board and a protruding electrode having an uncured conductive adhesive applied to the tip thereof are formed on electrode terminals, and a step of mounting the semiconductor device. The surface shape of the mounting area of the circuit board is substantially parallel to the electrode terminal forming surface of the semiconductor element, and a step of holding the circuit board, and in a state of holding the circuit board, A step of mounting the semiconductor element face down on the input / output electrode terminals provided in the mounting area on the circuit board with the uncured conductive adhesive; and curing the uncured conductive adhesive. And a step of filling a sealing material between the semiconductor element and the circuit board, and a step of curing the sealing material, and after the sealing material is cured, planarization of the circuit board is performed. Holding for A method for manufacturing a semiconductor device, characterized in that
記載の半導体装置の製造方法。2. The circuit board material of the circuit board is resin.
The manufacturing method of the semiconductor device described in the above.
構成される請求項1記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the circuit board is made of resin and glass.
求項1記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate material of the circuit board is ceramic.
板支持台に、前記回路基板を載置し、少なくとも前記回
路基板の実装領域分の大きさの開口部を有する基板固定
蓋を前記回路基板の前記実装領域部を塞がないようし
て、前記基板支持台と位置合わせを行って固定すること
により、前記回路基板の平坦化を保持することを特徴と
する請求項1記載の半導体装置の製造方法。5. A circuit board is mounted on a circuit board support having a recess for mounting a circuit board, and a circuit board fixing lid having an opening at least the size of a mounting area of the circuit board is provided. The semiconductor device according to claim 1, wherein the circuit board is kept flat by aligning and fixing the circuit board so that the mounting area of the circuit board is not blocked. Device manufacturing method.
めの回路基板であって、前記回路基板の前記半導体素子
の実装領域面が、前記半導体素子の電極端子形成面と略
平行かつ、平坦となるように前記回路基板を保持するた
めの半導体素子実装用基板保持具。6. A circuit board for mounting a semiconductor element face down, wherein a mounting area surface of the semiconductor element of the circuit board is substantially parallel to and flat with an electrode terminal forming surface of the semiconductor element. A substrate holder for mounting a semiconductor element for holding the circuit board.
板支持台と、少なくとも前記回路基板の実装領域分の大
きさの開口部を有する基板固定蓋とからなることを特徴
とする請求項6記載の半導体素子実装用基板保持具。7. A substrate supporting base having a recess for mounting a circuit board, and a substrate fixing lid having an opening having a size at least the mounting area of the circuit board. 6. The semiconductor element mounting substrate holder according to item 6.
属材料からなることを特徴とする請求項6または請求項
7記載の半導体素子実装用基板保持具。8. The substrate holder for mounting a semiconductor element according to claim 6 or 7, which is made of a metal material or a metal material whose surface is subjected to an insulation treatment.
り位置合わせして固定することを特徴とする請求項7記
載の半導体素子実装用基板保持具。9. The substrate holder for mounting a semiconductor element according to claim 7, wherein the substrate support base and the substrate fixing lid are aligned and fixed by screwing.
力によるものであることを特徴とする請求項6記載の半
導体素子実装用基板保持具。10. The substrate holder for mounting a semiconductor element according to claim 6, wherein the holding for flattening the circuit board is performed by a suction force.
によるものであることを特徴とする請求項6記載の半導
体素子実装用基板保持具。11. The substrate holder for mounting a semiconductor element according to claim 6, wherein the holding for flattening the circuit board is performed by magnetic force.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8014951A JP2932995B2 (en) | 1996-01-31 | 1996-01-31 | Method of manufacturing semiconductor device and substrate holder for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8014951A JP2932995B2 (en) | 1996-01-31 | 1996-01-31 | Method of manufacturing semiconductor device and substrate holder for mounting semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09213738A true JPH09213738A (en) | 1997-08-15 |
| JP2932995B2 JP2932995B2 (en) | 1999-08-09 |
Family
ID=11875291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8014951A Expired - Fee Related JP2932995B2 (en) | 1996-01-31 | 1996-01-31 | Method of manufacturing semiconductor device and substrate holder for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2932995B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010237061A (en) * | 2009-03-31 | 2010-10-21 | Tdk Corp | Substrate holder, electronic component inspection apparatus, and electronic component inspection method |
| JP2015520519A (en) * | 2012-06-05 | 2015-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Fixture for forming laminated substrates |
| EP3989275A4 (en) * | 2019-06-18 | 2022-07-13 | Fuji Corporation | PRINTED CIRCUIT BOARD FABRICATION METHOD AND PRINTED CIRCUIT BOARD FABRICATION DEVICE |
-
1996
- 1996-01-31 JP JP8014951A patent/JP2932995B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010237061A (en) * | 2009-03-31 | 2010-10-21 | Tdk Corp | Substrate holder, electronic component inspection apparatus, and electronic component inspection method |
| JP2015520519A (en) * | 2012-06-05 | 2015-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Fixture for forming laminated substrates |
| EP3989275A4 (en) * | 2019-06-18 | 2022-07-13 | Fuji Corporation | PRINTED CIRCUIT BOARD FABRICATION METHOD AND PRINTED CIRCUIT BOARD FABRICATION DEVICE |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2932995B2 (en) | 1999-08-09 |
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