JPH09213903A - Manufacture of semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the capacity of a cell. SOLUTION: A gate electrode 4 is made through a gate insulating film 3 on a semiconductor substrate 1, and with the gate electrode 4 as a mask, impurities are implanted into the substrate 1 to form source and drain diffused regions 5 and 6. Next, an NSG film 8 and a PSG film or a BPSG film 9 are stacked in order on the substrate and an interlayer insulating film 7 is made, and then the interlayer insulating film 7 is etched to form a contact hole 10 on the diffused layer 6. Subsequently, irregularity is made at the sidewall o the contact from the difference of the etching rate between the NSG film 8 and the PSG film or the BPSG film 9, by cleaning the inside of the contact hole 10, and a stacked capacitor 11 in contact with the diffused layer 6 is made through the contact hole 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a laminated capacitor of a dynamic random access memory (hereinafter referred to as DRAM).

[0002]

DR using this type of multilayer capacitor
A conventional method of manufacturing an AM memory cell is as shown in FIG. 7, in which a gate electrode 54 forming a word line formed on a semiconductor substrate 51 via a gate insulating film 53, an N + type source connected to a bit line, One diffusion layer 5 of the drain diffusion layer
5, after the transfer transistor having the other charge storage side source / drain diffusion layer 56 is formed,
The capacitor 6 is formed through the contact hole 60 formed in the interlayer insulating film 57 made of the SiO2 film on the drain diffusion layer 56.
1 is formed. That is, the polysilicon film 62 after the polysilicon film is formed by the CVD method and patterned
The silicon nitride film 63 (capacitance insulating film) is formed on the (charge storage electrode), and subsequently, the counter electrode 64 of the capacitor serving as the fixed electrode is formed by patterning the polysilicon film. Then, an interlayer insulating film 65 made of a BPSG film is formed, and the source / drain diffusion layers 5 for connecting the bit lines are formed.
After forming the contact hole 66 on the wiring 5, the bit line wiring 67 was formed.

However, with the recent increase in capacity and high integration of DRAMs, the cell area is also being reduced, and it is becoming difficult to secure the cell capacity in the above-mentioned multilayer capacitor. There is an urgent need to establish a technology to increase

[0004]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor memory device having a laminated capacitor having an increased cell capacity.

[0005]

Therefore, according to the present invention, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and impurities are injected into the substrate by using the gate electrode as a mask to form a source / drain diffusion layer. To form. Next, an NSG film, which is a non-doped silicate glass film, and a P film, which is a silicate glass film containing at least phosphorus ions, are formed on the substrate.
An SG film or a BPSG film is sequentially laminated to form an interlayer insulating film, and then the interlayer insulating film is etched to form a contact hole on the diffusion layer. Subsequently, by cleaning the inside of the contact hole, unevenness is formed on the side wall of the contact hole due to the difference in etching rate between the NSG film and the PSG film or the BPSG film, and the diffusion layer is contacted through the contact hole. Forming a polysilicon film as a charge storage electrode, forming a capacitive insulating film on the polysilicon film, forming a polysilicon film and patterning the film to form a fixed electrode.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a semiconductor memory device of the present invention will be described below with reference to the drawings of FIGS. At first, as shown in FIG.
After forming a LOCOS oxide film 2 as a device isolation film having a thickness of 0 °, a gate insulating film 3 having a thickness of approximately 150 ° is formed.
To form

Next, a polysilicon film is formed on the entire surface of the substrate 1, and the polysilicon film is patterned by a well-known patterning technique to form a word line.
To form Next, using the gate electrode 4 as a mask, impurities of the opposite conductivity type, for example, phosphorus ions (31 P +) or arsenic ions (75 As +) are implanted to connect to the bit line to be described later N + type source / drain diffusion layers. One diffusion layer 5 and the other charge accumulation side source / drain diffusion layer 6 are formed.

Further, as shown in FIG. 3, an interlayer insulating film 7 is formed on the substrate 1. In this step, first, an insulating film in which an impurity having a film thickness of about 1000 Å is not implanted on the substrate 1, a so-called non-doped silicate glass film (hereinafter,
It is called the NSG film 8. ), And about 1000
An insulating film having a thickness of Å implanted with impurities, for example, a silicate glass film containing at least phosphorus ions (31 P +) (hereinafter, referred to as a PSG film or a BPSG film 9).
By repeating this process several times.
An interlayer insulating film 7 is formed by stacking a G film 8 and a PSG film or a BPSG film 9 in any number of layers.

Next, after forming a resist film (not shown) on the interlayer insulating film 7, the interlayer insulating film 7 is etched by using the resist film as a mask to form contact holes 10 on the source / drain diffusion layers 6. To form. Then, the inside of the contact hole 10 is cleaned with a hydrofluoric acid-based etching solution. At this time, the NSG film 8 and the PSG film or B
Due to the difference in etching rate from the PSG film 9, the NSG film 8
Since the PSG or BPSG film 9 is etched more than the above, a contact hole 10A having unevenness on the side wall is formed as shown in FIG. As described above, in the present invention, the NSG film 8 and the PSG film or the BPSG film 9 are laminated to form the interlayer insulating film 7, and the contact hole 10 formed in the interlayer insulating film 7 is washed with a hydrofluoric acid-based cleaning liquid. At this time, due to the difference in etching rate between the NSG film 8 and the PSG film or the BPSG film 9, unevenness is formed on the side wall of the contact hole 10A, thereby increasing the cell capacitance of the multilayer capacitor formed in a later step. You can

Then, as shown in FIG.
The multilayer capacitor 11 is formed through the contact hole 10A on the drain diffusion layer 6. That is, first, a polysilicon film is formed by a CVD method and patterned to form a charge storage electrode 12 of a capacitor, a capacitor insulating film 13 made of a silicon nitride film is formed on the electrode 12, and then a fixed electrode is formed. The counter electrode 14 of the capacitor is formed by patterning a polysilicon film. Thereby, as shown in FIG. 5, in the multilayer capacitor 11, the cell capacitance is increased by utilizing the unevenness of the sidewall portion of the contact hole 10A formed in the above process.

Then, as shown in FIG. 6, an interlayer insulating film 15 made of a BPSG film is formed, a contact hole 16 is opened on the source / drain diffusion layer 5 connecting the bit line, and then a bit line wiring 17 is formed. Form.

[0012]

As described above, according to the present invention, when the contact hole formed in the interlayer insulating film formed by laminating insulating films having different etching rates is cleaned, the unevenness formed on the side wall of the contact hole is utilized. By doing so, the cell capacitance of the multilayer capacitor contacting the diffusion layer through the contact hole can be increased.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating a method of manufacturing a semiconductor memory device according to the present invention.
FIG.

FIG. 2 is a second diagram illustrating the method of manufacturing the semiconductor memory device according to the present invention;
FIG.

FIG. 3 is a third diagram illustrating the method for manufacturing the semiconductor memory device according to the present invention;
FIG.

FIG. 4 is a fourth view illustrating the method for manufacturing the semiconductor memory device of the present invention;
FIG.

FIG. 5 is a fifth view illustrating the method for manufacturing a semiconductor memory device of the present invention;
FIG.

FIG. 6 is a sixth view illustrating the method for manufacturing a semiconductor memory device of the present invention;
FIG.

FIG. 7 is a cross-sectional view showing a conventional semiconductor memory device.

Claims (2)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film; a step of implanting impurities on the substrate using the gate electrode as a mask to form a source / drain diffusion layer; Forming a interlayer insulating film by sequentially stacking a first insulating film not doped with impurities and a second insulating film doped with impurities on a substrate; and etching the interlayer insulating film to perform the diffusion. Forming a contact hole on the layer; cleaning the inside of the contact hole to form the first insulating film and the second insulating film;
Forming unevenness on the side wall of the contact hole due to the difference in etching rate from the insulating film, and forming a polysilicon film as a charge storage electrode that contacts the diffusion layer through the contact hole. A method of manufacturing a semiconductor memory device, comprising the steps of forming a polysilicon film after forming a capacitive insulating film thereon and patterning it to form a fixed electrode. 2. The method of manufacturing a semiconductor memory device, wherein the first insulating film is a non-doped silicate glass film and the second insulating film is a silicate glass film containing at least phosphorus ions.