JPH09213929A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, in which a T type gate electrode for preventing the separation of a gate and the increase of gate resistance is formed. SOLUTION: A columnar section 3G in the lower section of a T type gate electrode is formed of a first metal layer 3 in a recess 8 by a lift-off method using a first resist pattern on the main surface of a semiconductor substrate 1, and the section 3U of the head section of the columnar section 3G in the lower section of the T type gate electrode is exposed by etching an insulating film 4 while using a second resist pattern 5 as a mask. A second metal layer 6 is deposited at the section 3U of the exposed head section, and a T type gate electrode 10 is formed by shaping a broad width-shaped section 6G in the upper section of the T type gate electrode consisting of the second metal layer 6 by the lift-off method using the second resist pattern 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect semiconductor device.

[0002]

2. Description of the Related Art In order to improve the characteristics of a field effect transistor (hereinafter referred to as FET) using GaAs as a semiconductor material, the gate length has been shortened. Also, in order to reduce the gate resistance, using electron beam exposure technology,
So-called T-shaped gates are manufactured.

An example of the prior art of this manufacturing method will be described with reference to FIG.

First, as shown in FIG. 4A, a low sensitivity resist for electron exposure is applied on a GaAs substrate 31 to a thickness of 0.3 μm to 0.4 μm, and then a high sensitivity resist for electron exposure is applied. The thickness is, for example, 1.0 μm.

Next, a high-sensitivity resist in the upper layer is irradiated with a wide electron beam and then developed, and, for example, the dimension B is 0.7 .mu.m.
A high-sensitivity resist pattern 33 having 0.8 μm openings 33T is formed. Next, the lower-layer low-sensitivity resist is irradiated with an electron beam and then developed to form a low-sensitivity resist pattern 32 having an opening 32T having a dimension A corresponding to the gate length of, for example, 0.15 μm.

Next, using this resist pattern as a mask, the GaAs substrate 3 is formed by a phosphoric acid type etchant, for example.
1 is etched to form the recess 34.

Next, as shown in FIG. 4B, a gate electrode forming metal layer 35 is deposited. At this time, the metal layer 35 in the openings 32T and 33T has the structure of the T-type gate electrode 35G.

Next, as shown in FIG. 4C, the lift-off method is used to remove the low sensitivity resist patterns 32, 33 and the portion of the gate electrode forming metal layer 35 on the high sensitivity resist pattern 33. The remaining gate electrode forming metal film 35 forms a T-type gate electrode 35G.

[0009]

Currently, in order to improve the performance of HJFETs, the gate length is shifting from about 0.2 μm to about 0.1 μm.

Under these circumstances, if the T-shaped resist pattern is formed at one time and the T-shaped gate is formed by vapor deposition lift-off as in the above-described conventional manufacturing method, the metal growth direction during vapor deposition is Due to a problem, the junction 3 between the lower columnar portion and the upper wide portion of the gate electrode 3
6 is poor in embedding property and the upper and lower joints are poor. Therefore, problems such as peeling of the gate and deterioration of characteristics due to a large increase in gate resistance due to a decrease in gate cross-sectional area occur.

As a countermeasure against this problem, it has been considered to change the thickness of the resist or the taper angle, but it is not an effective countermeasure.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device for forming a T-type gate electrode which prevents the peeling of the gate and the increase of the gate resistance.

[0013]

A feature of the present invention is that a first resist pattern is formed on a main surface of a semiconductor substrate, and the first resist pattern is directly or indirectly used as a mask to form the semiconductor substrate. Forming a recess on the main surface of
Forming a columnar portion below the T-shaped gate electrode from the first metal layer in the recess by a lift-off method using the first resist pattern; depositing an insulating film on the entire surface; Forming a second resist pattern on the substrate, and exposing the insulating film with the second resist pattern as a mask to expose the head portion of the columnar portion under the T-shaped gate electrode. A step of depositing a second metal layer on the exposed head portion of the columnar portion, and a step of depositing a second metal layer on the upper portion of the T-shaped gate electrode made of the second metal layer by a lift-off method using the second resist pattern. And a step of forming a wide portion to form a T-type gate electrode of a field-effect semiconductor device.

Here, the first resist pattern is formed by directly depositing on the main surface of the semiconductor substrate, and the recess is formed on the main surface of the semiconductor substrate by directly using the first resist pattern as a mask. Can be formed. Alternatively, the first resist pattern is formed on the main surface of the semiconductor substrate via an insulating layer, and a pattern having an opening larger than the opening of the first resist pattern is formed by side etching using the first resist pattern. Is formed in the insulating layer, and the recess is formed in the main surface of the semiconductor substrate by using the insulating layer pattern as a mask, so that the first resist pattern is indirectly used as a mask in the semiconductor substrate. It is also possible to form a recess on the main surface.

The first resist pattern is formed by an electron beam exposure method, and the second resist pattern is formed.
The resist pattern is preferably formed by an optical exposure method.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 and 2 are cross-sectional views showing a manufacturing method according to a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, an electron exposure resist is applied to the main surface of the GaAs substrate 1 to a thickness of, for example, about 0.3 μm to 0.4 μm, and then the electron beam is applied. A first resist pattern 2 having an opening 2T having a dimension A corresponding to the gate length, for example, 0.15 μm, is formed by exposure and development processing. Since the gate length is minute and requires high precision, the electron beam exposure method is used in this way.

Then, using this first resist pattern 2 as a mask, a Ga-based etchant, such as a phosphoric acid-based etchant, is used.
The As substrate 1 is etched and the recess 8 with a width of 0.4 μm is formed.
To form

Next, as shown in FIG. 1B, for example, aluminum (Al) having a film thickness of 0.2 is formed as the first gate metal layer 3.
μm vapor deposition.

Next, as shown in FIG. 1C, the first resist pattern and the first gate metal layer 3 thereon are removed by a lift-off method, and the opening 2T of the first resist pattern 2 is removed. The first gate metal layer 3 left inside
Thus, the columnar portion 3G which is the lower portion of the T-type gate electrode and is connected to the bottom surface of the recess 8 is formed.

Next, as shown in FIG. 1D, a CVD silicon oxide film 4, for example, having a thickness of 1.0 is formed as an insulating film on the entire surface.
μm is deposited. After that, apply a resist for optical exposure,
A second resist pattern 5 having an opening 5T having a width B of 0.7 μm to 0.8 μm, which corresponds to a wide portion, that is, an eaves portion, which is an upper portion of the T-shaped gate electrode, is formed by optical exposure and development processing. This dimension B requires less precision than the dimension A that determines the gate length.
The pattern formation of the resist pattern 5 is performed by using the optical exposure method having high productivity as described above.

Next, as shown in FIG. 2A, dry etching is selectively performed with CHF ₃ gas using the second resist pattern 5 as a mask to form a recess 4T in the CVD silicon oxide film 4. Thereby, the columnar portion 3, which is the lower portion of the gate electrode, is located. That is, the head portion 3U of the columnar portion 3 is exposed.

Next, as shown in FIG. 2B, in order to form a wide portion which is an upper portion of the T-shaped gate electrode, a second portion is formed.
As the gate metal layer 6 of, for example, aluminum (Al) is vapor-deposited with a film thickness of 0.8 μm and bonded to the exposed head portion 3U of the columnar portion 3 below the gate electrode.

Next, as shown in FIG. 2C, the second resist pattern 5 and the second gate metal layer 6 on the second resist pattern 5 are removed by a lift-off method to form an opening in the first resist pattern 2. Due to the second gate metal layer 6 remaining in 2T, the wide portion 6G, which is the upper portion of the T-shaped gate electrode, is formed.
To form the T-shaped gate electrode 10 as a whole together with the columnar portion 3G.

By forming the T-type gate electrode in two steps as in this embodiment, the gate length is 0.1 μm.
Although it is as short as 0.2 μm, the problem of deterioration of the upper and lower junctions due to the problem of embedding of the joint between the lower columnar portion of the T-type gate electrode and the upper eave-shaped wide portion does not occur. No more troubles such as peeling off the gate. Furthermore, the gate resistance could be reduced to about half that of the conventional method.

Next, referring to FIGS. 3A to 3C, cross-sectional views showing a manufacturing method of a second embodiment of the present invention in the order of steps.

First, as shown in FIG. 3A, a CVD silicon oxide film 7 is formed on the GaAs substrate 1 as an insulating layer, for example.
0.5 μm is deposited. After that, the first resist pattern 2 having the opening 2T corresponding to the gate length is formed in the first resist layer as in the first embodiment. After that, the CVD silicon oxide film 7 is side-etched by wet etching using the first resist pattern 2 as a mask to form an opening 7T larger than the opening 2T. Thereafter, with the CVD silicon oxide film 7 as a mask, a recess 18 having a width of 1.0 μm is formed in the main surface portion of the GaAs substrate 1 below the opening 7T by using a phosphoric acid-based etchant. As described above, in this embodiment, the recess 18 is formed directly by the pattern of the CVD silicon oxide film 7 and indirectly by the first resist pattern 2.

Next, as shown in FIGS. 3B and 3C, a T-type gate electrode is formed in the same manner as in the first embodiment.

The wide recess 18 having such a large size
When the resist must be formed, if the resist is directly used as a mask, problems such as deformation of the resist occur. for that reason,
A recess is formed using the silicon oxide film under the resist as a mask. According to the second embodiment, a T-shaped gate electrode having a good shape can be formed even in such a case.

[0031]

As described above, according to the present invention, the lift-off gate is formed by electron beam exposure, for example.
By forming the T-type gate electrode in two steps, the problem of deterioration of the upper and lower junctions of the T-type gate electrode, which is a problem when the gate length is 0.2 μm or less, does not occur, and a problem such as peeling of the gate occurs. do not do. Further, the gate resistance could be reduced to about half that of the conventional method.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a step subsequent to FIG. 1 in order;

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device in the related art in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 First resist pattern 2T Opening of first resist pattern 3 First gate metal layer 3G Columnar part which is the lower part of the T-type gate electrode 3U Head part of the columnar part which is the lower part of the T-type gate electrode 4 CVD Silicon Oxide Film 4T Recess of CVD Silicon Oxide Film 5 Second Resist Pattern 5T Second Resist Pattern Opening 6 Second Gate Metal Layer 6G Wide Part That is the Top of T-type Gate Electrode 7 CVD Silicon Oxide Film 7T CVD Silicon oxide film opening 8,18 Recess 10 T type gate electrode 31 GaAs substrate 32 Low sensitivity resist pattern 32T Low sensitivity resist pattern opening 33 High sensitivity resist pattern 33T High sensitivity resist pattern opening 34 Recess 35 For forming gate electrode Metal layer 35G T-type gate electrode

Claims (4)

[Claims] 1. A step of forming a first resist pattern on a main surface of a semiconductor substrate, and forming a recess on the main surface of the semiconductor substrate using the first resist pattern as a mask directly or indirectly. Forming a columnar portion below the T-shaped gate electrode from the first metal layer in the recess by a lift-off method using the first resist pattern; depositing an insulating film on the entire surface; Forming a second resist pattern thereon, and exposing the head portion of the columnar portion under the T-shaped gate electrode by etching the insulating film using the second resist pattern as a mask And a step of depositing a second metal layer on the exposed head portion of the columnar portion, and a T-type formed of the second metal layer by a lift-off method using the second resist pattern. And a step of forming a wide portion above the gate electrode to form a T-type gate electrode of the field effect semiconductor device. 2. The first resist pattern is formed by directly depositing on the main surface of the semiconductor substrate, and the recess is formed in the main surface of the semiconductor substrate by directly using the first resist pattern as a mask. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed. 3. The first resist pattern is formed on the main surface of the semiconductor substrate via an insulating layer, and an opening larger than the opening of the first resist pattern is formed by side etching using the first resist pattern. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a pattern having the above is formed on the insulating layer, and the recess is formed on the main surface of the semiconductor substrate using the insulating layer pattern as a mask. 4. The semiconductor according to claim 1, wherein the first resist pattern is formed by an electron beam exposure method, and the second resist pattern is formed by an optical exposure method. Device manufacturing method.