JPH09218426A - Liquid crystal display substrate and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an opening rate and reliability. SOLUTION: A thin-film transistor(TFT) is constituted by forming its semiconductor layer of amorphous Si and forming a drain electrode 3A and a source electrode 3B consisting of aluminum in the state of not forming a contact layer doped with an impurity. A light shielding layer 5 is formed via insulating film on the lower layer of a drain signal line 3 along the drain signal line 3 so as to be separated from the gate signal line. The source electrode 3B of this TFT is connected to a pixel electrode 4 via a connecting layer 6 partly exposed in the aperture of a protective film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display substrate and a manufacturing method thereof, and more particularly to an active matrix type liquid crystal display substrate and a manufacturing method thereof.

[0002]

2. Description of the Related Art Active matrix type liquid crystal substrates are
It is known that a thin film transistor as a switching element is provided in each pixel region arranged in a matrix.

That is, a thin film transistor which is turned on by a scanning signal supplied to a gate signal line is provided in each pixel region on the liquid crystal side surface of one transparent substrate of the transparent substrates arranged to face each other with the liquid crystal interposed therebetween. Pixel electrodes and the like to which a pixel signal supplied from the drain signal line is applied via the turned-on thin film transistor are formed.

Further, on the liquid crystal side surface of the other transparent substrate,
A common electrode common to each pixel region and a light-shielding film that surrounds the periphery of each pixel region are formed in order to improve the contrast.

As a liquid crystal display substrate having such a structure, for example, Japanese Patent Laid-Open No. 63-309921 or "12.5 type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics, pages 193-210. , December 15, 1986, published by Nikkei McGraw-Hill Inc., etc.

[0006]

Since the liquid crystal display substrate having such a structure has the complicated and fine structure as described above, the number of manufacturing steps can be reduced,
In addition, an attempt has been made to provide a highly reliable structure, and at the same time, attempts have always been made to improve the aperture ratio in each pixel region.

For example, in a thin film transistor, while using amorphous Si as its semiconductor layer,
In particular, a technique in which a contact layer is not provided (Japanese Patent Laid-Open No. 60-49669), and a technique in which a light-shielding film is provided on the transparent substrate side where a thin film transistor is formed (Japanese Patent Laid-Open No. 61-235820). Issue) has been known.

[0008] Here, if these techniques are not applied individually but are configured to be combined with each other, the basic background configurations are completely different, which leads to an increase in manufacturing man-hours. It has been pointed out that there is an adverse effect or a shortcoming between signal lines, resulting in lack of reliability.

The present invention was devised based on such circumstances.

[0010] Its main purpose is to provide a liquid crystal display substrate having an improved aperture ratio.

Another object of the present invention is to provide a liquid crystal display substrate free from the risk of short circuit between signal lines.

Still another object is to provide a method for manufacturing a liquid crystal display substrate which can be constructed by reducing the number of manufacturing steps.

[0013]

Means for Solving the Problems A typical one of the inventions disclosed in the present application is constituted as follows.

That is, a thin film transistor which is turned on by a scanning signal supplied to a gate signal line is provided in each pixel region on the liquid crystal side surface of one of the transparent substrates arranged to face each other with the liquid crystal interposed therebetween. In the liquid crystal display substrate in which the pixel electrode to which the pixel signal supplied from the drain signal line is applied via the turned on thin film transistor is formed, the thin film transistor is made of amorphous Si as its semiconductor layer and is doped with impurities. A drain electrode and a source electrode made of aluminum are formed without forming a contact layer, and a light-shielding layer is provided below the drain signal line via an insulating film along the drain signal line, and a gate signal line. The source electrode of the thin film transistor is formed as a protective film while being formed separately. Through the connection layer part is exposed to the opening, characterized in that it is connected to the pixel electrode.

The liquid crystal display substrate thus configured can form a thin film transistor with a small number of manufacturing steps, which inevitably causes a defective contact between the source electrode (including the drain electrode) whose material is selected and the pixel electrode. Is solved by interposing a connection layer.

By interposing this connection layer, it is not necessary to form a contact hole, and the aperture ratio is improved.

Further, as will be described later, in order to form each constituent element in the same process as much as possible, by selecting the materials thereof, a liquid crystal display substrate can be manufactured without increasing the manufacturing process. Has become.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, FIG. 2 is a plan view showing the structure of one of the transparent substrates which face each other with a liquid crystal in between, which is located on the liquid crystal side.

In FIG. 1, there is a transparent substrate 1, and a gate signal line 2 is formed on the liquid crystal side surface of the transparent substrate 1 so as to extend in the x direction and be arranged in parallel in the y direction. The drain signal line 3 is formed so as to be insulated from the gate signal lines 2 and extend in the y direction and be arranged in parallel in the x direction.

Unit pixel regions (regions surrounded by dotted line A in the figure) are formed in a rectangular region surrounded by each gate signal line 2 and drain signal line 3, and these unit pixel regions are arranged in a matrix. The display section (the area surrounded by the dotted line B in the figure) is formed by the.

In each unit pixel region, a transparent pixel electrode occupying most of the unit pixel region is formed, a thin film transistor is formed adjacent to one gate signal line, and is further adjacent to the other gate signal line. Stray capacitance is formed. That is, an equivalent circuit in each unit pixel area is shown in FIG. 3, and the thin film transistor TFT is turned on by the scanning signal (voltage) supplied through the gate signal line 2, and the thin film transistor TFT is turned on via the turned on thin film transistor TFT. The pixel signal (voltage) supplied from the drain signal line 3 is applied to the pixel electrode 4. The stray capacitance Cadd is provided to store the pixel signal for a long time when the thin film transistor TFT is turned off.
The detailed configurations of the pixel electrode 4, the thin film transistor TFT, and the floating capacitance Cadd will be described later.

Then, as shown in FIG. 2, on the outer periphery of the transparent substrate 1 corresponding to the outer periphery of the display portion, the gate electrode terminal 2T constituted by the extended portion of the gate signal line 2 and the drain signal line 3 are formed. A drain electrode terminal 3T composed of the extending portion is provided.

Another transparent substrate (not shown) is arranged in the display section through the liquid crystal, and a common electrode common to each unit pixel area, a color filter, etc. are provided on the liquid crystal side surface of the transparent substrate. Has been formed. The liquid crystal is sealed between the transparent substrates by a sealing material formed on the dotted line (dotted line B) in the figure.

FIG. 4 is a plan view showing a detailed structure of the unit pixel area, and shows a view corresponding to the area A in FIG. In addition, in FIG. 4, a cross-sectional view taken along the line I-I is shown in FIG. 1, and a cross-sectional view taken along the line V-V is shown in FIG.

First, a gate signal line 2 extending in the x direction and a light shielding layer 5 extending in the y direction are formed on the main surface of the transparent substrate 1. The light-shielding layer 5 has the gate signal line 2 at a portion where a drain signal line, which will be described later, is formed.
Are separated from each other (thus not connected to the gate signal line 2). Therefore, the gate signal 2 and the light shielding layer 5 are formed so as to surround one unit pixel region.

By forming the light-shielding layer 5, it is not necessary to form a light-shielding layer, which has been provided on the other transparent substrate side, so that the alignment margin of the other transparent substrate with respect to the transparent substrate 1 can be reduced. It is not necessary to consider the above, and the effect is that the aperture ratio can be substantially improved.

The gate signal line 2 on one side (upper side in the drawing) is integrally formed with an extending portion 2A extending to the pixel region side, and this extending portion 2A is of a thin film transistor TFT described in detail later. It is adapted to form a gate electrode.

In this thin film transistor TFT, its drain electrode 3A is formed integrally with the drain signal line 3.
Then, the source electrode 3B comes to be connected to the pixel electrode 4 which will be described in detail later, but in the connection between the source electrode 3B and the pixel electrode 4, a connection layer 6 is formed on the surface of the transparent substrate 1 as much as an intervening layer.

Further, the gate signal line 2 on the other side (lower side in the drawing) also extends to the pixel region side.
B is integrally formed, and the extending portion 2B constitutes one electrode of a stray capacitance Cadd described in detail later.

The gate signal line 2 (including the extending portions 2A and 2B), the light-shielding layer 5, and the connection layer 6 which have been described so far.
Are formed of chromium (Cr), and are simultaneously formed in the same photomask process. In this case, in this embodiment, in order to bring out the effects described later, the thickness of the chrome layer is particularly set to 60 nm or less. As a result, the gate signal line 2 made of the chrome layer is not formed as a signal line having a sufficiently low resistance, but its adverse effect is caused by partially laminating a low resistance layer (see FIG. 5) described later. I am trying to remove.

The gate signal lines 2 (including the extending portions 2A and 2B), the light shielding layer 5 and the connection layer 6 which are formed at the same time are not necessarily limited to chromium, and may be molybdenum (Mo). ), Tungsten (W), or titanium (Ti).

Then, the transparent substrate 1 processed in this way
A silicon nitride film 7A having a predetermined pattern is sequentially formed on the surface of the
(Thickness 300 nm) and amorphous Si7B (thickness 10
0 nm) is formed.

The laminated body 7 is formed along the formation region of the drain signal line 3 which will be described later, covering the light shielding layer 5.
Moreover, a part thereof is formed with the extending portion 7A extending to the formation region of the thin film transistor TFT.

This laminated body 7 is a thin film transistor TFT.
In the formation region of the gate oxide film and the semiconductor layer, at the intersection of the gate signal line 2 and the drain signal line 3 described later, as the interlayer insulating film, and the region that covers the light shielding layer 5. Has a function of reducing the capacitance with the liquid crystal.

Silicon nitride film 7A and amorphous Si7
The stacked body 7 formed by sequentially stacking B and B is continuously formed by the same vapor deposition apparatus and simultaneously formed by the same photomask process. As the selective etching in this case, plasma etching using SF ₆ gas is suitable.

Then, the transparent substrate 1 processed in this way
A drain signal line 3 is formed on the surface of the. A part of the drain signal line 3 is a thin film transistor TF.
The drain electrode 3A extending in the formation region of T (on the stacked body 7) is integrally formed. At the same time, the source electrode 3B of the thin film transistor TFT is also formed, and the source electrode 3B is connected to a part of the connection layer 6 exposed from the laminated body 7 by grooving the step portion of the laminated body 7. It is supposed to be done.

In the thin film transistor TFT in this case, a so-called contact layer doped with, for example, an n-type high-concentration impurity is not formed in the amorphous Si, and the materials of the drain electrode 3A and the source electrode 3B are used as described later. By making aluminum
This is because an alloy layer containing aluminum as a main component is formed, and this alloy layer has a function as a contact layer. Therefore, the effect of reducing the step of doping the impurities to form the contact layer is obtained.

Further, at the same time when the drain signal line 3 is formed, the low resistance layer 8 is formed so as to be laminated on the portion of the gate signal line 2 which is exposed from the laminated body 7. It is configured to reduce the resistance value of the line 2.

As a result, the gate signal line 2 has its own layer thickness (60 nm) at the intersection with the drain signal line 3.
The following), and the low resistance layer 8 is provided in the other portions.
The gate signal line 2 has a structure in which the resistance is reduced as a whole by increasing the layer thickness.

The above structure is provided to prevent the occurrence of a short circuit between the gate signal line 2 and the drain signal line intersecting with the silicon nitride film 7A, and the reason will be described later.

The drain signal line 2 (including the drain electrode 2A), the source electrode 2B, and the low resistance layer 8 described above are all formed of aluminum (Al) and are simultaneously formed in the same photomask process. To be formed.

Then, the transparent substrate 1 processed in this way
A protective film 1 made of, for example, a silicon nitride film is formed on the surface of the
0 is formed. The protective film 10 has an opening provided in a portion of the pixel region other than the region where the thin film transistor TFT is formed. The main function of the protective film 10 is to prevent the characteristics of the thin film transistor TFT from being deteriorated due to direct contact with the liquid crystal.

The opening of the protective film in this case is formed by a photomask process, and one end of the connection layer 6 (the end opposite to the connection with the source electrode 3B) is opened from the opening. It is necessary to form it so that it is sufficiently exposed. This exposed portion becomes a portion for contact with the pixel electrode 4 formed in the next step.

Further, the transparent substrate 1 processed in this way
A pixel electrode 4 made of, for example, an ITO (Indium-Tin-Oxide) film is formed on the surface of the. This pixel electrode 4
Are formed in the opening of the protective film 10 and extend to the upper surface of the protective film 10 at the periphery thereof.

With the formation of the pixel electrode 4, the pixel electrode 4 is inevitably connected to the connection layer 6, and thus the source electrode 3B of the thin film transistor TFT is connected via the connection layer 6. Will be connected with.

From this, the connection with the source electrode 3B can be achieved without forming a contact hole in the protective film 10, so that the region for forming the contact hole can be eliminated.
The aperture ratio can be improved.

In the liquid crystal display substrate thus constructed, as shown in the cross-sectional view of the thin film transistor TFT in FIG. 1, impurities (so-called contact layer) (so-called contact layer) are formed on the surface of the amorphous Si7B serving as a semiconductor layer. For example, it has a structure in which a layer doped with high concentration n is an impurity is not formed.

This is a structure in which the contact layer need not be formed by using aluminum for the drain electrode 3A and the source electrode 3B and forming amorphous Si7B under certain conditions.
This is because aluminum diffuses along the voids and grain boundaries in amorphous Si7B to form an alloy layer containing aluminum as a main component, and the alloy layer exhibits metallic conductivity, whereby the energy barrier can be reduced.

In this case, amorphous-Si
In order to avoid characteristic distortion caused by the energy barrier when a thin film transistor is operated, the localized level is located in the middle of the energy barrier during charge injection from aluminum. Will be able to.

Therefore, the amorphous Si is 60 n / min.
When it is formed at a high speed of m or more, a film having many crystal defects, that is, having many shallow localized levels can be obtained. 1 per 1 cm ^{3 at} a position of about 1.5 to 1.4 eV from the valence band
If amorphous Si having a level of 0 to the 17th power is used, distortion of transistor characteristics due to this energy barrier will be improved.

When diffusing aluminum into amorphous Si, the surface of the amorphous Si is
It is suitable to remove the oxide film by 2% hydrofluoric acid treatment, plasma etching of fluorine-based gas, argon plasma sputtering, or the like.

FIG. 6 shows the characteristics of the thin film transistor TFT thus obtained and the characteristics of amorphous Si formed under the low-speed film formation condition in which the localized level density is low.
It can be seen that there is some distortion in the Vg-Id characteristic, but it is in a range where there is no practical problem.

As a result of disassembling and examining this transistor, aluminum was detected from the amorphous silicon portion covered with aluminum by Auger spectroscopy. The passivation film formation temperature is 2
Since the temperature is 00 ° C. and the transparent substrate is heated for about 10 minutes including preheating, it is considered that aluminum diffused into the amorphous Si during that time.

As is clear from FIG. 1, the source electrode 3B of the thin film transistor TFT extends so as to extend over the step of the laminated body 7 and is formed on the connection layer 6 formed outside the laminated body 7. Once connected, the connection layer 6 is configured to be connected to the pixel electrode 4 extending through the protective film 10 and up to the upper surface of the protective film 10. That is, the source electrode 3B made of aluminum is ITO
The structure is such that the direct connection with the pixel electrode 4 made of is avoided and the connection is made via the connection layer 6 made of chromium.

The direct connection between aluminum and ITO is based on the fact that an oxide film is likely to be formed at the interface, so that the source electrode 3 is formed by interposing the connection layer 6.
This is intended to ensure good contact between B and the pixel electrode 4.

In this case, the connection between the connection layer 6 and the pixel electrode 4 is formed so that the connection layer 6 protrudes from the protective film, and the pixel electrode 4 is formed in this protruding portion. By the protective film 1
0, especially avoiding the configuration of forming a contact hole,
The contact hole prevents the increase in aperture ratio from being hindered.

Further, the gate signal line 2 has a structure in which a low resistance layer 8 made of aluminum is formed except for a portion intersecting with the drain signal line 3, as shown in FIG. 5 which is a sectional view thereof. .

Therefore, it is possible to prevent the gate signal line 2 from being a high-resistance signal line as a whole and to prevent a short circuit with the drain signal line 3 intersecting with the silicon nitride film 7A in advance. Become.

That is, if the gate signal line 2 is itself formed as a low resistance signal line by increasing its layer thickness, the silicon nitride film 7A at the intersection with the drain signal line 3 is formed.
Voids are likely to be generated therein, and aluminum that constitutes the drain signal line 3 is easily diffused, so that a short circuit with the gate signal line 2 occurs.

In this case, as one of the solutions, it was found that the layer thickness of the gate signal line 2 should be, for example, 60 nm or less, and the gate signal line 2 is formed to have the above-mentioned layer thickness at the intersection. However, the adverse effect of increasing the resistance is eliminated by stacking the low resistance layer 8 made of aluminum in a portion other than the intersection.

Further, in spite of each of the above-mentioned effects, the photomask process is carried out five times, so that there is a great effect that the manufacturing can be completed without increasing the manufacturing process. Like

[0062]

As is apparent from the above description,
According to the liquid crystal display substrate of the present invention, the aperture ratio can be improved. In addition, it is possible to obtain a device that is not likely to cause a short circuit between signal lines.

Further, according to the method of manufacturing a liquid crystal display substrate of the present invention, the above-mentioned effects can be achieved without increasing the manufacturing man-hour.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a liquid crystal display substrate according to the present invention.

FIG. 2 is a schematic plan view showing an embodiment of a configuration on a liquid crystal side surface of one glass substrate of the liquid crystal display substrate according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of an equivalent circuit per unit pixel of the liquid crystal display substrate according to the present invention.

FIG. 4 is a plan view showing an example of a configuration per unit pixel of the liquid crystal display substrate according to the present invention.

FIG. 5 is a sectional view taken along line VV in FIG. 4;

FIG. 6 is a diagram showing characteristics of a thin film transistor incorporated in a liquid crystal display substrate according to the present invention.

[Explanation of symbols]

2 ... Gate signal line, 3 ... Drain signal line, 3A ...
Drain electrode, 3B ... source electrode, 4 ... pixel electrode,
5 ... Shading film, 6 ... Connection layer, 7A ... Silicon nitride film, 7B ... Amorphous Si, 8 ... Low resistance layer.

Claims (9)

[Claims] 1. A thin film transistor, which is turned on by a scanning signal supplied to a gate signal line, in each pixel region of a liquid crystal side surface of one of the transparent substrates arranged to face each other with a liquid crystal interposed therebetween, In a liquid crystal display substrate on which a pixel electrode to which a pixel signal supplied from a drain signal line is applied via the turned on thin film transistor is formed, the thin film transistor is made of amorphous Si as its semiconductor layer and is doped with impurities. A drain electrode and a source electrode made of aluminum are formed without forming a contact layer, and a light-shielding layer is provided below the drain signal line with an insulating film interposed between the drain signal line and the gate signal line. The source electrode of the thin film transistor, which is formed separately, has an opening of a protective film. A liquid crystal display substrate, characterized in that the liquid crystal display substrate is connected to the pixel electrode through a connection layer exposed partially. 2. The method of manufacturing a liquid crystal display substrate according to claim 1, wherein the gate signal line, the light shielding layer, and the connection layer are formed of the same material and are formed in the same step. 3. The method for manufacturing a liquid crystal display substrate according to claim 2, wherein the gate signal line, the light shielding layer, and the connection layer are made of a refractory metal material. 4. A refractory metal material such as Cr, Mo, W,
And any one of Ti and Ti, or an alloy thereof, and a method for manufacturing a liquid crystal display substrate. 5. The method of manufacturing a liquid crystal display substrate according to claim 1, wherein the drain signal line is made of aluminum and is formed in the same step as the drain electrode and the source electrode of the thin film transistor. 6. The method for manufacturing a liquid crystal display substrate according to claim 1, wherein the source electrode is connected to the connection layer by forming the source electrode. 7. The liquid crystal display substrate according to claim 1, wherein the gate signal line has a low resistance layer laminated except for a portion intersecting with the drain line via an insulating film. 8. The liquid crystal display substrate according to claim 7, wherein the low resistance layer is formed of aluminum. 9. The method of manufacturing a liquid crystal display substrate according to claim 8, wherein the low resistance layer is formed in the same process as the drain signal line made of aluminum.