JPH09223393A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] (Correction) [Problem] Synchronous D having latency mode
The clock access time in the read mode in which the CAS latency of the RAM or the like is 3 is accelerated, and the upper limit frequency of the operation clock signal is increased. SOLUTION: The output latch of the first stage is made to perform a through operation in the first latency mode to be latched in the second and third latency modes, and the output latch of the second stage is made to operate in the first and second latency modes. Third through the through operation in the mode
Latch operation in the latency mode of the inverter V
9 and output latch control signal generation circuits OG20 to OG23, and second internal clock signals OK20 to OK20 supplied to the output latches of the second stage by the clock signal CLK from the outside.
A first internal clock signal OK10 including the generation path of OK23, the inverter V8, and the output latch control signal generation circuits OG11 to OG13 and being supplied to the output latch of the first stage.
˜OK13 generation pathway is provided independently from the initial stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, for example, to a synchronous DRAM (dynamic random access memory) having a latency mode and a technique which is particularly effective for use in increasing the speed thereof.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM which operates synchronously according to a predetermined clock signal. In the synchronous DRAM, when the read (read) command is input, the time from when the column address strobe signal is set to the effective level to when the first read data is output is selected, for example, for 1 to 3 cycles of the clock signal. Many have a so-called latency mode that can be delayed.

[0003]

Prior to the present invention, the inventors of the present invention developed a synchronous DRAM having a latency mode and provided a data input / output circuit with an output latch having a two-stage structure. A method is used in which the number of delay cycles in the latency mode is selectively switched by selectively switching the operation mode. Among them, the output latch of the first stage is the output latch control signal generation circuit OG10 corresponding to the timing generation circuit TG of FIG.
~ Output latch control signal OK10 output from OG13
When ~ OK13 is set to the high level, the through operation is selectively performed, and when it is set to the low level, the latch operation is performed. The output latch of the second stage is the output latch control signal generation circuit OG corresponding to the timing generation circuit TG.
20 to OG23 output latch control signal OK
When 20 to OK23 are set to the high level, the through operation is selectively performed, and when they are set to the low level, the latch operation is performed.

On the other hand, in the latency mode of the synchronous DRAM, for example, the number of delay cycles from the input of a read command to the output of read data is specified as so-called CAS latency, and its value is
For example, it is selectively set to 1 to 3 according to the frequency of the clock signal. Among them, in the latency 3 corresponding to the case where the frequency of the clock signal is the highest, as illustrated in FIG. 9, the output latch control signals OK10 and OK2 are generated.
0 and the like are repeatedly set to the high level in accordance with the clock signal CLK, and in response to this, the output latches of the first stage and the second stage are alternately passed or latched. Further, after the clock signal CLK is set to the high level, the data input / output terminal D
The time until the logic level of the read data (a) or the like is fixed to 0, that is, the clock access time tac is
Output latch control signal O supplied to the output latch of the second stage
It depends on the rise of K20.

Synchronous DR developed by the present inventors
In the AM, the output latch control signal OK20 and the like supplied to the output latch of the second stage are the output latch control signal generation circuits OG20 to OG20 of the timing generation circuit TG as described above.
The clock signal CLK generated by the OG 23 is supplied to these output latch control signal generation circuits from the clock buffer CLKB via the common inverters VJ and VG. In other words, the output terminal of the inverter VK has output latch control signal generation circuits OG10 to OG1.
3, a relatively large load corresponding to the input capacitances of OG20 to OG23 and other circuits (not shown) is coupled, and the level change of the output signal VKout thereof is gentle as shown in FIG. Becomes As a result,
Correspondingly, the clock access time tac of the synchronous DRAM is delayed, and in some cases, the clock signal CL
The read data cannot be taken in at the next rising edge of K, which restricts the speedup of the synchronous DRAM.

An object of the present invention is to speed up the clock access time in a read mode with a CAS latency of 3 such as a synchronous DRAM having a latency mode and increase the operable clock frequency.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for example, in a synchronous DRAM or the like having the first to third latency modes and having a two-stage output latch, the first-stage output latch is made to perform the through operation in the first latency mode to perform the second and Latch operation is performed in the third latency mode, the output latch of the second stage is slewed in the first and second latency modes to perform latch operation in the third latency mode, and a clock signal supplied from the outside is supplied. A generation path of the second internal clock signal that is received and supplied to the output latch of the final stage, that is, the second stage, and a first internal clock that receives the clock signal and is supplied to the output latch of the preceding stage, that is, the first stage The signal generation path and the signal generation path are provided separately from the initial stage.

According to the above means, the influence of the load capacitance coupled to the generation path of the first internal clock signal on the generation path of the second internal clock signal is eliminated, and the second capacitance with respect to the rising edge of the clock signal is eliminated. The delay time of the rising edge of the internal clock signal can be shortened. As a result, it is possible to speed up the clock access time in the read mode in which the CAS latency is 3 such as the synchronous DRAM and increase the upper limit frequency of the operable clock signal.

[0010]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM (semiconductor device) to which the present invention is applied. First, an outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification,
It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique of an integrated circuit, which is a generic name of an insulated gate field effect transistor by referring to a MOSFET.

In FIG. 1, the synchronous DRAM of this embodiment comprises a pair of banks BNK0 and BNK1.
Each of these banks includes a memory array MARY arranged to occupy most of its layout area, a row address decoder RD serving as a direct peripheral circuit, a sense amplifier SA and a column address decoder CD, a write amplifier and a read amplifier, respectively. And a main amplifier MA including.

The memory array MARY forming the banks BNK0 and BNK1 has a predetermined number of word lines arranged in parallel in the vertical direction and a predetermined set of complementary bit lines arranged in parallel in the horizontal direction. Include each. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

The word lines constituting the memory array MARY of the banks BNK0 and BNK1 are coupled to the corresponding row address decoder RD, and each of them is alternatively selected. To these row address decoders RD, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the row address buffer RB, and an internal control signal RG is commonly supplied from the timing generation circuit TG. Supplied. The row address buffer RB is supplied with the X address signals AX0 to AXi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal RL.

The row address buffer RB has an X address signal A input through address input terminals A0 to Ai.
X0 to AXi are fetched and held according to internal control signal RL, and internal address signals X0 to Xi are formed based on these X address signals. Of these, the internal address signal Xi of the most significant bit is the bank selection circuit BS.
And other internal address signals X0 to Xi-1
Are commonly supplied to the row address decoders RD of the banks BNK0 and BNK1.

The bank selection circuit BS decodes the internal address signal Xi of the most significant bit supplied from the row address buffer RB and outputs the corresponding bank selection signal BS0.
Alternatively, BS1 is selectively set to the high level. These bank selection signals BS0 and BS1 correspond to the corresponding bank BNK.
0 and BNK1, respectively, which are peripheral circuits such as a row address decoder RD and a column address decoder C.
It is provided for selectively operating the D, the sense amplifier SA and the main amplifier MA.

The row address decoders RD of the banks BNK0 and BNK1 are selectively activated by setting the internal control signal RG to the high level and the corresponding bank selection signal BS0 or BS1 to the high level. The internal address signals X0 to Xi-1 supplied from the address buffer RB are decoded to selectively set the designated word line of the corresponding memory array MARY.

Next, the complementary bit lines constituting the memory array MARY of the banks BNK0 and BNK1 are coupled to the corresponding sense amplifier SA. A bit line selection signal of a predetermined bit is supplied from the corresponding column address decoder CD to each of these sense amplifiers SA, and an internal control signal PA is commonly supplied from the timing generation circuit TG. In addition, the column address decoders CB to i + are added to the column address decoder CD of each bank.
1-bit internal address signals Y0 to Yi are commonly supplied, and an internal control signal CG (not shown) is commonly supplied from the timing generation circuit TG. Further, the column address buffer CB has address input terminals A0 to A0.
The Y address signals AY0 to AYi are time-divisionally supplied via Ai, and the internal control signal CL is supplied from the timing generation circuit TG.

The column address buffer CB fetches the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal CL,
The bank BNK0 holds the internal address signals Y0 to Yi based on these Y address signals.
And BNK1 column address decoder CD. The column address decoder CD of each bank is
When the internal control signal CG is set to the high level and the corresponding bank selection signal BS0 or BS1 is set to the high level, the internal address signals Y0 to Y are selectively activated.
i is decoded and the corresponding bit line selection signal is alternatively set to the high level.

On the other hand, the sense amplifiers SA of the banks BNK0 and BNK1 include a predetermined number of unit circuits provided corresponding to the complementary bit lines of each memory array MARY, and each of these unit circuits has a pair of CMOS inverters. And a pair of N-channel type switch MOSFETs. Among these, the unit amplifier circuit of each unit circuit has the internal control signal PA at the high level and the corresponding bank selection signal BS0 or BS.
When 1 is set to the high level, they are selectively and simultaneously activated, and output from a predetermined number of memory cells coupled to the selected word line of the corresponding memory array MARY via the corresponding complementary bit lines. The minute read signals thus generated are each amplified to be a high-level or low-level binary read signal. In addition, the switch MOS of each unit circuit
Upon receiving the high level of the corresponding bit line selection signal, the FETs are selectively turned on by 16 pairs, and the 16 pairs of corresponding complementary bit lines and complementary common data lines CD0 * to CDF * (here: , Complementary signal lines consisting of non-inverted and inverted signals have * at the end of their names.
It is indicated by adding. In addition, the serial numbers of signal lines and elements whose number exceeds 10 are represented by alphabets. The same applies to the following).

The complementary common data lines CD0 * to CDF * are
Coupled to corresponding main amplifier MA. These main amplifiers MA have complementary common data lines CD0 * to CDF *.
16 write amplifiers and 16 read amplifiers are provided corresponding to the above. Of these, the input terminals of each write amplifier are connected to the corresponding internal data buses DBUS0 to DBU.
It is coupled to SF and its output terminal is coupled to corresponding complementary common data lines CD0 * to CDF *. The input terminal of each read amplifier has a corresponding complementary common data line CD
0 * to CDF *, and their output terminals are connected to corresponding internal data buses DBUS0 to DBUSF.
The internal control signals RP and WP are commonly supplied to each main amplifier MA from the timing generation circuit TG.

Internal data buses DBUS0 to DBUSF
Are coupled to the output terminals of the corresponding input latches of the data input / output circuit IO and to the input terminals of the corresponding first stage output latches OL10 to OL1F. here,
As will be described later, the data input / output circuit IO includes 16 data input buffers and 16 input latches provided corresponding to the internal data buses DBUS0 to DBUSF, first stage output latches OL10 to OL1F, and second stage output latches. OL20 to OL2F and data output buffer DOB
0 to DOBF are included. Of these, the input terminals of each data input buffer are the corresponding data input / output terminals D0 to DF.
, Whose output terminal is coupled to the input terminal of the corresponding input latch. The output terminals of these input latches are respectively coupled to the corresponding internal data buses DBUS0 to DBUSF.

On the other hand, the first stage output latches OL10 to OL1.
The input terminals of F are corresponding internal data buses DBUS0 to DBUS0.
Coupled to DBUSF, the output terminal of which is the corresponding second
It is coupled to the input terminals of the stage output latches OL20-OL2F. The output terminals of the second stage output latches OL20 to OL2F are coupled to the input terminals of the corresponding data output buffer OB, and the output terminals of these data output buffers are coupled to the corresponding data input / output terminals D0 to DF, respectively. . The data input / output circuit IO includes a timing generation circuit T
An input latch control signal IK (not shown) is supplied from G, and output latch control signals OK10 to OK13 are supplied.
(First internal clock signal), OK20 to OK23 (second internal clock signal), and output control signal DOC0
~ DOC3 is supplied. These output latch control signals and output control signals are output to the first stage output latches OL10 to OL.
1F, 2nd stage output latches OL20 to OL2F and 4 data output buffers DOB0 to DOBF, respectively.

Each data input buffer of the data input / output circuit IO receives 16-bit write data input via the data input / output terminals D0-DF to the corresponding input latch when the synchronous DRAM is set in the write mode. Each input latch receives and holds the write data transmitted from the corresponding data input buffer in accordance with the input latch control signal IK, and holds the write data via the internal data buses DBUS0 to DBUSF and the corresponding write amplifier of the main amplifier MA. Communicate to. At this time, the 16 write amplifiers forming each main amplifier MA are
When the internal control signal WP is set to the high level and the corresponding bank selection signal BS0 or BS1 is set to the high level, the respective blocks are selectively and simultaneously activated, and the internal data is input from the corresponding input latch of the data input / output circuit IO. After converting the write data transmitted via the data buses DBUS0 to DBUSF into predetermined complementary write signals, the selected 16 memories of the corresponding memory array MARY via the complementary common data lines CD0 * to CDF *. Write in a cell.

The 16 read amplifiers constituting the main amplifiers MA of the banks BNK0 and BNK1 are selectively selected by setting the internal control signal RP to the high level and the corresponding bank selection signal BS0 or BS1 to the high level. Read signals output from the 16 selected memory cells of the corresponding memory array MARY through the complementary common data lines CD0 * to CDF * are amplified to generate an internal data bus. DBU
Output to S0 to DBUSF.

At this time, the first-stage output latches OL10-OL1F of the data input / output circuit IO are selectively brought into the through state when the corresponding output latch control signals OK10-OK13 are set to the high level, and these outputs are also output. When the latch control signal is set to the low level, the latch state is selectively brought into the latch state, and the read amplifier corresponding to the main amplifier MA of the bank BNK0 or BNK1 changes from the internal data bus DB.
The read data supplied via US0 to DBUSF are transmitted to the corresponding second stage output latches OL20 to OL2F. Similarly, the second-stage output latches OL20 to OL2F of the data input / output circuit IO are selectively brought into the through state when the corresponding output latch control signals OK20 to OK23 are set to the high level, and these output latch control signals Is set to the low level to selectively enter the latch state, and the corresponding first stage output latches OL10 to OL
The read data transmitted from 1F is transmitted to the corresponding data output buffers DOB0-DOBF. Further, the data output buffers DOB0 to DOBF receive the high level of the corresponding output control signals DOC0 to DOC3 to be selectively activated, and read the read data transmitted from the corresponding second stage output latches OL20 to OL2F. Synchronous DR via input / output terminals D0-DF
Output to the access device of AM. The specific configuration and operation of the data input / output circuit IO and its characteristics will be described later in detail.

The timing generation circuit TG includes a clock signal CLK and a clock enable signal CKE supplied from an external device, and a chip selection signal CS which is a start control signal.
B (here, a so-called inverted signal or the like that is selectively brought to a low level when it is valid is indicated by adding B to the end of the name. The same applies hereinafter), row address strobe signal RASB, column address Strobe signal C
Based on the ASB, the write enable signal WEB and the input / output mask signal DQM, the above various internal control signals, input latch control signals, output latch control signals and output control signals are selectively formed and supplied to each section. The specific configuration and operation of the portion related to the present invention of the timing generation circuit TG and its characteristics will be described later in detail.

FIG. 2 shows a partial block diagram of an embodiment of the data input / output circuit IO included in the synchronous DRAM of FIG. 1, and FIG. 3 shows a partial circuit of the embodiment. The figure is shown. Further, FIG. 4 shows a partial block diagram of an embodiment of the timing generation circuit TG included in the synchronous DRAM of FIG. 1, and FIG. 5 shows a partial circuit diagram of the embodiment. It is shown. Further, FIG. 6 shows a signal waveform diagram of an embodiment of the read mode in which the CAS latency of the synchronous DRAM of FIG. 1 is 3. Based on these figures, the specific configuration and operation of the data input / output circuit IO and the timing generation circuit TG included in the synchronous DRAM of this embodiment and their characteristics will be described.

In FIG. 3, the output latches OL10, O
L20 and data output buffer DOB0 will be explained, and output latches OL10-OL1F, OL20-OL will be described.
2F and the data output buffers DOB0 to DOBF will be described. In FIG. 5, the output latch control signal generation circuits OG10 and OG20 are described, and the output latch control signal generation circuits OG10 to OG13 and OG20 to
The OG23 will be described. Furthermore, in the circuit diagram below,
M with an arrow on the channel (back gate)
The OSFET is a P-channel MOSFET and is shown separately from the N-channel MOSFET without an arrow.

In FIG. 2, the data input / output circuit IO is
Data input / output terminals D0-DF and internal data bus D
1 for each of BUS0 to DBUSF
Six first stage output latches OL10-OL1F, second stage output latches OL20-OL2F and data output buffers DOB0-DOBF are provided. Of these, the input terminals of the first-stage output latches OL10-OL1F are coupled to the corresponding internal data buses DBUS0-DBUSF, and the output terminals thereof are the corresponding second-stage output latches OL20-OL2.
Coupled to the F input terminal. Output latch OL20 to OL
The output terminal of 2F has a corresponding data output buffer DOB.
The output terminals of these data output buffers are coupled to the input terminals of 0 to DOBF and the corresponding data input / output terminals D
0 to DF. The data input / output circuit IO
As described above, each of the 16 data input buffers and the input latches, which are not shown, is provided. However, since the data input buffers and the input latches are not directly related to the present invention, their specific configurations and operations are not shown. I omit the explanation about.

First-stage output latches OL10-OL1F and second-stage output latch OL20 of data input / output circuit IO.
To OL23 are divided into groups of four, and the corresponding output latch control signals OK10 to OK13 (first internal clock signal) or OK20 to OK23 (second internal clock signal) from the timing generation circuit TG are commonly used. Supplied. Also, the data output buffer D
Similarly, OB0 to DOBF are also divided into groups of four, and corresponding output control signals DOC0 to DOC3 are commonly supplied from the timing generation circuit TG.

The first stage output latches OL10 to OL1F forming the data input / output circuit IO are the output latches OL of FIG.
As represented by 10, a pair of clocked inverters CV1 and CV2 whose output terminals are commonly coupled are provided.
including. Of these, the input terminal of the clocked inverter CV1 is coupled to the corresponding internal data bus DBUS0 as the input terminal of the output latch OL10. Further, the output terminals of the clocked inverters CV1 and CV2 are coupled to the input terminal of the clocked inverter CV2 via the inverter V1, and the input terminal of the second stage output latch OL20, that is, the clocked inverter CV3 forming the same. Is connected to the input terminal of. N-channel MOSFE that serves as a non-inverting control terminal of the clocked inverter CV1
The output latch control signal OK10 is commonly supplied to the gate of the T-channel and the gate of the P-channel MOSFET that serves as the inversion control terminal of the clocked inverter CV2, and the gate and clock of the P-channel MOSFET that serves as the inversion control terminal of the clocked inverter CV1. De-inverter CV2
An inverted signal from the inverter V2 is supplied to the gate of the N-channel MOSFET that serves as the non-inversion control terminal of.

As a result, the clocked inverter CV1
Receives the high level of the output latch control signal OK10 and is selectively brought into a transmission state, and the read data supplied from the corresponding read amplifier of the main amplifier MA via the internal data bus DBUS0 is supplied to the second stage output latch OL20. It acts to selectively invert and transmit. The clocked inverter CV2 receives the low level of the output latch control signal OL10 and is brought into a selective transmission state, and constitutes a latch circuit together with the inverter V1 to hold the immediately preceding level at the output terminal of the clocked inverter CV1. It works. That is, when viewed as a circuit as a whole, the first-stage output latch OL10 has the corresponding output latch control signal O
When K10 is high level, internal data bus DB
Latch operation is performed to logically invert read data supplied via US0 and transmit it to the subsequent stage, and when the corresponding output latch control signal OK10 is set to low level, the logic level immediately before that is held. Will be done.

Similarly, the input terminal of the clocked inverter CV3 constituting the second stage output latch OL20 becomes the input terminal of the output latch OL20 and the first stage output latch OL.
10 output terminals. Further, the output terminals of the clocked inverters CV3 and CV4 are coupled to the input terminal of the clocked inverter CV4 via the inverter V3, and serve as the output terminal of the second stage output latch OL20, and the input of the corresponding data output buffer DOB0. The terminal, that is, the inverter V5 and the input terminal of one of the NOR gates NO2 and NO2 constituting the terminal. The gate of the N-channel MOSFET which becomes the non-inversion control terminal of the clocked inverter CV3 and the P-channel MO which becomes the inversion control terminal of the clocked inverter CV4.
The output latch control signal OK20 is commonly supplied to the gates of the SFETs, and the gates of the P-channel MOSFETs that serve as the inverting control terminals of the clocked inverter CV3 and the N-channel MOSFETs that serve as the non-inverting control terminals of the clocked inverter CV4. Is its inverter V
The inversion signal by 4 is commonly supplied.

As a result, the clocked inverter CV3
Receives the high level of the corresponding output latch control signal OK20 and is selectively brought into the transmission state, and the first stage output latch O
It serves to invert and transmit the output signal LO10 of L1 to the corresponding data output buffer DOB0. Further, the clocked inverter CV4 outputs the output latch control signal OK20.
Of the clocked inverter CV3, the latch circuit is formed together with the inverter V3 to hold the previous level at the output terminal of the clocked inverter CV3. That is, when viewed as the circuit as a whole, the second-stage output latch OL20 logically inverts the output signal LO10 of the first-stage output latch OL10 when the corresponding output latch control signal OK20 is set to the high level. Output latch control signal OK
When 20 is set to the low level, the latch operation is performed to hold the logic level immediately before that.

The data output buffer DOB0 includes two N-channel type output MOSFETs N1 and N provided in a totem pole configuration between the power supply voltage of the circuit and the ground potential.
2 inclusive. Of these, the output signal of the NOR gate NO1 is supplied to the gate of the output MOSFET N1, and the output MO
The output signal of the NOR gate NO2 is supplied to the gate of the SFET N2. The output signal LO20 of the second stage output latch OL20 is supplied to one input terminal of the NOR gate NO2, and the inverted signal of the inverter V5 is supplied to one input terminal of the NOR gate NO1. An inverted signal of the corresponding output control signal DOC0 by the inverter V6 is commonly supplied to the other input terminals of the NOR gates NO1 and NO2. The commonly coupled sources and drains of the output MOSFETs N1 and N2 serve as the output terminals of the data output buffer DOB0 and are coupled to the corresponding data input / output terminal D0.

As a result, when the output signal of the NOR gate NO1 is at high level, the output MOSFET N1 is
In other words, the output control signal DOC0 is set to the high level and the output signal LO20 of the second stage output latch OL20 is set.
Is turned on selectively, and outputs a high-level output signal lower than the power supply voltage of the circuit by the threshold voltage to the data input / output terminal D0. Further, the output MOSFET N2 has the second-stage output latch OL when the output signal of the NOR gate NO2 is at the high level, that is, the output control signal DOC0 is at the high level.
When the output signal LO20 of 20 is low level, it is selectively turned on, and a low level output signal such as the ground potential of the circuit is output to the data input / output terminal D0.

Next, the timing generation circuit TG, as shown in FIG. 4, includes a clock buffer CLKB that receives the clock signal CLK through the clock input terminal CLK, and
Each of the four output latch control signal generation circuits OG10 to OG10
OG13 (first internal clock signal generation circuit) and OG20 to OG23 (second internal clock signal generation circuit). The output signal of the clock buffer CLKB is supplied to the output latch control signal generation circuits OG10 to OG13 via the inverter V7 (first inverter) and then to the output latch control signal generation circuits OG10 to OG13, and the output signal of the inverter V9. It is commonly supplied to the output latch control signal generation circuits OG20 to OG23 via (third inverter). The output signal of the inverter V8 is also supplied to another circuit (not shown) of the timing generation circuit TG. Further, as shown in FIG. 6, the clock signal CLK has an extremely high frequency, for example, a period of 10 ns (nanoseconds) or less when the synchronous DRAM is in a read or write mode with a CAS latency of 3. It is a pulse signal.

The clock buffer CLKB of the timing generation circuit TG takes in the clock signal CLK supplied from the external device through the clock input terminal CLK, inverts it, and transmits it to the inverter V7. The output signal of the inverter V7 is supplied to the output latch control signal generation circuits OG10 to OG13 and other circuits (not shown) via the inverter V8 as described above, and also output to the output latch control signal generation circuit via the inverter V9. OG20 ~
It is supplied to the OG 23.

On the other hand, the output latch control signal generation circuits OG10 to OG13 of the timing generation circuit TG are not particularly limited, but the output latch control signal generation circuit OG10 of FIG.
As represented by, a pair of clocked inverters CV5 and CV controlled by an internal control signal LE3.
6 inclusive. Of these, the output signal V8out of the inverter V8 is supplied to the input terminal of the clocked inverter CV5, and the input terminal of the clocked inverter CV6 is
The delay signal from the delay circuit DL1 is supplied. The internal control signal LE3 is commonly supplied to the inverting control terminal of the clocked inverter CV5 and the non-inverting control terminal of the clocked inverter CV6, and the clocked inverter CV5 is supplied.
An inversion signal from the inverter VA is commonly supplied to the non-inversion control terminal and the inversion control terminal of the clocked inverter CV6. The internal control signal LE3 is selectively set to the high level when the synchronous DRAM is set to the read or write mode in which the CAS latency is 3.

The output latch control signal generation circuit OG10 is
Further, a pair of NAND gates NA3 and NA4 whose first input terminal and output terminal are cross-coupled.
including. Among these, the output signal of the NAND gate NA1 is supplied to the second input terminal of the NAND gate NA3, and the inverted signal of the internal control signal LE1 by the inverter VD is supplied to the third input terminal thereof. The output signal of the NAND gate NA2 is supplied to the second input terminal of the NAND gate NA4, and the inverted signal of the internal control signal RST from the inverter VE is supplied to the third input terminal thereof.

The output signal of the clocked inverter CV5 is supplied to one input terminal of the NAND gate NA1, and the inverted delay signal from the inverter VB and the delay circuit DL3 is supplied to the other input terminal. Further, the delay signal of the output signal of the clocked inverter CV6 by the delay circuit DL2 is supplied to one input terminal of the NAND gate NA2, and the inverted delay signal of the inverter VC and the delay circuit DL4 is supplied to the other input terminal. Supplied. The output signal of the NAND gate NA3 becomes the output latch control signal OK10. The internal control signal LE1 is selectively set to a high level when the synchronous DRAM is set to the read or write mode in which the CAS latency is 1, and the internal control signal RST is selected when the system including the synchronous DRAM is reset. Is set to a high level.

As a result, the output latch control signal OK10 is output.
Output latch control signals OK10 to OK13 represented by
Are fixed to the high level when the synchronous DRAM is in the first latency mode, that is, the read or write mode in which the CAS latency is 1, and the internal control signal LE1 is at the high level. In addition, the synchronous DRAM has a second latency mode, that is, C
When the AS latency is set to 2, the read or write mode is temporarily set to the high level with a relatively short time delay from the rising edge of the clock signal CLK, that is, the output signal V8out of the inverter V8,
When the synchronous DRAM is set to the third latency mode, that is, the read or write mode in which the CAS latency is 3, as shown in FIG. 6, the clock signal CLK, that is, the output signal V8 of the inverter V8.
The signal is temporarily set to the high level with a delay of a time td corresponding to the delay time of the delay circuit DL1 from the rising edge of out.

Thus, the synchronous D of this embodiment is
In the RAM, the output latch control signal OK for controlling the first-stage output latches OL10 to OL1F of the data input / output circuit IO.
The generation timings of 10 to OK13 are selectively switched according to the CAS latency, and thereby the level determination timing of the read data output from the selected memory cell of the memory array MARY via the internal data buses DBUS0 to DBUSF. Matching is achieved. The output latch control signal generation circuits OG10 to OG13 of the timing generation circuit TG output the output latch control signal OK1.
A relatively deep logic circuit is required to selectively switch the generation timings of 0 to OK13, but the generation timings of these output latch control signals are described below.
Since the frequency of the clock signal CLK is the highest and the synchronous DRAM is operated in the read or write mode in which the CAS latency is 3, the access time is not affected, so that no problem occurs.

Next, the output latch control signal generation circuits OG20 to OG23 of the timing generation circuit TG are not particularly limited, but the output latch control signal generation circuit OG20 of FIG.
As is represented by, the OR gate OG1 receives the output signal V9out of the inverter V9 at one of its input terminals and receives the inverted delay signal from the inverter VF and the delay circuit DL5 at the other input terminal. The output signal of the OR gate OG1 is supplied to one input terminal of the NAND gate NA5, and the internal control signal LE3 is supplied to the other input terminal of the NAND gate NA5. The output signal of the NAND gate NA5 becomes the output latch control signal OL2.

As a result, the output latch control signal OL2
Is fixed to a high level when the synchronous DRAM is in a read or write mode with a CAS latency of 1 or 2 and the internal control signal LE3 is at a low level, and the synchronous DRAM has a read or write with a CAS latency of 3. When the mode is set and the internal control signal LE3 is set to the high level, it is set to the high level immediately and temporarily in response to the rising edge of the clock signal CLK, that is, the output signal V9out of the inverter V9, as illustrated in FIG. Becomes

As is apparent from FIG. 5, the output latch control signal generation circuits OG20 to OG23 include a complicated logic circuit for selectively switching the generation timing of the output latch control signals OK20 to OK23 according to the CAS latency. Output latch control signals OK20 to OK23
Is generated without much delay in changing the level of the clock signal CLK. As a result, the generation timing of the output latch control signals OK10 to OK13 is controlled by the output latch control signal generation circuits OG10 to OG13 for each CAS latency without sacrificing the access time in the read mode in which the CAS latency of the synchronous DRAM is set to 3. , And can be matched with the read data level determination timing.

When the synchronous DRAM is set to the read mode, the internal data bus DB is set after the clock signal CLK is set to the high level when the read command is input.
The time taa until the read data of the selected memory cell of the memory array MARY is output to US0 to DBUSF is constant in relation to the CAS latency, which causes the generation timing of the output latch control signals OK10 to OK13 to be CAS. This is a cause of having to switch for each latency.

When the synchronous DRAM is set to the read mode in which the CAS latency is 1, all output latch control signals OK10 to OK13 and OK20 are output.
~ OK23 is fixed to the high level as described above,
First stage output latches OL10-O of the data input / output circuit IO
L1F and second stage output latches OL20 to OL2F
Are all through operation. At this time, the read data output via the internal data buses DBUS0 to DBUSF is the same as the first-stage output latches OL10 to OL10.
OL1F and second stage output latches OL20 to OL2F
Output signal LO10-OL1F or O
L20 to OL2F, and output control signal DOC0
When ~ DOC3 is set to the high level, the data is output from the corresponding data input / output terminals D0-DF. As a result, the access device of the synchronous DRAM causes the clock signal C
At the next rising edge of LK, the data input / output terminal D0
It is possible to capture read data output via ~ DF.

On the other hand, when the synchronous DRAM is set to the read mode in which the CAS latency is 2, the output latch control signals OK10 to OK13 are as described above.
The output latch control signal OK20 is generated with a relatively short time delay from the rising edge of the clock signal CLK.
~ OK23 is fixed at a high level.

Therefore, the first stage output latches OL10-OL1F of the data input / output circuit IO are connected to the memory array MAR.
At the effective timing immediately after the read data of the 16 selected memory cells of Y are established on the internal data buses DBUS0 to DBUSF, the through state is set, and the read data is transferred to the corresponding second stage output latches OL20 to OL2.
Output latch control signal OK1
Even after 0 to OK13 are returned to the low level, they are in the latched state and hold these read data, and the corresponding second
It continues to transmit to the stage output latches OL20 to OL2F. Further, the second-stage output latches OL20 to OL2F receive the high level of the corresponding output latch control signals OK20 to OK23 and steadily perform the through operation.
20 to OL2F are output to the data input / output terminals D0 to DF in response to the high level of the output control signals DOC0 to DOC3. As a result, the synchronous DRAM access device can capture the read data output from the data input / output terminals D0 to DF at the rising edge of the clock signal CLK after two cycles.

Next, when the synchronous DRAM is set to the read mode in which the CAS latency is 3, the output latch control signals OK10 to OK13, as described above, the clock signal CLK, that is, the output signal V8 of the inverter V8.
The output latch control signals OK20 to OK2 are generated with a relatively long time td delayed from the rising edge of out.
3 is generated with a relatively short time delay from the rising edge of the clock signal CLK, that is, the output signal V9out of the inverter V9.

Therefore, as shown in FIG. 6, the first stage output latches OL10 to OL1F of the data input / output circuit IO store the read data (a) of the 16 memory cells selected in the memory array MARY. Internal data bus DBU
At the effective timing immediately after being established on S0 to DBUSF, the through state is established, and these read data are started to be transmitted to the corresponding output latches OL20 to OL2F, and the output latch control signals OK10 to OK13 are returned to the low level. After that, the read data (a) is held in the latched state and the corresponding second-stage output latch OL2
0 to OL2F continues to be transmitted. Further, the second stage output latches OL20 to OL2F are connected to the first stage output latches OL10 to O.
When the output signals LO10 to LO1F of L1F are established, the through state is entered and the read data (a) and the like starts to be transmitted to the corresponding data output buffers DOB0 to DOBF, and the output latch control signals OK20 to OK23 are returned to the low level. After that, the read data is held in the latched state and the corresponding data output buffer DOB0
~ Continue transmitting to DOBF.

The output signals LO20 to LO2F of the second stage output latches OL20 to OL2F of the data input / output circuit IO are:
When the corresponding output control signals DOC0 to DOC3 are set to the high level, the data input / output terminals D0 to DF output the read data (a) or the like. As a result, the access device of the synchronous DRAM causes the clock signal C
Read data (a) output from the data input / output terminals D0 to DF at the rising edge of LK after 3 cycles
Etc. can be captured.

By the way, the synchronous DRAM is CAS
When the read mode with a latency of 3,
The time t2, that is, the clock access time tac from the rising edge of the clock signal CLK after the input of the read command to the synchronous DRAM to the output of the read data (a) or the like to the data input / output terminals D0 to DF is as follows. Output signals LO20 to LO2 of the second stage output latches OL20 to OL23 of the data input / output circuit IO
3 level change, that is, output latch control signal OK20-
It depends on the rise time of OK23.

In this embodiment, the output latch control signal generation circuits OG20 to OG23 for generating the output latch control signals OK20 to OK23 are clocked from the clock buffer CLKB via the inverters V7 and V9 as shown in FIG. CLK, output latch control signal O
The generation paths of K20 to OK23 are separated from the generation paths of the output latch control signals OK10 to OK13 by the output latch control signal generation circuits OG10 to OG13 from the initial stage. Therefore, the output latch control signals OK20 to O
The generation path of K23 is the output latch control signal generation circuit OG.
10 to OG13 and other circuits are not affected by the input capacitance of the output latch control signal OK1.
The rise of 0 to OK13 is accelerated by about 10 to 20% as compared with the synchronous DRAM of FIGS. As a result, the clock access time is correspondingly increased in the synchronous DRAM or the like, particularly in the read mode in which the CAS latency is 3, and the synchronous D
The upper limit frequency of the operable clock signal of the RAM can be increased.

The operational effects obtained from the above embodiments are as follows. That is, (1) Synchronous DR having, for example, first to third latency modes and having a two-stage output latch
In AM or the like, the output latch of the first stage is made to perform the through operation in the first latency mode to perform the latch operation in the second and third latency modes, and the output latch of the second stage is made to operate in the first and second latency modes. In the mode, the through operation is performed to perform the latch operation in the third latency mode, and the second internal clock signal generation path that receives the clock signal supplied from the outside and is supplied to the output latch of the final stage, that is, the second stage is provided. , The first internal clock is provided separately from the initial stage of the generation path of the first internal clock signal which is supplied to the output latch of the preceding stage, that is, the first stage, upon receiving the clock signal. The effect that the load capacitance coupled to the signal generation path can exert on the second internal clock signal generation path can be eliminated.

(2) According to the above item (1), it is possible to reduce the delay time of the rising of the second internal clock signal with respect to the rising of the clock signal. (3) According to the above items (1) and (2), the clock access time is increased in the read mode in which the synchronous DRAM has a CAS latency of 3,
The effect that the upper limit frequency of the clock signal with which the synchronous DRAM or the like can operate can be increased is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can have any bit configuration such as a x8 bit configuration or a x32 bit configuration, and can have an arbitrary number of banks.
Further, the internal data buses DBUS0 to DBUSF can be dedicated for writing or reading, and the data input / output terminals D0 to DF can also be separated as data input terminals and data output terminals according to their uses. The memory array MARY forming each bank can be divided into a plurality of mats including its direct peripheral circuits. Furthermore, the block configuration of the synchronous DRAM, the names and combinations of the start control signal and the internal control signal, and their effective levels are not restricted by this embodiment.

In FIG. 2, the first stage input latch OL10 is shown.
~ OL1F and second stage input latches OL20 to OL2
F can be divided into any number of groups. Further, the data input / output circuit IO includes the data input / output terminals D0 to D0.
An input protection circuit provided corresponding to the DF can be included. The data input / output circuit IO can include an arbitrary number of output latches, and when its CAS latency is set to, for example, 1 to 8, each of them has an 8-bit register R0 as illustrated in FIG. It may also include a shift register type output latch consisting of ~ R7.
In this case, the output latch control signal generation circuit SKG2 (second internal clock signal) that generates the output latch control signal SCK2 (second internal clock signal) to be supplied to the output latch of the final stage of the timing generation circuit TG, that is, the register R7. The clock signal CLK should be supplied to the generator circuit) from the clock buffer CLKB via the inverters VG (first inverter) and VH (third inverter), and should be supplied to the output latch of the preceding stage, that is, the registers R0 to R6. Output latch control signal generation circuit SKG1 for generating output latch control signal SCK1 (first internal clock signal)
The clock signal CLK may be supplied to the (first internal clock signal generation circuit) from the clock buffer CLKB via the inverters VG and VI (second inverter).

In FIG. 3, the concrete circuit configurations of the first-stage output latches OL10-OL1F, the second-stage output latches OL20-OL2F and the data output buffers DOB0-DOBF constituting the data input / output circuit IO are various embodiments. Can be taken. In FIG. 4, output latch control signal generation circuits OG10 to OG13 and OG20 to OG23.
The number of installation of the first stage output latches OL10 to OL1F
And the number of group divisions of OL20 to OL2F. Further, the output latch control signal generation circuit OG2
The generation paths for 0 to OG23 may be further separated, and the specific circuit configuration thereof including FIG. 5 is not restricted by this embodiment. In FIG. 6, each start control signal,
The effective levels of the internal control signal, the output latch control signal, the output control signal, and the like can take various embodiments as long as the necessary logic conditions are satisfied, and the prepared CAs can be used.
The type of S latency can also be set arbitrarily.

In the above description, the invention mainly made by the present inventor is applied to a synchronous DRAM having a latency mode which is a field of application which is the background of the invention. However, the invention is not limited thereto. For example, it can be applied to other various memory integrated circuits having a latency mode, digital integrated circuits including output latches, and the like. The present invention can be widely applied to a semiconductor device including at least a plurality of stages of output latches and a system including such a semiconductor device.

[0062]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for example, in a synchronous DRAM or the like having the first to third latency modes and having, for example, a two-stage structure output latch, the first stage output latch is made to perform the through operation in the first latency mode to perform the second operation. And the third latency mode, the second stage output latch performs the through operation in the first and second latency modes to perform the latch operation in the third latency mode, and the clock signal supplied from the outside. A second internal clock signal generation path which is supplied to the final stage, ie, the second stage output latch, and a first internal circuit which receives the clock signal and is supplied to the preceding stage, ie, the first stage output latch By providing the clock signal generation path and the clock signal generation path separately from the initial stage,
Eliminating the influence of the load capacitance coupled to the internal clock signal generation path on the second internal clock signal generation path, and shortening the delay time of the rising of the second internal clock signal with respect to the rising of the clock signal. You can As a result, it is possible to speed up the clock access time in the read mode in which the synchronous DRAM has a CAS latency of 3, and to increase the upper limit frequency of the clock signal with which the synchronous DRAM can operate.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a partial block diagram showing an embodiment of a data input / output circuit included in the synchronous DRAM of FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of the data input / output circuit of FIG.

4 is a partial block diagram showing an embodiment of a timing generation circuit included in the synchronous DRAM of FIG.

5 is a partial circuit diagram showing an embodiment of the timing generation circuit of FIG.

6 is a signal waveform diagram showing an embodiment of a read mode in which the CAS latency of the synchronous DRAM of FIG. 1 is 3. FIG.

FIG. 7 is a partial block diagram showing another embodiment of a synchronous DRAM to which the invention is applied.

FIG. 8 is a partial block diagram showing an example of a timing generation circuit included in a synchronous DRAM developed by the inventors of the present application prior to the present invention.

9 is a signal waveform diagram showing an example of a read mode in which the CAS latency of the synchronous DRAM including the timing generation circuit of FIG. 8 is set to 3. FIG.

[Explanation of reference symbols] BNK0 to BNK1 ... Bank, MARY ... Memory array, RD ... Row address decoder, SA ... Sense amplifier, CD ... Column address decoder, MA ... Main amplifier, RB ... Row address buffer , CB ...
Column address buffer, BS ... Bank selection circuit, I
O: data input / output circuit, TG: timing generation circuit. D0 to DF ... Data input / output terminals, DBUS0 to D
BUSF ... Internal data bus, OL10-OL1F ...
First stage output latch, OL20 to OL2F ... Second stage output latch, DOB0 to DOBF ... Data output buffer,
OK10 to OK1F ... First stage output latch control signal, O
K20 to OK2F ... Second stage output latch control signal, DO
C0-DOCF ... Output control signal. CLK: clock signal, CLKB: clock buffer, OG10-OG
13, OG20 to OG23 ... Output latch control signal generation circuit. SKG1 to SKG2 ... Output latch control signal generation circuit, SCK1 to SCK2 ... Output latch control signal, R
0-R7 ... Register. NO1-NO2 ... Noah (NO
R) gate, NA1 to NA5 ... NAND gate, OG1 ... OR gate, CV1 to CV6
... Clocked inverter, V1-VK ... CMOS inverter, N1-N2 ... N-channel MOSFET,
DL1 to DL5 ... Delay circuits.

Claims (3)

[Claims] 1. A data including a plurality of stages of output latches for sequentially transmitting read data according to a prescribed internal clock signal, and a data output buffer for receiving an output signal of the final stage of the output latch and outputting it from a prescribed external terminal. An input / output circuit and a timing generation circuit for generating the internal clock signal based on a clock signal supplied from the outside, and a generation path of the internal clock signal supplied to the final stage of the output latch, A semiconductor device characterized in that the generation path of the internal clock signal supplied to the preceding stage is separated from the initial stage. 2. The semiconductor device has a multi-bit configuration, and the data input / output circuit includes a plurality of output latches provided corresponding to respective bits of read data that are simultaneously output. The timing generation circuit receives a clock buffer that receives the clock signal, a first inverter that receives the output signal of the clock buffer, and a second inverter that receives the output signal of the first inverter. A first internal clock signal generation circuit for generating a first internal clock signal to be supplied to the preceding stage of the output latch, and an output signal of the first inverter via a third inverter, and a final output of the output latch. A second internal clock signal generation circuit for generating a second internal clock signal to be supplied to the stage. 1. The semiconductor device of 1. 3. The semiconductor device operates synchronously in accordance with the clock signal, and the output timing of read data is delayed by 1 to 3 cycles of the clock signal from the time of inputting a corresponding command, respectively. Synchronous D having a third latency mode
A first stage of the RAM, wherein each of the output latches receives the first internal clock signal, is through-operated in the first latency mode, and is latched in the second and third latency modes. And an output latch and a second stage output latch which receives the second internal clock signal and is through-operated in the first and second latency modes and latched in the third latency mode. The semiconductor device according to claim 1 or 2, which is characterized in that.