JPH09223752A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

Kind Code: A1 Abstract: A non-volatile semiconductor memory device has an ONO interlayer insulating film having a uniform film thickness and a leakage current, thereby reducing the film forming temperature and further thinning the film. At the same time, the reduction in reliability of the tunnel insulating film due to the rewriting operation is suppressed. A lower oxide film or an upper oxide film that is a part of an ONO interlayer insulating film 105 is formed by plasma treatment in an oxidizing atmosphere.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor device, and more particularly to a method for manufacturing an interlayer insulating film.

[0002]

2. Description of the Related Art A non-volatile semiconductor device is shown in FIG.
The stack structure shown in (a) is widely used. Here, 101 is a single crystal Si substrate, 102 is an element isolation oxide film, 103 is a gate oxide film (tunnel insulating film), 104
Is a floating gate electrode, 105 is an interlayer insulating film, 106 is a control gate electrode, 108 is a source, 109 is a drain, 10
6, 110 and 111 are insulating films, 112 is a source wiring, and 113 is a drain wiring. More specifically, the interlayer insulating film 105 is formed by thermally oxidizing the floating gate electrode 104 (phosphorus-doped polycrystalline Si film) as shown in FIG. 1B, and the SiO ₂ film 105 (a) having a thickness of about 4 nm is formed. , A Si ₃ N ₄ film 105 (b) of about 13 nm formed by low pressure chemical vapor deposition (hereinafter referred to as LP-CVD), and the Si
₃ N ₄ film 105 (b) the of SiO ₂ film 105 (c) of about 4nm formed by oxidation in steam atmosphere SiO ₂ equivalent thickness of about 13nm laminated film of a so-called ONO film 105
Is used.

In this nonvolatile semiconductor memory device, the source 108 is + 3.3V, the control gate electrode 106 is -7V,
By opening the drain 109 and grounding the Si substrate 101, the electrons accumulated in the floating gate electrode 104 are extracted to the source side to write information. The voltage is applied using a single pulse each 100 microseconds wide.

According to this method, the floating gate electrode 104
The electrons inside are Fowler-Nordhe
im) tunnel current (F-N current) causes the source 108
At the same time, holes are injected into the gate insulating film 103 from the source 108 side. In addition, the control gate electrode 106 is + 12V, the source 108, the drain 109, S
By grounding the i substrate 101, electrons are injected from the Si substrate 101 to the floating gate electrode 104 to erase information. The voltage is applied with a single pulse each 100 microseconds wide.

[0005]

At present, the ONO film, which is the mainstream of the interlayer insulating film, is more leaky than a single-layer SiO ₂ film or a single-layer CVD-SiO ₂ film formed by thermally oxidizing polycrystalline Si. There is an advantage that the current is small. However, the following problems have become apparent as the non-volatile semiconductor device becomes highly integrated, has a high speed, and has a low voltage.

First, the ONO film formation temperature cannot be lowered. From the studies so far, it has been clarified that the lower layer and the upper layer oxide film (SiO ₂ film) of the ONO film are required to have a thickness of about 4 nm or more in order to retain the charges accumulated in the floating gate. However, as is well known, CV
The D-Si ₃ N ₄ film has a high oxidation resistance, and the oxidation hardly progresses as compared with the oxidation of the Si film. Therefore, it is necessary to oxidize the CVD-Si ₃ N ₄ film to obtain a 4 nm upper layer SiO ₂ film at 900 ° C.
It is necessary to oxidize at the above temperature for about 90 minutes. Since the transistor has already been formed in the lower layer of the ONO film, the heat load of 900 ° C. or higher becomes a great obstacle to the miniaturization of the device.

Furthermore, regarding the reliability of the tunnel insulating film, if there is a high temperature treatment step of 900 or more in the step of forming the interlayer insulating film, the electron trap level in the tunnel insulating film increases, and the tunnel rewriting is repeated to rewrite the tunnel insulating film. Electrons are trapped in the insulating film, which causes a problem that the rewriting time becomes long.

Second, it is very difficult to thin the ONO film formed by this method. In order to increase the operating speed and lower the voltage of the non-volatile semiconductor device, not only the tunnel insulating film but also the interlayer insulating film must be thinned. As described above, the SiO ₂ film above and below the ONO film needs to have a thickness of about 4 nm or more.
There is no choice but to thin the D-Si ₃ N ₄ film. However, Si ₃ N ₄
If the film is made thin, the oxidation resistance of the film deteriorates.
A defect (abnormal oxidation) occurs in which the floating gate electrode is rapidly oxidized when the iO ₂ film is formed. Therefore, the thinning of the ONO film is rate-controlled by the oxidation resistance of the Si ₃ N ₄ film, and at present, the thinning of the Si ₃ N ₄ film thickness of about 8 nm immediately after deposition is the limit. Therefore, the thinning limit of the SiO ₂ equivalent film thickness of the ONO film is about 12 nm ± 0.5 nm.

As a countermeasure against these problems, the upper SiO ₂ film is
The researches for forming the film by the P-CVD method to lower the temperature and to reduce the film thickness are being actively conducted. However, with the current CVD technology, 4n
It is very difficult to form an extremely thin SiO ₂ film of m on a large diameter wafer with good uniformity.

The object of the present invention is to provide a film thickness uniformity of the ONO film,
In addition, the temperature of forming the film is lowered and the film is thinned without deteriorating the leakage current, and the reliability of the tunnel insulating film is improved by lowering the temperature of the ONO film forming process.

[0011]

[Means for Solving the Problems]
This is achieved by oxidizing the i ₃ N ₄ film in an oxidizing plasma atmosphere (hereinafter referred to as plasma oxidation) to form an upper SiO ₂ film.

When plasma is generated in a reduced pressure atmosphere containing oxygen atoms, active oxygen radicals and oxygen ions are formed. Oxygen radicals and oxygen ions excited by plasma have a very strong oxidizing power, and the cations have a particularly strong oxidizing power. Oxidation by the excited oxidizing species is rate-controlled by the lifetimes and diffusion lengths of radicals and ions, and the acceleration energy of ions, and even on the CVD-Si ₃ N ₄ film having high oxidation resistance, SiO ₂ equivalent to a Si substrate is formed. A film is formed. However, the SiO ₂ film thickness is limited to several nm.

FIG. 2 shows the relationship between the SiO ₂ film thickness formed by plasma oxidation of a Si substrate and a CVD-Si ₃ N ₄ film and the plasma oxidation conditions. High frequency (R
F; 13.56 MHz) A power source was applied to the electrode side, and a parallel plate type plasma device in which the Si substrate was grounded was used. In this device, in order to prevent the heavy metal of the electrode material from adhering to the wafer, the entire electrode is covered with a quartz plate.
The conditions for plasma oxidation are: oxygen flow rate = 500 sccm, total pressure =
The basic conditions were 10 Torr, RF power = 300 W, substrate temperature = 400 ° C., and oxidation time = 5 minutes.

FIG. 2A shows the RF power dependency, FIG. 2B shows the oxidation (plasma) time dependency, and FIG. 2C shows the substrate temperature dependency. SiO on CVD-Si ₃ N ₄ film
_{The two} film thicknesses are slightly thinner than those on the Si substrate, but it can be seen that almost the same film thickness can be obtained. As described above, by plasma oxidation, SiO ₂ of several nm can be easily formed on the Si ₃ N ₄ film even at a low temperature of about 400 ° C. Further, the SiO ₂ film thickness distribution is also very good, and the film thickness uniformity equivalent to that of a known thermal oxide film using dry oxygen can be obtained.

3 and 4 show the relationship between the CVD-Si ₃ N ₄ deposited film thickness and the film thickness after oxidation. In the figure, a SiO ₂ film having a thickness of about 4 nm is formed on a Si ₃ N ₄ film, and the conventional method and the present invention are compared. FIG. 3 shows S deposited on a Si substrate.
The results of measuring the i ₃ N ₄ film thickness and the film thickness before and after oxidation by the ellipsometry method are shown in FIG. 4, which shows the relationship between the Si ₃ N ₄ film thickness of the ONO capacitor and the SiO ₂ conversion film thickness calculated from the capacitor capacitance. It is a thing.

As is apparent from FIG. 3, in the conventional high temperature steam oxidation method (hereinafter referred to as pyrogenic oxidation), S
When the i ₃ N ₄ film thickness is made thinner than 8 nm, the underlying Si substrate is oxidized and the film thickness is rapidly increased. On the other hand, according to the present invention, it can be seen that the Si ₃ N ₄ film does not vary in thickness up to about 4 nm. That is, in the plasma oxidation according to the present invention, the diffusion distance of oxygen radicals and oxygen ions is very short, so that the oxidizing species do not reach the base substrate and Si ₃
Oxidation of the N ₄ film proceeds. Therefore, the interface between the Si ₃ N ₄ film and the upper oxide film has a very steep structure. On the other hand, in the conventional method, since the oxidation species have a long diffusion distance due to high-temperature oxidation, the oxidation species diffused in the Si ₃ N ₄ film of about 8 nm are Si.
It reaches the substrate and abruptly oxidizes the Si substrate, causing abnormal oxidation. Therefore, as shown in FIG.
The thinning of the NO film is limited to about 12 nm. According to the present invention, the ONO film can be thinned to about 9 nm.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIG. In this example, in order to compare current-voltage characteristics (IV characteristics) of ONO films formed by several kinds of methods, the polycrystalline Si upper electrode / ONO insulating film / polycrystalline Si lower electrode shown in FIG. Was manufactured.

First, a 500 nm element isolation oxide film 202 is formed on the N-type single crystal Si substrate 201 by the well-known LOCOS method, and then phosphorus is deposited by LP-CVD.
200 nm of polycrystalline Si film 203 containing x10 ²⁰ / cm ³
accumulate. In this example, monosilane (SiH ₄ ) and phosphine (PH ₃ ) were used to form the phosphorus-doped polycrystalline Si film 203, and deposition was performed at a temperature of 630 ° C. Next, after performing heat treatment for 30 minutes in a nitrogen atmosphere at 800 ° C., the phosphorus-doped polycrystalline Si film 203 was processed into a predetermined shape by a well-known lithography and dry etching method to form a lower electrode 203.

Next, seven types of ONO films were formed by the method shown in Table 1.

[0020]

[Table 1]

The wafers No. 1 to No. 6 shown in Table 1 are
The lower electrode 203 was oxidized by a dry oxidation method at 800 ° C. diluted with nitrogen to 10% to form a 4 nm SiO ₂ film 204 (a) to be a lower oxide film 204 (a). No.7
Wafer is 4nm lower oxide film 2 by plasma oxidation method.
04 (a) was formed. Here, a parallel plate type device in which the Si substrate 201 is grounded and an RF power source is connected to the electrode side is used. The substrate temperature is 400 ° C., the pressure is 10 torr, and the power source is 20
Oxidation was performed for 2 minutes under the condition of 0W.

Next, a 6 nm and 13 nm Si ₃ N ₄ film 204 (b) was deposited by the LP-CVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as source gases. Here, No. 2 and No. 4 were deposited to 6 nm, and others were deposited to 13 nm. In this embodiment, the Si ₃ N ₄ film 20 is used.
4 (b) was deposited at a temperature of 720 ° C. and a pressure of 0.6 Torr. Next, as the upper oxide film 204 (c), the Si ₃ N ₄ film 204 (b) is oxidized by the method described below to obtain 4 nm.
Of SiO ₂ film 204 (c) was formed. No.1 and No.2
Is a reference sample, which is an oxidation of the Si ₃ N ₄ film 204 (b) by a conventional pyrogenic oxidation method. Here, 9
Oxidation at 00 ° C. for 90 minutes performs 4 nm SiO ₂ film 204
(C) was formed. At this time, pre-annealing for stabilizing the wafer temperature was performed for 30 minutes before inserting the wafer into the furnace and performing oxidation. The other wafer is an oxidation of the Si ₃ N ₄ film 204 (b) by the plasma oxidation method. Here, the Si substrate 201 is grounded, and a parallel plate type device in which an RF power source is connected to the electrode side performs oxidation for 5 minutes under the conditions of a substrate temperature of 400 ° C., an oxygen flow rate of 500 sccm, a pressure of 10 torr, and a power source of 300 W. . Further, wafers No. 5 and No. 6 were added with dry oxidation and pyrogenic oxidation for 30 minutes at 850 ° C., respectively.

After forming the upper oxide film 204 (c) by the above method, a polycrystalline Si film 205 containing phosphorus is formed to a thickness of 200 nm by LP-CVD under the same conditions as the lower electrode 203.
accumulate. Subsequently, after heat treatment is performed for 30 minutes in a nitrogen atmosphere at 800 ° C., the phosphorus-doped polycrystalline Si film 205 is processed into a predetermined shape to form an upper electrode 205, and a planar capacitor as shown in FIG. 5 is manufactured. did.

FIG. 6 shows a comparison of current-voltage characteristics of the ONO films 204 having different Si ₃ N ₄ film thicknesses 204 (b). The broken line shows the result of the conventional pyrogenic oxidation, and the solid line shows the result of the plasma oxidation of the present invention. This figure shows the Si substrate 20.
1 is grounded and a positive voltage is applied to the upper electrode 205, and the horizontal axis represents the applied voltage applied to the ONO film 204 by the electric field strength normalized by the SiO ₂ equivalent film thickness.

When the Si ₃ N ₄ film thickness 204 (b) is 13 nm, the leakage current increases in the plasma oxidation method on the high electric field side, but a significant difference from the conventional method on the low electric field side is seen. And shows a good withstand voltage. Moreover, the SiO ₂ converted film thicknesses of both were approximately the same as 13.2 nm to 13.5 nm. On the other hand, the Si ₃ N ₄ film thickness 204 (b) of the sample of the conventional method having a thickness of 6 nm has a SiO ₂ conversion film thickness of 35.3 nm, which causes abnormal oxidation of the lower electrode 203 and significantly increases the leakage current. It was observed. On the other hand, in the present invention, almost no increase in leakage current occurred. Here, an example of plasma oxidation by oxygen (O ₂ ) is shown, but nitric oxide (NO), nitrous oxide (N ₂ O), water vapor (H ₂ O)
Atmosphere containing oxygen atoms such as, and a mixed atmosphere thereof,
Even if the plasma oxidation is performed in a mixed atmosphere with an inert gas, the same effect is obtained.

FIG. 7 shows a comparison of current-voltage characteristics of a sample in which the lower SiO ₂ film 204 (a) is formed by the dry oxidation method (No. 3) and the plasma oxidation method (No. 7). The characteristics of both are almost the same, and it can be seen that the plasma oxidation method is also effective in forming the lower oxide film 204 (a). In general, the oxidation of the phosphorus-doped polycrystalline Si film only produces a non-uniform SiO ₂ film because the oxidation proceeds along the grain boundaries of the polycrystalline Si. Further, since phosphorus in the polycrystalline Si film diffuses into the SiO ₂ film, the leakage current increases remarkably. On the other hand, in plasma oxidation, a uniform SiO ₂ film is obtained, and since the oxide film is formed at a very low temperature of about 400 ° C., phosphorus hardly diffuses into the film. Therefore, a good withstand voltage is exhibited.

FIG. 8 shows that after plasma oxidation, the temperature was 30 ° C. at 850 ° C.
It is the figure which showed the comparison of the current-voltage characteristic of the sample which performed the dry oxidation of the minute and the pyrogenic oxidation. Although there is no significant difference in the leakage current in the low electric field, it can be seen that the leakage current in the high electric field side is reduced by the reoxidation treatment at about 850 ° C. This is CVD-S due to high temperature oxidation (heat treatment).
This is because the film quality of the i ₃ N ₄ film 204 (b) was improved, and the same effect was observed even if the above oxidation was performed before plasma oxidation. Therefore, considering only the film quality of the ONO film, it is effective to perform high-temperature oxidation treatment in a range where abnormal oxidation does not occur.

In this embodiment, an RF (13.56 MHz) power source is shown as an example of a high frequency power source for generating plasma, but similar results can be obtained if the frequency is in the range of 50 KHz to microwave (2.45 GHz). It was Although an example using a parallel plate type plasma oxidation apparatus is shown here, in the parallel plate type, a damage layer is formed in the film when the power is excessively increased. Further, if the substrate temperature is raised too high, impurities are desorbed from the inner wall of the chamber, electrodes, etc., and are taken into the film. Therefore, when using the parallel plate type, it is desirable that the power is about 500 W or less and the temperature is about 500 ° C. or less. On the other hand, the oxidation time is longer than that of the parallel plate type,
Good characteristics were obtained even when using a remote plasma type that does not damage the thin film.

As described above, according to this embodiment, O
The formation temperature can be significantly lowered while maintaining the electrical characteristics of the NO film. Further, it is possible to obtain an ONO film having an equivalent oxide film thickness of 10 nm or less, which cannot be realized by the conventional method.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the ON shown in FIG.
A planar capacitor composed of an O-stacked film / polycrystalline Si film electrode / tunnel insulating film / Si substrate was produced and the electrical characteristics of the tunnel insulating film were evaluated.

First, a 500 nm element isolation oxide film 302 is formed on a P-type single crystal Si substrate 301 by the well-known LOCOS method, and then a 9 nm thick SiO ₂ film 303 is formed by pyrogenic oxidation at 850 ° C. A tunnel insulating film 303 is formed. Then, the phosphorus-doped polycrystalline Si film 3 to be the gate electrode 304 is formed by the method described in the first embodiment.
After depositing 04 of 200 nm, heat treatment was performed for 30 minutes in a nitrogen atmosphere at 800 ° C. After that, an ONO film was formed on the gate electrode 304 by various methods in order to evaluate the influence of the heat load in the ONO film forming step on the tunnel insulating film.

First, 800 diluted to 10% with nitrogen
The surface of the gate electrode 304 is oxidized by a dry oxidation method at a temperature of 4 ° C. and 4 nm of SiO ₂ corresponding to the lower oxide film 305 (a) is formed.
The film 305 (a) was formed. Subsequently, a 13 nm CVD-Si ₃ N ₄ film 305 (b) was deposited by the method described in Example 1.

The upper oxide film 305 (c) is formed by oxidizing the Si ₃ N ₄ film 305 (b) by the following three methods to obtain 4n.
m SiO ₂ film 305 (c) was formed. The first is a reference sample, which is made by the conventional pyrogenic oxidation method.
_This is the oxidation of the ₃ N ₄ film. Here, oxidation was performed at 900 ° C. for 90 minutes to form a 4 nm SiO ₂ film 305 (c).
At this time, pre-annealing for stabilizing the wafer temperature was performed for 30 minutes before inserting the wafer into the furnace and performing oxidation.

The second is the oxidation of the Si ₃ N ₄ film 305 (b) by plasma oxidation. Here, the Si substrate 301
Was oxidized for 5 minutes under the conditions of a substrate temperature of 400 ° C., a pressure of 10 torr, and a power supply power of 300 W by a parallel plate type apparatus in which an RF power supply was connected to the electrode side.

Third, after plasma oxidation, at 850 ° C., 3
This is a sample to which 0 minutes of pyrogenic oxidation was added. Even with this oxidation, before inserting the wafer into the furnace and performing oxidation,
Pre-annealing for stabilizing the wafer temperature was performed for 30 minutes.

The above three samples were processed into the predetermined shapes of the ONO film 305 and the phosphorus-doped polycrystalline Si film 304 by the well-known lithography and dry etching methods to form the MOS capacitor shown in FIG.

Using the MOS capacitor having this structure, the characteristic variation of the tunnel insulating film 303 due to high electric field stress was evaluated. FIG. 10 shows the fluctuation of the gate voltage when a constant current stress is applied (negative gate voltage, 10 mA / cm ² ). The decrease in gate voltage due to hole trapping at the initial stage of stress application is the same in all samples, but the amount of trapped electrons is the same as in the ONO film 30.
The lower the formation temperature of 5, that is, the conventional method (pyrogenic oxidation 900 ° C., 90 minutes + 30 minutes), plasma oxidation + pyrogenic oxidation (850 ° C., 30 minutes + 30)
Min) and the order of plasma oxidation became smaller. Further, FIG. 11 shows the leakage current at 6 MV / cm after applying the same constant current stress. Leakage current value can also be measured by conventional method, plasma oxidation +
Pyrogenic oxidation (850 ℃, 30 minutes + 30 minutes),
It became smaller in the order of plasma oxidation. These results are
The higher the formation temperature of the NO film 305, the tunnel insulating film 3
No. 03 shows that the characteristic deterioration becomes large. Also,
Also in the ONO film formed by the other method described in Example 1, a better result was obtained as the method in which the overall heat load was smaller. As described above, according to this embodiment, the reliability of the tunnel insulating film can be significantly improved.

(Embodiment 3) A third embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. In this example, the memory cell shown in FIG. 1 was manufactured in order to evaluate the variation of the write time and the threshold voltage.

First, the element isolation oxide film 102 is formed on the P-type single crystal Si substrate 101 by the well-known LOCOS method, and then the tunnel insulating film 103 of 9 nm is formed by the steam oxidation method at 850 ° C. Next, a polycrystalline Si film 104 containing 3 × 10 ²⁰ / cm ^{3 of} phosphorus is formed by the LP-CVD method.
Is deposited to 200 nm. In this example, monosilane (SiH ₄ ) and phosphine (PH ₃ ) were used to form the phosphorus-doped polycrystalline Si film 104, and deposition was performed at a temperature of 630 ° C. Next, after performing a heat treatment for 30 minutes in a nitrogen atmosphere at 800 ° C., one side surface of the phosphorus-doped polycrystalline Si film 104 to be the floating gate electrode 104 (see FIG. 1) is formed by a well-known lithography and dry etching method. The direction parallel to the paper surface) was processed into a predetermined shape.

Next, by the three methods shown in Example 2, O
After forming the NO laminated interlayer insulating film 105, a 200 nm phosphorus-doped polycrystalline Si film 1 to be the control gate electrode 106.
The SiO ₂ film 107 of 06 and 100 nm is LP-CV
It was deposited by the D method and heat-treated for 20 minutes in a nitrogen atmosphere at 800 ° C. Then, the SiO ₂ film 107, the phosphorus-doped polycrystalline Si film 106 serving as the control gate electrode 106, the ONO interlayer insulating film 105, and the other side surface of the floating gate electrode 104 (perpendicular to the plane of FIG. 1) are formed by lithography and dry etching. The direction) is processed into a predetermined shape to form the control gate electrode 106 and the floating gate electrode 104.
Subsequently, arsenic (As) was ion-implanted into the regions to be the source 108 and the drain 109, and then nitrogen annealing was performed at 800 ° C. for 20 minutes to form the source 108 and the drain 109.

Next, after depositing a 150 nm thick SiO ₂ film 110 by the LP-CVD method, the entire surface of the SiO ₂ film 110 is etched by anisotropic dry etching to form the floating gate electrode 104 and the control gate electrode 106 side wall portion. Then, the sidewall insulating film 110 is formed. Then, LP-C
By the VD method, a SiO ₂ film (PS containing 4 mol% of phosphorus)
(G film) 111 is deposited to a thickness of 200 nm, and then the source 108,
A contact hole is formed so that the surface of the drain 109 is exposed. Finally, aluminum (Al) was deposited to a thickness of 500 nm by the reactive sputtering method, and then processed into a predetermined shape to form the source wiring 112 and the drain wiring 113, and the memory cell shown in FIG. 1 was manufactured.

Rewriting characteristics were evaluated using the nonvolatile semiconductor memory device having this structure. The erasing operation is performed by performing FN on the floating gate electrode 104 through the entire surface of the tunnel insulating film 103.
The write operation is performed by injecting charges by a current, and the write operation is performed on the tunnel insulating film 1 from the floating gate electrode 104 to the drain 109.
No. 03 F-N current was used to extract charges. At the time of erasing, a pulse of +12 V, 0 V for the source 108, drain 109 and Si substrate 101 was applied to the control gate electrode 106, and erasing was performed while confirming the threshold voltage. When writing, the control gate electrode 106 is
Writing was performed while confirming the threshold voltage by applying a pulse of 7 V, drain 109 +3 V, source 108 open, and Si substrate 101 grounded.

FIG. 12 shows a comparison of the change in the write time with respect to the number of times of rewriting of the memory cell. Compared to the case where the upper oxide film of the ONO film 105 is formed by the conventional method, the present invention using plasma oxidation can suppress the fluctuation of the writing time. Regarding the erase characteristic (β), no significant difference was found among the three memory cells.

Next, after rewriting operation 10 ⁵ times,
The charge retention characteristics were evaluated from the change in threshold value. FIG.
The results are shown in 3. The amount of change in the threshold voltage is ONO
Depending on the formation temperature of the upper oxide film of the film 105, the variation of the writing time was suppressed in the order of the conventional method, oxygen plasma + pyrogenic (850 ° C.), and oxygen plasma. The same effect was obtained with the ONO film forming method shown in the first embodiment.

[0045]

According to the present invention, the formation temperature can be lowered and the ONO film can be thinned without increasing the leakage current of the ONO film. As a result, the electron trap level of the tunnel insulating film and the low electric field leakage current due to the high electric field stress are suppressed, and it is possible to provide a good non-volatile semiconductor memory device in which the writing time is increased and the charge retention characteristic is less changed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a memory cell showing a third embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the relationship between plasma oxidation conditions and SiO ₂ film thickness.

FIG. 3 is an explanatory diagram showing a relationship between a deposited film thickness of a CVD-Si ₃ N ₄ film and a film thickness after oxidation.

FIG. 4 is an explanatory diagram showing the relationship between the CVD-Si ₃ N ₄ film thickness and the SiO ₂ converted film thickness of the ONO film.

FIG. 5 is a sectional view of a capacitor showing a first embodiment of the present invention.

FIG. 6 is a characteristic diagram showing a comparison of current-voltage characteristics of ONO films.

FIG. 7 is a current-voltage characteristic diagram of an ONO film according to a difference in a forming method of a lower oxide film.

FIG. 8 is a current-voltage characteristic diagram of an ONO film according to a difference in reoxidation method.

FIG. 9 is a sectional view of a capacitor showing a second embodiment of the present invention.

FIG. 10 is a comparative characteristic diagram of variations in gate voltage due to constant current stress.

FIG. 11 is a comparative characteristic diagram of a leakage current after applying a constant current stress.

FIG. 12 is a comparative characteristic diagram of changes in writing time with respect to the number of rewritings.

FIG. 13 is a comparative characteristic diagram of a threshold voltage fluctuation amount after a rewriting operation.

[Explanation of symbols]

101 ... Single crystal silicon substrate, 102 ... Element isolation oxide film, 103 ... Gate insulating film, 104 ... Floating gate electrode,
105 ... ONO film, 106 ... Control gate electrode, 107,
110, 111 ... Insulating film, 108 ... Source, 109 ... Drain.

Front page continuation (72) Inventor Jiro Yugami 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] 1. A floating gate electrode provided on a semiconductor substrate having a first conductivity type via a tunnel insulating film, and provided at least partially on the floating gate electrode via an interlayer insulating film. In the electrically rewritable nonvolatile semiconductor memory device including the control gate electrode, and the second conductivity type source / drain regions provided on the semiconductor substrate separately from each other, at least a part of the interlayer insulating film is provided. ,
A method of manufacturing a nonvolatile semiconductor memory device, comprising: an insulating film formed in an oxidizing plasma atmosphere. 2. The interlayer insulating film comprises a laminated film of silicon oxide film / silicon nitride film / silicon oxide film, and the upper or lower silicon oxide film is a silicon oxide film formed in an oxidizing plasma atmosphere. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1. 3. The S of the interlayer insulating film according to claim 1 or 2.
A method for manufacturing a non-volatile semiconductor memory device having an io ₂ converted film thickness of 12 nm or less. 4. A method for manufacturing a nonvolatile semiconductor memory device according to claim 2, wherein the formation temperature of the upper or lower silicon oxide film is 500 ° C. or lower. 5. A method for manufacturing a non-volatile semiconductor memory device, wherein the silicon oxide film formed in the plasma atmosphere according to claim 2 is heat-treated in an oxidizing atmosphere at 850 ° C. or lower. 6. A nonvolatile semiconductor memory device according to claim 2, 3, 4, or 5, wherein the silicon oxide film has a film thickness of 4 nm or more. 7. The nonvolatile semiconductor memory device according to claim 2, wherein the silicon nitride film is a silicon nitride film formed by a chemical vapor deposition method, and the film thickness of the silicon nitride film when deposited is 8 nm or less. . 8. The silicon oxide film according to claim 2 is a high frequency power source having a frequency of 50 KHz or more and 2.45 GHz or less,
And a method for manufacturing a non-volatile semiconductor memory device formed in an oxidizing plasma atmosphere excited by electric power of 500 W or less. 9. A method of manufacturing a semiconductor memory device, wherein the high frequency power source according to claim 8 is a parallel plate type plasma generator connected to an electrode side. 10. The oxidizing plasma atmosphere according to claim 1 or 2, which is oxygen (O ₂ ), water vapor (H ₂ O), nitric oxide (NO) or nitrous oxide (N ₂ O). A method for manufacturing a non-volatile semiconductor memory device, which is formed by introducing the gas, a mixed gas of the gases, or the gas and an inert gas.