JPH09230968A - Data communication device and external interface control method - Google Patents

Abstract

(57) Abstract: It is difficult to perform high-speed data transfer on an external i / f in a system using an open collector type buffer, and in a system using a totem pole type buffer, a connection cable Depending on the conditions on the receiver side and the receiver side, a transient current or a steady current that exceeds the driving capability will flow. SOLUTION: Buffer IC sections A and B10 are provided in a parallel port control section 102 according to a receiver condition of a partner machine connected via a parallel interface (i / f).
1 is selected, and the selected buffer IC unit A10
Data is transferred via 1a or the buffer IC unit B101b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device having at least two external interfaces (i / f) and an external interface control method.

[0002]

2. Description of the Related Art In a facsimile, a printer or the like which is connected to a terminal such as a personal computer to transfer data, a parallel i known as Centronics i / f.
With / f, some handshake timings related to data transfer can be fixed or set by the user.

An open collector type buffer is generally used as the buffer IC for driving the Centronics i / f signal.

[0004]

However, in the open collector type buffer, the switching speed of the signal level greatly changes depending on the external resistor and the termination condition on the receiver side. As a method of increasing the switching speed, it is possible to reduce the resistance value of the external resistor. However, the power consumption increases and the speed cannot be significantly increased.

For this reason, in a system using an open collector type buffer, it is difficult to perform high-speed data transfer on the external i / f, and it is necessary to increase the interval between signal changes related to data transfer. Transfer speed will be slower.

Therefore, in order to increase the switching speed of the signal level, a totem pole output buffer may be used. However, depending on the conditions of the connection cable and the receiver side, a transient current or a steady current exceeding the driving capability may flow. There was a possibility that it would end.

Under these circumstances, even if the switching speed is sacrificed, an open collector type buffer has been used in consideration of the connectivity with all personal computers, but in recent years, a parallel port has been used to achieve both high speed operation. There is an increasing demand for communication aimed at people.

The present invention has been made to solve the above problems, and selects a desired external interface according to the receiver condition of a connected partner device, and a data communication device which enables high-speed data transfer. It is intended to provide an external interface control method.

[0009]

In order to achieve the above object, the present invention is a method for controlling an external interface of an apparatus having at least two external interfaces (i / f), which is a receiver condition of a connected counterpart device. It is characterized by including respective steps of selecting a desired external i / f according to the above, and performing data transfer via the selected external i / f.

The present invention is also a data communication apparatus having at least two external interfaces (i / f), and selecting means for selecting a desired external i / f according to the receiver condition of the connected counterpart device. And communication means for performing data communication via the external i / f selected by the selection means.

In such a configuration, a desired external i / f is selected according to the receiver condition of the connected counterpart device, and high-speed data communication is performed via the selected external i / f.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a facsimile apparatus having a bidirectional Centro interface (i / f). In the figure, 101a is a buffer IC section a which performs buffering between the parallel port control section and i / f input / output, and 101b is a buffer I which performs buffering between the parallel port control section and i / f input / output.
C units b and 102 are parallel port control units that perform data transfer control of the parallel port. Reference numeral 103 is a reading unit for reading an original, and 104 is a codec (CODEC) for encoding / decoding data.

Reference numeral 105 denotes N for performing network control with a general public line.
The CU 106 is a modem (MODEM) that modulates / demodulates transmission / reception data. Reference numeral 107 denotes a bus use arbitration with a main control unit (to be described later) and DM in response to a DMA transfer request from each unit
A DMA control unit that controls A transfer, 108 is an image memory that stores image data, and 109 is a main control unit that controls the entire system. Reference numeral 110 is a recording unit for recording image data, and 111 is an operation unit for an operator to operate the system.

BUFSEL in the figure is a buffer IC
Buffer selection signal for switching the buffer type for the unit 101, XPIFEN is an i / f bus enable signal for instructing the buffer IC unit 101 to activate the i / f bus, and PIFDIR is i / f for the buffer IC unit 101. An i / f bus direction designation signal for designating the input / output direction of the bus, HLDREQ is a bus use request signal to the main control unit 109, and XHLDACK is a bus use request acceptance signal from the main control unit 109. DMAREQ1 is a DMA transfer request signal from the parallel port control unit 102 to the DMA control unit 107, XDMAACK1 is a DMA transfer acceptance signal from the DMA control unit 107, and DMAREQ2 is a DM from the CODEC 104 to the DMA control unit 107.
The A transfer request signal and XDMAACK2 are DMA control units 10
7 is a DMA transfer acceptance signal, LAST is a final data transfer end signal from the DMA control unit 107, INTPIF is an interrupt request signal to the main control unit 109, INTDKC is an interrupt request signal delay clock that delays the generation of the interrupt signal INTPIF. is there. And STSO-4:
0 is the i / f output status signal (0-4), STSI-
3: 0 indicates i / f input status (0-3), DATA-
7: 0 is an i / f parallel data bus (8).

FIG. 2 is a block diagram showing a detailed configuration of the parallel port control unit 102. In the figure, 201
Is a reception control unit that performs a handshake related to data transfer during reception, 202 is a transmission control unit that performs a handshake related to data transfer during transmission, and 203 is a TPI timer that generates timing during transmission and reception. Reference numeral 204 is a status control unit that generates an i / f status signal, 205 is an interrupt control unit that generates an interrupt signal to the main control unit,
Reference numeral 206 denotes a data buffer that buffers transmitted / received data. 207 is a DMA for controlling a DMA request
A control unit, 208 is a mode generation unit that generates an operation mode by setting a control register, 209 is an R / W control unit that controls read / write of the control register and the data buffer, and 210 is transmission / reception data and operation designation Is a control register for.

IFMOD in the drawing is an interface mode instruction signal for designating the operation mode of the parallel port control unit, and R / W is a read / write signal from the main control unit 109 to the parallel port control unit 102.

Next, the operation of the parallel port control unit 102 in the embodiment will be described. In the embodiment, the IE
Among the data transfer methods defined in the EE-P1284 standard, the operation based on the following four operation modes is possible.

(1) Compatibility
) Mode (2) Nibble mode (3) Byte (BYTE) mode (4) ECP (ECP Fwd / ECP Rev) mode In the parallel port control unit 102 in order to operate in accordance with each of the above modes. The operation mode of the control register 21
The IF generated by the mode generation unit 208 according to the setting of 0
It is specified by the MOD signal. The parallel port control unit 102 performs switching of data transmission / reception and switching of the handshake format with an external device related to data transfer by the IFMOD signal. Buffer IC section 101A, 1
01B is switched by the BUFSE generated by the setting of the control register 210 in the parallel port control unit 102.
It is performed by the L signal.

Table 1 shows the input / output status signals (STSO-4: 0, STSI-3: 0) in each of the above modes.
3 is a correspondence table of signal names and signal definitions of.

[0021]

[Table 1]

The data transfer rate defining method for each mode will be described below.

[Compatibility Mode] By setting the mode corresponding to the control register 210, the operation mode in the parallel port control unit 102 becomes the compatibility mode.

FIG. 3 is a diagram showing the response timing of the Busy signal when the rising / falling of the nStrobe signal is set as the data strobe timing. FIG. 3A shows the response timing at the fall, and FIG. 3B shows the response timing at the time of the rise setting.

Although the data strobe is performed by the change of the signal nStrobe signal from the host side, the control register 2 selects the falling edge or the rising edge of the change edge.
It can be changed by setting 10. Busy again
The signal is nS according to the above-mentioned rising / falling setting.
It goes high in synchronization with the change in the probe signal.

The response timing of the Busy, nAck signal is the time designated by the TP1 timer (T1 ≧ 0.5).
uS) and Busy, nAck signals, respectively, and is determined by the setting of a 4-bit shift register. FIG. 3 also shows changes in the response timing due to the settings of the TP1 timer and the two 4-bit shift registers. The shift register shifts by one bit every T1 time, and the value of the most significant bit corresponds to the output of the Busy, nAck signal. Start of counting of TP1 timer is nSt
Since the robe signal becomes H, the response timing of the Busy and nAck signals after the change of the Busy signal L → H does not depend on the strobe edge setting. This timing control is not performed immediately when there is no free space in the data buffer unit 206. A status in the busy state is sent out, and when there is free space in the data buffer unit 206, a response according to the setting is performed. In this way, Busy, nAc
The maximum reception rate can be defined by controlling the response timing of the k signal.

[Nibble Mode] By setting the mode corresponding to the control register 210, the operation mode in the parallel port control unit 102 becomes the nibble mode.

FIG. 4 is a diagram showing the timing of the status response at the time of data transmission. The process of transmitting data in the nibble mode will be described below.

After the data is written in the transmission buffer, when the status on the host side becomes idling, the lower Nibb
After le is set and the time (Tp ≧ 0.5uS) specified by the TP1 timer for generating the basic period has elapsed, Ptrcl
The k signal is set to L. When the HostBus signal is returned from the host, the PtrClk signal is immediately set to H. At the same time, the transmission signal on the transmission status line is switched from data to printer status. Then, when the host Busy signal of the host becomes L, the upper Nibbl
e data is set, and the Ptrclk signal is set to L after the TP time has elapsed. When the Host Busy signal is returned from the host, the sending signal of the sending status line is switched from data to printer status after the TP time has elapsed from that point. Repeat this process to send multiple bytes. In this way, by controlling the TP time, the maximum transmission rate can be defined.

[Byte mode] By setting the mode corresponding to the control register 210, the operation mode in the parallel port control unit 102 becomes the byte mode.

FIG. 5 is a diagram showing the timing of status response during transmission. Hereinafter, a process at the time of transmitting data in the byte mode will be described.

After writing the data in the transmission buffer, when the status on the host side becomes idling, the data is set in the data bus, and after the time (Tp ≧ 0.5 uS) specified by the TP1 timer for generating the basic period elapses, Ptrc
The lk signal is set to L. And the host HostBus
The Ptrclk signal is set to H after TP time has elapsed from the response of the y signal. While the HostBusy signal of this host is H, if there is a rise of HostClk from L to H, 1
The byte transfer ends. Further, when transmitting a plurality of bytes, data is set after waiting for the HostBusy signal to become L, and the same processing is repeated thereafter. in this way,
By controlling the TP time, the maximum transmission rate can be defined.

[ECP mode] By setting the mode corresponding to the control register 210, the operation mode in the parallel port control unit 102 becomes the ECP mode. EC
Two modes of transmission and reception are defined in P mode,
It is necessary to set the transmission / reception according to the setting of the ECP mode. Hereinafter, transmission / reception control of data in the ECP mode will be described with reference to FIG.

(ECP Fwd) -Reception- (A) shown in FIG. 6 is a diagram showing the status response timing in the ECP Fwd mode. Based on this diagram,
The control when receiving data in the ECP Fwd mode will be described.

The data is strobed by the change of the signal HostClk signal from the host side, and the selection of the falling edge or the rising edge of the change edge can be changed by the setting of the control register 210. Also, PtrBus
The y signal does not depend on the above-mentioned rising and falling settings, and is H
It goes high in synchronization with the fall of the ostClk signal. Also, as in the compatibility mode described above, Ptr
The response timing of the Busy signal is determined by the time designated by the TP1 timer (T1 ≧ 0 uS) and the setting of the 4-bit shift register assigned for Busy signal control (range of T1 × 1 to 4). Timing control is not performed immediately when there is no free space in the data buffer 206, the status in the Busy state is sent out, and when there is free space in the data buffer 206, a response according to the setting is performed. In this way, by controlling the response timing of the Busy signal, the maximum reception rate can be defined.

(ECP Rev) -Transmission- (B) shown in FIG. 6 is a diagram showing the status response timing in the ECP Rev mode. Based on this diagram,
Control during data transmission in the ECP Rev mode will be described.

After writing the data in the transmission buffer, when the status on the host side becomes idling, the data is set on the data bus, and after the time designated by the TP1 timer for generating the basic period (TP ≧ 0 us) has passed, Ptrcl
The k signal is set to L. Then, TP time has elapsed since the Ptrclk signal was set to L, and the HostBus of the host
When there is a response from the y signal, the Ptrclk signal is set to H and 1
The byte transfer ends. When transmitting a plurality of bytes, data is set after waiting for the HostBusy signal to become L, and the same processing is repeated thereafter. Thus, T
By controlling the P time, the maximum transmission rate can be defined.

The switching of the buffer units 102A and 102B is performed by the user's setting, and the handshake timing is automatically switched according to the setting. Table 2 is an example of setting the control value of the handshake timing according to the selection of the buffer units 101A and 101B and the operation mode of the facsimile.

[0039]

[Table 2]

As described above, according to the embodiment, two types of buffers, the totem pole type and the open collector type, are provided as buffers for driving the interface signal line, and it is necessary to switch the signal line at high speed, and the buffer on the receiver side is required. When the conditions are those considered for high-speed data transfer as described above, use a totem-pole type buffer and set the signal change interval short to speed up data transfer. You can

Further, when the totem pole type buffer is used, if the timing setting on the handshake is set so that the data transfer can be performed at high speed, the data transfer can be speeded up according to the communication system.

[Other Embodiments] In the above-described embodiment,
Although the buffer switching is manual switching by the user, if information can be obtained from the host, the buffers 101A and 101B may be automatically switched and handshake timing for data transfer may be set according to the information. good.

It is also possible to perform an appropriate data transfer test and automatically switch the buffers 101A and 101B and set handshake timing for data transfer according to the result.

The details of the above-mentioned data transfer test will be described below.

In a normal PC, the data bus output uses a totem pole buffer, and a data transfer test is performed to determine whether the control signal line is an open collector type buffer or a totem pole type buffer. It is also possible to do so.

This is because if the drive buffer of the data bus is a totem pole type, the type of the buffer that drives the control signal line is determined by determining the change delay of the control signal based on the signal change of the data bus. To do.

FIG. 7 is a diagram showing the handshake timing during the test execution in the compatibility mode. The host-side output signal nStrobe (SEND) is observed as nStrobe (RECIVE) due to the delay at the receiving end (the delay amount is shown as Td).

Although the data strobe is performed by the change of the nStrobe signal from the host side, the setting of the control register 210 is set to the rising edge of the strobe signal here. Then, the test data transfer is performed by the host P.
The data sent from C to the data bus is FFH, for example, and is changed to 00H after a data hold time (indicated by Th *) from the rising of the nStrobe signal. At this time, if Td time is smaller than Th, the strobed data becomes FFH, and T is smaller than Th.
If d time is large, the strobe data is 00H. Therefore, if the data hold time is gradually reduced and a data transfer test is performed, the signal delay time in the system can be estimated.

That is, when this value is larger than the predetermined first value (large delay amount of nStrobe signal).
The drive buffer type of the control line is determined to be an open collector, and when it is smaller than the second value set in advance, it is determined to be a totem pole type buffer. When the control signal sent from the PC side is judged to be an open collector type,
When it is judged that the receiver side is also set to receive the signal from the open collector output and it is judged to be the totem pole type, it is judged that the receiver side is also set to receive the signal from the totem pole output. I do.

Then, the buffer 101 on the facsimile side
Switching between A and B is automatically performed according to the above determination. Further, when the first and second values are different and a value between them is obtained as the delay value, the switching is automatically performed according to the determination result designated by the user in advance.

As described above, according to another embodiment, the buffer is automatically switched by the acquisition of the host information and the data transfer test, so that the receiver condition can be set without the user making complicated settings. It is possible to switch the buffers accordingly.

Even when the present invention is applied to a system composed of a plurality of devices (eg, host computer, interface device, reader, printer, etc.), a device composed of one device (eg, copier, facsimile). Device).

[0053]

As described above, according to the present invention,
High-speed data transfer is possible by selecting the desired external interface according to the receiver conditions of the connected partner device, and the convenience of the device and the user is improved by automatically selecting the desired external interface. It also becomes possible to improve.

[0054]

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a facsimile apparatus having a bidirectional Centro.i / f.

FIG. 2 is a block diagram showing a detailed configuration of a parallel port control unit shown in FIG.

FIG. 3 is a diagram showing a data transfer timing in a compatibility mode.

FIG. 4 is a diagram showing a data transfer timing in a nibble mode.

FIG. 5 is a diagram showing a data transfer timing in a byte mode.

FIG. 6 is a diagram showing a data transfer timing in an ECP mode.

FIG. 7 is a diagram showing a timing in a data transfer test.

[Explanation of symbols]

 101A buffer IC unit A 101B buffer IC unit B 102 parallel port control unit 103 reading unit 104 CODEC 105 NCU 106 modem 107 DMA control unit 108 image memory 109 main control unit 110 recording unit 111 operation unit BUFSEL buffer selection signal XPIFEN i / f bus Enable signal PIFDIR i / f bus direction designation signal HLDREQ bus use request signal XHLDACK bus use request acceptance signal DMAREQ1 DMA transfer request signal 1 XDMAACK1 DMA transfer acceptance signal 1 DMAREQ2 DMA transfer request signal 2 XDMAACK2 DMA transfer acceptance signal 2 LAST Final data transfer end Signal INTPIF interrupt request signal INTDKC interrupt request signal delay clock 201 reception control unit 202 transmission control unit 2 03 TPI timer 204 Status control unit 205 Interrupt control unit 206 Data buffer 207 DMA control unit 208 Mode generation unit 209 R / W control unit 210 Control register IFMOD Interface mode instruction signal R / W Read / write signal

Claims (8)

[Claims] 1. A method for controlling an external interface of a device having at least two external interfaces (i / f), comprising selecting a desired external i / f according to a receiver condition of a connected partner device, and selecting the desired external i / f. An external interface control method comprising the steps of performing data transfer via an external i / f. 2. The external interface control method according to claim 1, wherein in the selecting step, selection is automatically performed based on device information from the partner device. 3. The external interface control method according to claim 1, wherein in the selecting step, a predetermined transfer rate test is performed with the partner device and the result is automatically selected. 4. The external interface control method according to claim 1, wherein in the data transfer step, the handshake timing for data transfer is changed according to the selected external i / f. 5. A data communication device having at least two external interfaces (i / f), and selecting means for selecting a desired external i / f according to a receiver condition of a connected counterpart device, and the selection. And a communication unit that performs data communication via the external i / f selected by the unit. 6. The data communication apparatus according to claim 5, wherein the selection means automatically selects the device information from the other device. 7. The data communication apparatus according to claim 5, wherein the selecting means performs a predetermined transfer rate test with the counterpart device and automatically selects the result according to the result. 8. The communication means is a selected external i / f.
6. The data communication device according to claim 5, wherein the handshake timing for data transfer is changed by.