JPH09232332A - Semiconductor device - Google Patents

Abstract

(57) Abstract: An on-voltage is reduced at a low cost without increasing switching loss of an IGBT. A the n ^- inner surface layer of the drain region 4 p ⁺ base region 5 and p ^- and region 7 is formed, n ⁺ source region 6 is formed on the surface layer of these regions, p ^- region 7 The gate electrode 9 is formed on the surface through the gate insulating film 8,
Source electrode 11 is formed in contact with p ⁺ base region 5 and n ⁺ source region 6 via interlayer insulating film 12. After the source electrode 11 and the interlayer insulating film 12 are formed, proton irradiation is performed on the entire surface layer. The irradiation dose in this case is 1 × 10 ^12.
The irradiation depth is 1 to 10 μm at cm ⁻² or more. After irradiation 3
The low-resistance layer 12 is formed on the surface layer of the n ⁻ drain region by heat treatment at 50 ° C. or higher and making the lattice defects formed by irradiation with protons into shallow donors.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a vertical insulated gate bipolar transistor (IGBT).

2. Description of the Related Art FIG. 2 is a schematic view of a main part of a vertical IGBT.
You. n^-P inside the surface layer of the drain region 4⁺Base area
5 and p^-Areas 7 and are formed, and in the surface layer of these areas
n⁺P where the source region 6 is formed and the channel is formed
^-A gate electrode 9 is formed on the surface of the region 7 via a gate insulating film 8.
Is formed, and p is further formed through the interlayer insulating film 12.⁺base
Area and n⁺Source electrode 11 in contact with source region 6 is formed
Is done. n^-N on the other surface of the drain region 4⁺Buff
P across the layer 3⁺The collector layer 2 is formed and p ⁺this
The collector electrode 1 is formed on the surface of the contact layer 2. this
When the on-voltage of the IGBT is decomposed into each component, it is as follows.
Become. (1) p⁺Collector layer 2 and n⁺Diffusion charge between the buffer layers 3
Voltage drop due to (2) n^-Voltage drop in drain region 4. (3) p where a channel is formed^-Region 7 and this p^-region
N sandwiched between 7^-Junction type electrode formed in the drain region 4
Field effect transistor, so-called JFET voltage drop. (4) n that constitutes the JFET section^-Surface of drain region 4
Voltage drop due to storage layer. (5) p^-Voltage drop in the channel layer formed in region 7
under. (6) Contour at 1 part of collector electrode and 11 parts of source electrode
Voltage drop due to the electrical resistance. Of these voltage drops, the voltage drop of the JFET part of (3)
Is dominant. Therefore, to improve this voltage drop
First, n^-N on the surface layer of the drain region 4^-Drain region
Ion implantation of n-type impurity atoms of the same conductivity type as 4
Narrowing, heat treatment, shallow diffusion, n^-Drain region 4 table
Face part n⁺Layer. This allows the drain region
The spread of the depletion layer is suppressed, the JFET effect is reduced, and
Reducing the pressure drop is being done. Of course, n^-Dre
Increase the lifetime of the IN area 4 to reduce the voltage drop
This method increases switching loss compared to
It is possible to reduce the voltage drop without causing it.

However, in order to form the n ⁺ layer on the surface portion of the n ⁻ drain region 4, it is necessary to prevent n type impurity atoms from being introduced into the p ⁻ region 7 and the p ⁺ base region 5. However, a mask is required at the time of ion implantation, the number of steps for that is increased, and the manufacturing cost is increased. An object of the present invention is to solve the above problems and provide a semiconductor device in which the voltage drop of the JFET is reduced at a low cost without providing an n ⁺ layer on the surface of the n ⁻ drain region 4.

In order to achieve the above-mentioned object, a second region of the second conductivity type selectively formed inside the surface layer of the first region of the first conductivity type and the second region. Has a third region of the first conductivity type selectively formed in the surface layer of,
In a semiconductor device in which a gate electrode is formed on the surface of a second region sandwiched between a third region and a first region via an insulating film, light ions are present at least in the surface layer of the first region sandwiched between the second regions. After the fixed amount of irradiation, heat treatment is performed at a predetermined temperature to form a resistance layer having a resistance lower than the resistance of the first region in the surface layer of the first region. The light ions are protons and the irradiation dose is 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ^−2.
And the heat treatment temperature may be 350 ° C. to 600 ° C. Furthermore, it is effective that the depth of irradiation with the light ions is 5 μm to 50 μm from the surface of the first region, but preferably about 20 μm. The light ions are preferably protons or helium ions. It is known that when light ions such as protons and helium ions are irradiated into silicon, lattice defects are locally generated, and they act as a lifetime killer. Lattice defects can be generated at any depth by changing the accelerating voltage during irradiation.
When n-type silicon is irradiated with a predetermined dose of light ions and then heat-treated, the introduced lattice defects are shallow donors (in the case of proton irradiation, a donor having a shallow energy level) or deep donors (in the case of helium). Are formed and the resistance is locally reduced. Therefore, the above n
By irradiating the first region (drain region) of the shape with light ions, the depletion layer is less likely to expand by converting the surface layer into a donor, the effect of the JFET can be suppressed, and the on-voltage can be reduced. .

FIG. 1 is a diagram showing an embodiment of the present invention. In the following description, the first conductivity type is n-type and the second conductivity type is p-type. Inside the surface layer of the n ⁻ drain region 4 which is the first region, the p ⁺ base region 5 which is the second region
And p ⁻ region 7 (channel layer is formed on this surface layer)
And n ⁺ source region 6 which is a third region is formed in the surface layer of these regions, and gate electrode 9 is formed on the surface of p ⁻ region 7 via gate insulating film 8 formed of an oxide film or the like. Is formed. BPSG is formed on the gate electrode 9 (boron-doped phosphorus glass also serves as a passivation film).
Covered with the interlayer insulating film 12, such as, in the interlayer insulating film 12 is insulated from the gate electrode 9, p ⁺ base region 5 and n ⁺
Source electrode 4 is formed in contact with source region 6. n ^-
A p ⁺ collector layer 2 is formed on the other surface of drain region 4 with n ⁺ buffer layer 3 interposed therebetween, and collector electrode 1 is formed on the surface of p ⁺ collector layer 2. Further, the proton irradiation is performed after forming the source electrode 11 and the interlayer insulating film 12.
Perform on the entire surface layer. In this case, the irradiation dose is 1 × 10 ¹² cm
^-2 to 1 × 10 ¹⁴ cm ^-2 , with irradiation depth of 1 μm
The range is 10 μm, but preferably about several μm. After irradiation, the range of 350 ° C to 600 ° C (preferably 3
The low resistance layer 13 is formed in the surface layer of the n ⁻ drain region by heat treatment at a temperature of 50 ° C. to 450 ° C.) and making the lattice defects formed by irradiating the protons into shallow donors. Irradiation dose is 1 × 10 ¹² cm ^-2 or less and heat treatment temperature is 3
At 50 ° C. or lower, lattice defects formed by light ions do not become donors. Further, when the heat treatment temperature exceeds 600 ° C., the ratio of lattice defects that are annealed and crystallized increases, and as a result, the formation of donors weakens. When the heat treatment temperature for introducing the lifetime killer is higher than the heat treatment temperature after the proton irradiation, the step of introducing the lifetime killer is performed before the proton irradiation step, and when it is lower, the step is performed later. Usually, the lifetime killer with gold or platinum is introduced before proton irradiation because the heat treatment temperature is as high as about 800 ° C, and in the case of electron beam irradiation, the heat treatment temperature is about 300 ° C after proton irradiation. Done in. After introducing the lifetime killer, the collector electrode 1 is formed on the p ⁺ collector layer 2. Since the proton irradiation is performed over the entire surface, a mask required for forming the low resistance layer in the n ⁻ drain region 4 due to diffusion of phosphorus atoms or arsenic atoms is not necessary, and the manufacturing cost is reduced. In addition, the IGB can be obtained by forming a low-resistance layer by making a lattice defect formed by proton irradiation into a shallow donor and by forming a low-resistance layer by conventional diffusion.
The degree of reduction of the ON voltage of T was the same. Further, the same effect can be expected when helium ions are used as the light ions.

According to the present invention, light ions such as protons are irradiated to a semiconductor device having a MOS gate structure such as an IGBT without masking over the entire surface to form a low resistance layer in the n ^- drain region and a depletion layer. Makes it difficult to spread. By doing so, the JFET effect is suppressed, the on-voltage of the semiconductor device having the MOS gate structure is reduced, and the manufacturing cost is also reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an IGBT according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a conventional IGBT.

[Explanation of symbols]

1 collector electrode 2 p ⁺ collector layer 3 n ⁺ buffer layer 4 n ⁻ drain region 5 p ⁺ base region 6 n ⁺ source region 7 p ⁻ region (channel layer is formed on this surface layer) 8 gate insulating film 9 gate Electrode 11 Source electrode 12 Interlayer insulation film 13 Low resistance layer

Claims (4)

[Claims] 1. A second region of the second conductivity type selectively formed inside the surface layer of the first region of the first conductivity type and a first conductivity selectively formed on the surface layer of the second region. In a semiconductor device having a third region of a shape and a gate electrode formed on the surface of a second region sandwiched between the third region and the first region with an insulating film interposed between the first region sandwiched at least in the second region. The surface layer of the region is irradiated with a predetermined amount of light ions and then heat-treated at a predetermined temperature to form a resistance layer lower than the resistance of the first region in the surface layer of the first region. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the light ions are protons or helium ions. 3. The semiconductor device according to claim 1, wherein the depth of light ion irradiation is 1 μm to 10 μm from the surface of the first region. 4. The light ion is a proton and the irradiation dose is 1
2. The semiconductor device according to claim 1, wherein the temperature is × 10 ¹² cm ^-2 to 1 × 10 ¹⁴ cm ^-2 and the heat treatment temperature is 350 ° C to 600 ° C.