JPH09232632A - Semiconductor light emitting device and method of manufacturing the same - Google Patents
Semiconductor light emitting device and method of manufacturing the sameInfo
- Publication number
- JPH09232632A JPH09232632A JP34161296A JP34161296A JPH09232632A JP H09232632 A JPH09232632 A JP H09232632A JP 34161296 A JP34161296 A JP 34161296A JP 34161296 A JP34161296 A JP 34161296A JP H09232632 A JPH09232632 A JP H09232632A
- Authority
- JP
- Japan
- Prior art keywords
- type layer
- side electrode
- electrode
- emitting device
- light emitting
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、窒化ガリウム系化
合物半導体(Inx Gay Al1-x-y N:0≦x≦1,
0≦y≦1)からなる発光ダイオード、半導体レーザな
どの半導体発光素子、及びその製造方法に関する。The present invention relates to the gallium nitride compound semiconductor (In x Ga y Al 1- xy N: 0 ≦ x ≦ 1,
The present invention relates to a light emitting diode consisting of 0 ≦ y ≦ 1), a semiconductor light emitting device such as a semiconductor laser, and a manufacturing method thereof.
【0002】[0002]
【従来の技術】従来、この種の半導体素子としては、例
えば図11に示すようなものがあった。図11は、従来
の窒化ガリウム系化合物半導体発光素子の構造を示す断
面図である。2. Description of the Related Art Conventionally, as a semiconductor element of this type, there is one shown in FIG. 11, for example. FIG. 11 is a sectional view showing the structure of a conventional gallium nitride-based compound semiconductor light emitting device.
【0003】この半導体発光素子は、絶縁性のサファイ
ア基板11の上に、n型の窒化ガリウム系化合物半導体
層(以下、単にn型層という)112と、p型の窒化ガ
リウム系化合物半導体層(以下、単にp型層という)1
13とを積層したp−n接合ウエハに対し、p型層11
3の一部を選択的にエッチングしてn型層112を露出
させ、p型層113に対してp側電極114を、n型層
112に対してはp側電極114と電極材料の異なるn
型電極115を形成させることにより、p−n接合型の
発光素子が実現されている(Applied Phys
ics Letters,vol.64,pp.168
7−1689,March 28,1994)。In this semiconductor light emitting device, an n-type gallium nitride compound semiconductor layer (hereinafter simply referred to as an n-type layer) 112 and a p-type gallium nitride compound semiconductor layer (on an insulating sapphire substrate 11). Hereinafter referred to simply as the p-type layer) 1
The p-type layer 11 is formed on the pn junction wafer in which
3 is selectively etched to expose the n-type layer 112, and the p-side electrode 114 is different from the p-type layer 113 and the p-side electrode 114 is different from the p-side electrode 114 in the n-type layer 112.
By forming the mold electrode 115, a pn junction type light emitting device is realized (Applied Phys).
ics Letters, vol. 64, pp. 168
7-1689, March 28, 1994).
【0004】なお、p側及びn側電極が同一面側に形成
されているのは、窒化ガリウム系化合物半導体層が絶縁
性のサファイア基板上に形成されるためであり、この材
料系の半導体発光素子に特徴的である。The p-side and n-side electrodes are formed on the same surface because the gallium nitride-based compound semiconductor layer is formed on an insulating sapphire substrate. It is characteristic of the device.
【0005】図12(a)〜(d)及び図13(e),
(f)は、上記図11に示した半導体発光素子の製造工
程を示す断面図である。12 (a) to 12 (d) and FIG. 13 (e),
11F is a sectional view showing a manufacturing process of the semiconductor light emitting device shown in FIG. 11.
【0006】まず、図12(a)に示すように、絶縁性
のサファイア基板111の上に、n−GaNからなるn
型層112とp−GaNからなるp型層113とを積層
したp−n接合ウエハを用意する。次に、そのp−n接
合ウエハに対し、p型層113の一部より選択的にエッ
チングしてn型層112を露出させる(図12
(b))。First, as shown in FIG. 12A, n made of n-GaN is formed on an insulating sapphire substrate 111.
A pn junction wafer in which the mold layer 112 and the p-type layer 113 made of p-GaN are stacked is prepared. Next, the pn junction wafer is selectively etched from a part of the p-type layer 113 to expose the n-type layer 112 (FIG. 12).
(B)).
【0007】その後、リフトオフ法によって前記n側電
極115を形成すべく、前記ウエハ表面にマスクパター
ン121を形成し、さらにそのマスクパターン121の
表面にn側の電極として適したTi/Al層115aを
真空蒸着法により形成する(図12(c))。そして、
マスクパターン121を除去すれば、図12(d)に示
すようにn型層112の表面上にn側電極115を得
る。Thereafter, in order to form the n-side electrode 115 by a lift-off method, a mask pattern 121 is formed on the wafer surface, and a Ti / Al layer 115a suitable as an n-side electrode is formed on the surface of the mask pattern 121. It is formed by the vacuum evaporation method (FIG. 12C). And
When the mask pattern 121 is removed, an n-side electrode 115 is obtained on the surface of the n-type layer 112 as shown in FIG.
【0008】さらに、同様にリフトオフ法によって前記
p側電極114を形成すべく、n側電極115の形成さ
れた前記ウエハ表面にマスクパターン122を形成し、
そのマスクパターン122の表面にp側の電極として適
したNi/Au層114aを蒸着形成する(図12
(e))。そして、マスクパターン122を除去すれ
ば、図12(f)に示すように、上記図11に示す電極
構造の半導体発光素子が得られる。Further, a mask pattern 122 is formed on the surface of the wafer on which the n-side electrode 115 is formed in order to form the p-side electrode 114 by the lift-off method.
A Ni / Au layer 114a suitable for a p-side electrode is formed on the surface of the mask pattern 122 by vapor deposition (FIG. 12).
(E)). Then, by removing the mask pattern 122, the semiconductor light emitting device having the electrode structure shown in FIG. 11 is obtained as shown in FIG.
【0009】上述の如く、従来の半導体発光素子では、
p側及びn側の電極114,115をそれぞれ異なる電
極材料で形成し、これによって良好なオーミック特性を
得ることにより、素子の動作電圧を低減し、過剰な発熱
による特性の劣化を防ぐようにしていた。As described above, in the conventional semiconductor light emitting device,
The p-side and n-side electrodes 114 and 115 are formed of different electrode materials, respectively, and thereby good ohmic characteristics are obtained, thereby reducing the operating voltage of the element and preventing deterioration of characteristics due to excessive heat generation. It was
【0010】[0010]
【発明が解決しようとする課題】しかしながら、このよ
うな異なる電極材料からなる電極構造を形成するには、
上記したように電極金属の蒸着やパターン形成など複数
回行うことが必要となり、製造工程が長く複雑になる。
そのため、製造プロセスに時間がかかるばかりか、製造
時に初期不良や長期通電などによる劣化が発生し、良好
な素子特性が得られる歩留を悪化させるという問題があ
った。However, in order to form such an electrode structure made of different electrode materials,
As described above, it is necessary to perform the vapor deposition of the electrode metal and the pattern formation a plurality of times, which makes the manufacturing process long and complicated.
Therefore, there is a problem that not only the manufacturing process takes a long time, but also an initial defect or deterioration due to long-term energization occurs at the time of manufacturing, which deteriorates the yield for obtaining good element characteristics.
【0011】本発明は、上述の如き従来の問題点を解決
するためになされたもので、その目的は、良好な素子特
性を得ることができる半導体発光素子を提供することで
ある。またその他の目的は、電極の形成工程を簡素化し
て、製造工程の短縮を可能にした半導体発光素子の製造
方法を提供することである。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor light emitting device capable of obtaining good device characteristics. Another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device, which simplifies the process of forming electrodes and shortens the manufacturing process.
【0012】[0012]
【課題を解決するための手段】上記目的を達成するため
に、第1の発明である半導体発光素子の特徴は、基板の
同一面側に形成され窒化ガリウム系化合物半導体からな
るp型層及びn型層と、前記p型層及び前記n型層上に
それぞれ形成されたp側電極及びn側電極とを備えた半
導体発光素子において、前記p側電極と前記n側電極
は、同一の金属単体または合金、もしくはそれらからな
る層構造で構成され且つ同一工程で形成された電極とし
たことにある。In order to achieve the above object, the semiconductor light emitting device of the first invention is characterized in that a p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor are formed on the same surface side of a substrate. In a semiconductor light emitting device including a mold layer and a p-side electrode and an n-side electrode formed on the p-type layer and the n-type layer, respectively, the p-side electrode and the n-side electrode are made of the same metal simple substance. Alternatively, the electrodes are made of an alloy or a layered structure made of them and are formed in the same step.
【0013】この第1の発明である半導体発光素子によ
れば、p側及びn側電極の電極材料として同一の材料を
使用するため、p側及びn側電極を同一条件で同時に形
成させることができる。このようにp側及びn側電極を
同時に一括して形成しても素子特性に悪影響はなく、良
好な特性を得ることができる。According to the semiconductor light emitting device of the first aspect of the present invention, since the same material is used for the p-side and n-side electrodes, the p-side and n-side electrodes can be formed simultaneously under the same conditions. it can. Thus, even if the p-side electrode and the n-side electrode are simultaneously formed at the same time, the device characteristics are not adversely affected and good characteristics can be obtained.
【0014】第2の発明である半導体発光素子の特徴
は、上記第1の発明において、前記p側電極と前記n側
電極は、少なくともTiとAuとが積層されてなること
にある。A feature of the semiconductor light emitting element of the second invention is that in the first invention, the p-side electrode and the n-side electrode are formed by stacking at least Ti and Au.
【0015】この第2の発明である半導体発光素子によ
れば、良好なオーミック特性を得ることができる。According to the semiconductor light emitting device of the second invention, good ohmic characteristics can be obtained.
【0016】第3の発明である半導体発光素子の特徴
は、上記第1の発明において、前記p側電極と前記n側
電極は、少なくともNiとAuとが積層されてなること
にある。A feature of the semiconductor light emitting element of the third invention is that in the first invention, the p-side electrode and the n-side electrode are formed by stacking at least Ni and Au.
【0017】この第3の発明である半導体発光素子によ
れば、良好なオーミック特性を得ることができる。According to the semiconductor light emitting device of the third invention, good ohmic characteristics can be obtained.
【0018】第4の発明である半導体発光素子の特徴
は、上記第1乃至第3の発明において、前記p側電極及
び前記n側電極がフリップチップ方式で第1及び第2の
外部リードにそれぞれ接続され、フェースダウンで前記
基板の裏面側より外部へ光を取り出すように構成された
ことにある。The semiconductor light emitting device according to the fourth invention is characterized in that, in the first to third inventions, the p-side electrode and the n-side electrode are respectively flip-chip type to the first and second external leads. It is configured to be connected and to extract light from the back side of the substrate to the outside with the face down.
【0019】この第4の発明によれば、n側電極とp側
電極に同一の電極を用いているので、均質な反射特性が
得られる。According to the fourth aspect of the invention, since the same electrode is used for the n-side electrode and the p-side electrode, uniform reflection characteristics can be obtained.
【0020】第5の発明である半導体発光素子の特徴
は、基板の同一面側に形成され窒化ガリウム系化合物半
導体からなるp型層及びn型層と、前記p型層及び前記
n型層上にそれぞれ形成されたp側電極及びn側電極と
を備えた半導体発光素子において、前記p側電極と前記
n側電極は、同一の導電性材料の単体または複合体、も
しくはそれらからなる層構造で構成され且つ同一工程で
形成された透光性の電極としたことにある。A fifth feature of the semiconductor light emitting device is that the p-type layer and the n-type layer are formed on the same surface of the substrate and are made of a gallium nitride-based compound semiconductor, and the p-type layer and the n-type layer are formed on the p-type layer and the n-type layer. In a semiconductor light-emitting device having a p-side electrode and an n-side electrode formed respectively, the p-side electrode and the n-side electrode are simple substances or composites of the same conductive material, or a layered structure made of them. That is, the transparent electrode is formed and formed in the same step.
【0021】この第5の発明によれば、p型電極及びn
側電極を透光性の電極にしているので、上記第1乃至第
3の発明に比べて光をより有効に取り出すことができ
る。特に、n側電極をも透光性にしていることにより、
裏面からの反射光をより有効に取り出すことができる。According to the fifth aspect of the invention, the p-type electrode and the n-type
Since the side electrode is a translucent electrode, it is possible to extract light more effectively than in the first to third inventions. In particular, by making the n-side electrode also transparent,
The reflected light from the back surface can be extracted more effectively.
【0022】第6の発明である半導体発光素子の製造方
法の特徴は、基板の同一面側に窒化ガリウム系化合物半
導体からなるp型層とn型層を形成し、前記p型層とn
型層の全面または一部に、同一の金属単体または合金、
もしくはそれらからなる層構造で構成される電極を同時
に形成して、それぞれp側電極及びn側電極とすること
にある。A sixth aspect of the method of manufacturing a semiconductor light emitting device is that a p-type layer and an n-type layer made of a gallium nitride compound semiconductor are formed on the same surface side of a substrate, and the p-type layer and the n-type layer are formed.
The same metal element or alloy, on all or part of the mold layer,
Alternatively, an electrode having a layered structure composed of them is simultaneously formed to form a p-side electrode and an n-side electrode, respectively.
【0023】この第6の発明によれば、上記第1乃至第
3の発明と同等の半導体発光素子を製造するに際して、
電極の形成工程が簡素化し、製造工程の短縮を図ること
ができる。According to the sixth aspect of the invention, when manufacturing a semiconductor light emitting device equivalent to the first to third aspects,
The electrode forming process can be simplified and the manufacturing process can be shortened.
【0024】第7の発明である半導体発光素子の製造方
法の特徴は、基板の同一面側に窒化ガリウム系化合物半
導体からなるp型層とn型層を形成し、前記p型層とn
型層の全面または一部に、同一の導電性材料の単体また
は複合体、もしくはそれらからなる層構造で構成される
透光性の電極を同時に形成して、それぞれp側電極及び
n側電極とすることにある。A feature of the method for manufacturing a semiconductor light emitting device according to the seventh invention is that a p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor are formed on the same surface side of a substrate, and the p-type layer and the n-type layer are formed.
A transparent electrode composed of a single or composite of the same conductive material, or a layered structure composed of the same is simultaneously formed on the entire surface or a part of the mold layer to form a p-side electrode and an n-side electrode, respectively. To do.
【0025】この第7の発明によれば、上記第5の発明
と同等の半導体発光素子を製造するに際して、電極の形
成工程が簡素化し、製造工程の短縮を図ることができ
る。According to the seventh aspect of the invention, when manufacturing a semiconductor light emitting device equivalent to the fifth aspect of the invention, the electrode forming process can be simplified and the manufacturing process can be shortened.
【0026】[0026]
【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。図1は、本発明の第1実施形態に係
る半導体発光素子の断面構造図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional structural view of a semiconductor light emitting device according to a first embodiment of the present invention.
【0027】この半導体発光素子は、絶縁性のサファイ
ア基板11上に窒化ガリウム系化合物半導体からなるn
型層12とp型層13とを積層したp−n接合ウエハに
おいて、前記p型層13及びn型層12の表面上には、
同一の金属からなるp側電極14及びn側電極15がそ
れぞれ形成されている。In this semiconductor light emitting device, n made of a gallium nitride compound semiconductor is formed on an insulating sapphire substrate 11.
In a pn junction wafer in which the mold layer 12 and the p-type layer 13 are laminated, on the surface of the p-type layer 13 and the n-type layer 12,
A p-side electrode 14 and an n-side electrode 15 made of the same metal are formed, respectively.
【0028】ここで、n側電極15は、従来と同様に、
前記p−n接合ウエハのp型層13の一部より選択的に
エッチングしてn型層12を露出させることにより、n
型層12の表面上に形成されている。Here, the n-side electrode 15 is, as in the conventional case,
By selectively etching a part of the p-type layer 13 of the pn junction wafer to expose the n-type layer 12,
It is formed on the surface of the mold layer 12.
【0029】前記p側電極14及びn側電極15の電極
材料としては、p側及びn側共に、より良好なオーミッ
ク特性を得るために、本実施形態では、Ni(ニッケ
ル)とTi(チタン)とAu(金)を積層した合金を用
いている。但し、この電極材料としては、Au、Pd
(パラジュウム)、Ti、Pt(白金)、Mo(モリブ
デン)、Cr(クロム)、Al(アルミニューム)、C
o(コバルト)、Rh(ロジューム)、Ir(イリジュ
ーム)、Mn(マンガン)、V(バナジューム)、Sc
(スカンジューム)、Mg(マグネシューム)、Zr
(ジルコニューム)などの金属単体やこれらの金属より
構成される合金、さらにはこれらの金属や合金からなる
層構造としてもよい。例えば、NiとAuを積層した合
金、またはTiとAuを鏡層した合金であっても、良好
なオーミック特性を得ることができる。In order to obtain better ohmic characteristics on both the p-side and the n-side, the electrode materials for the p-side electrode 14 and the n-side electrode 15 are Ni (nickel) and Ti (titanium) in this embodiment. And an alloy in which Au (gold) is laminated is used. However, as the electrode material, Au, Pd
(Paradium), Ti, Pt (platinum), Mo (molybdenum), Cr (chromium), Al (aluminum), C
o (Cobalt), Rh (Rhodium), Ir (Iridium), Mn (Manganese), V (Vanadium), Sc
(Scandium), Mg (magnesium), Zr
A single metal such as (zirconium), an alloy composed of these metals, or a layered structure composed of these metals or alloys may be used. For example, good ohmic characteristics can be obtained even with an alloy in which Ni and Au are laminated or an alloy in which Ti and Au are mirror layers.
【0030】上記構造の半導体発光素子では、p側電極
14とn側電極15間に所定の電圧を与えると、p側電
極14側からの正孔とn側電極15側からの電子が、n
型層12とp型層13との界面付近で再結合する結果、
発光する。In the semiconductor light emitting device having the above structure, when a predetermined voltage is applied between the p-side electrode 14 and the n-side electrode 15, holes from the p-side electrode 14 side and electrons from the n-side electrode 15 side are n
As a result of recombination near the interface between the mold layer 12 and the p-type layer 13,
It emits light.
【0031】図2(a)〜(d)は、図1に示した半導
体発光素子の製造工程を示す断面図である。2A to 2D are cross-sectional views showing the manufacturing steps of the semiconductor light emitting device shown in FIG.
【0032】まず、同図(a)に示すように、絶縁性の
サファイア基板11の上に、n−GaNからなるn型層
12とp−GaNからなるp型層13とを積層したp−
n接合ウエハを有機金属気相成長法などを用いることに
より用意する。次に、そのp−n接合ウエハに対し、従
来と同様に、p型層13の一部より選択的にエッチング
してn型層12を露出させる(図2(b))。First, as shown in FIG. 1A, a p-type is formed by laminating an n-type layer 12 made of n-GaN and a p-type layer 13 made of p-GaN on an insulating sapphire substrate 11.
An n-junction wafer is prepared by using a metal organic chemical vapor deposition method or the like. Next, the pn junction wafer is selectively etched from a part of the p-type layer 13 to expose the n-type layer 12 as in the conventional case (FIG. 2B).
【0033】その後、1回のリフトオフによって同時に
p側電極14及びn側電極15を形成すべく、前記ウエ
ハ表面にレジストを塗布してマスクパターン21を形成
し、さらにそのマスクパターン21の表面に、真空蒸着
法によりNiとTiとAuを順次積層して金属層22を
形成する(図2(c))。Thereafter, in order to simultaneously form the p-side electrode 14 and the n-side electrode 15 by one lift-off, a resist is applied to the wafer surface to form a mask pattern 21, and the mask pattern 21 is further formed on the surface thereof. A metal layer 22 is formed by sequentially stacking Ni, Ti, and Au by a vacuum vapor deposition method (FIG. 2C).
【0034】そして、マスクパターン21を除去すれ
ば、図2(d)に示すように、上記図1に示す電極構造
の半導体発光素子が得られる。By removing the mask pattern 21, the semiconductor light emitting device having the electrode structure shown in FIG. 1 is obtained as shown in FIG.
【0035】ここで、p側電極14及びn側電極15を
構成するNi,Ti,Auの厚さをそれぞれ0.02μ
m,0.02μm,0.5μmとしたとき、本実施形態
の20mAにおける動作電圧は3.8Vとなる。この値
は、上記従来の半導体発光素子(図11)の動作電圧
(3.6V)とほぼ同等のものが本実施形態による電極
構造により得られていることを示すものである。Here, the thicknesses of Ni, Ti, and Au forming the p-side electrode 14 and the n-side electrode 15 are each 0.02 μm.
When m, 0.02 μm, and 0.5 μm, the operating voltage at 20 mA of this embodiment is 3.8 V. This value shows that an operating voltage (3.6 V) almost equal to that of the conventional semiconductor light emitting device (FIG. 11) is obtained by the electrode structure according to the present embodiment.
【0036】低い動作電圧を得るには、図3のグラフに
示すように、前記Ni,Ti,Auのうち、Ni,Ti
の厚さを0.001から0.5μmまでの範囲にするこ
とが望ましい。それは、この厚さを0.001μmより
薄くすると密着性が悪くなって電極が剥がれやすくな
り、また、0.5μmよりも厚くするとp側またはn側
のコンタクト抵抗が高くなり動作電圧が高くなるからで
ある。さらに望ましい範囲としては0.005〜0.1
μmにすることで動作電圧が低い実用的な素子を得るこ
とができる。In order to obtain a low operating voltage, as shown in the graph of FIG. 3, among Ni, Ti and Au, Ni and Ti are selected.
It is desirable that the thickness of the film be in the range of 0.001 to 0.5 μm. This is because if the thickness is less than 0.001 μm, the adhesion is poor and the electrode is easily peeled off, and if it is more than 0.5 μm, the p-side or n-side contact resistance is high and the operating voltage is high. Is. A more desirable range is 0.005 to 0.1
By setting the thickness to μm, a practical device having a low operating voltage can be obtained.
【0037】上記の如く、本実施形態では、p側電極1
4及びn側電極15の電極材料として同一の材料を使用
したので、p側電極14及びn側電極15を同一条件で
同時に被着させることができる。このように同時に形成
しても、素子特性に悪影響はなく、良好な特性を得るこ
とができる。As described above, in this embodiment, the p-side electrode 1
Since the same material is used for the 4 and n-side electrodes 15, the p-side electrode 14 and the n-side electrode 15 can be simultaneously deposited under the same conditions. Even if they are simultaneously formed in this way, the device characteristics are not adversely affected and good characteristics can be obtained.
【0038】従って、素子形成プロセスが大幅に簡素化
されて製造時間か短縮化し、しかも複雑な製造プロセス
が不要となることで、初期不良の発生や長期通電による
劣化の発生を抑制することができる。Therefore, the element forming process is greatly simplified, the manufacturing time is shortened, and a complicated manufacturing process is not required, so that the occurrence of initial defects and the deterioration due to long-term energization can be suppressed. .
【0039】図4は、本発明の第2実施形態に係る半導
体発光素子(シングルヘテロ構造)の断面構造図であ
る。FIG. 4 is a sectional structural view of a semiconductor light emitting device (single hetero structure) according to the second embodiment of the present invention.
【0040】この半導体発光素子は、絶縁性のサファイ
ア基板31の上に、n−GaNからなるn型層32と、
p−GaAlNからなるp型層33、p−GaNからな
るp型層34とを積層したシングルヘテロ構造のウエハ
に対し、p型層34の一部より選択的にエッチングして
n型層32を露出させ、p型層34に対してはp側電極
35を、n型層32に対しては前記p側電極35と同一
の電極材料からなるn型電極36を形成している。In this semiconductor light emitting device, an n-type layer 32 made of n-GaN is provided on an insulating sapphire substrate 31.
A single heterostructure wafer in which a p-type layer 33 made of p-GaAlN and a p-type layer 34 made of p-GaN are laminated is selectively etched from a part of the p-type layer 34 to form the n-type layer 32. A p-side electrode 35 is formed for the p-type layer 34 and an n-type electrode 36 made of the same electrode material as the p-side electrode 35 is formed for the n-type layer 32 by exposing.
【0041】前記p側電極35及びn側電極36の電極
材料としては、上記第1実施形態と同様に、例えばNi
とTiとAuを積層した合金を用い、この半導体発光素
子の製造方法は、使用するウエハがシングルヘテロ構造
であることのみが異なり、上記図2に示したものと同様
である。The electrode material of the p-side electrode 35 and the n-side electrode 36 is, for example, Ni as in the first embodiment.
The method of manufacturing this semiconductor light emitting device using an alloy in which Ti and Au are laminated is the same as that shown in FIG. 2 above, except that the wafer used has a single hetero structure.
【0042】本実施形態においても、上記第1実施形態
と同様の効果が得られる。Also in this embodiment, the same effect as that of the first embodiment can be obtained.
【0043】図5は、本発明の第3実施形態に係る半導
体発光素子(ダブルヘテロ構造)の断面構造図である。FIG. 5 is a sectional structural view of a semiconductor light emitting device (double hetero structure) according to the third embodiment of the present invention.
【0044】この半導体発光素子は、絶縁性のサファイ
ア基板41の上に、n−GaNからなるn型層42と、
窒化ガリウム系化合物半導体からなる活性層43と、p
−GaNからなるp型層44とを積層したダブルヘテロ
構造のウエハに対し、p型層44の一部より選択的にエ
ッチングしてn型層42を露出させ、p型層44に対し
てはp側電極45を、n型層42に対しては前記p側電
極45と同一の電極材料からなるn型電極46を形成し
ている。This semiconductor light emitting device comprises an n-type layer 42 made of n-GaN on an insulating sapphire substrate 41,
An active layer 43 made of a gallium nitride-based compound semiconductor;
A double heterostructure wafer in which a p-type layer 44 made of -GaN is laminated is selectively etched from a part of the p-type layer 44 to expose the n-type layer 42. For the p-side electrode 45, an n-type electrode 46 made of the same electrode material as the p-side electrode 45 is formed for the n-type layer 42.
【0045】前記p側電極45及びn側電極46の電極
材料としては、上記第1実施形態と同様に、例えばNi
とTiとAuを積層した合金を用い、この半導体発光素
子の製造方法は、使用するウエハがダブルヘテロ構造で
あることのみが異なり、上記図2に示したものと同様で
ある。The electrode material of the p-side electrode 45 and the n-side electrode 46 is, for example, Ni as in the first embodiment.
The method of manufacturing this semiconductor light emitting device using an alloy in which Ti and Au are laminated is the same as that shown in FIG. 2, except that the wafer used has a double hetero structure.
【0046】本実施形態においても、上記第1実施形態
と同様の効果が得られる。Also in this embodiment, the same effect as in the first embodiment can be obtained.
【0047】図6は、本発明の第4実施形態に係る半導
体発光素子(半導体レーザ)の断面構造図である。FIG. 6 is a sectional structural view of a semiconductor light emitting device (semiconductor laser) according to the fourth embodiment of the present invention.
【0048】この半導体発光素子は、半導体レーザとし
て構成され、絶縁性のサファイア基板51の上に、n−
GaNからなるn型層52と、窒化ガリウム系化合物半
導体からなる活性層53と、p−GaAlNからなるp
型層54と、n型領域55が部分的に形成されたp型層
56とを積層したウエハに対し、p型層56の一部より
選択的にエッチングしてn型層52を露出させ、p型層
56に対してはp側電極57を、n型層52に対しては
前記p側電極57と同一の電極材料からなるn型電極5
8を形成している。This semiconductor light emitting device is constructed as a semiconductor laser, and n-type is formed on an insulating sapphire substrate 51.
An n-type layer 52 made of GaN, an active layer 53 made of a gallium nitride-based compound semiconductor, and a p layer made of p-GaAlN.
With respect to the wafer in which the mold layer 54 and the p-type layer 56 in which the n-type region 55 is partially formed are stacked, the n-type layer 52 is exposed by selectively etching from a part of the p-type layer 56, A p-side electrode 57 for the p-type layer 56 and an n-type electrode 5 made of the same electrode material as the p-side electrode 57 for the n-type layer 52.
8 are formed.
【0049】前記p側電極57及びn側電極58の電極
材料としては、上記第1実施形態と同様に、例えばNi
とTiとAuを積層した合金を用い、この半導体発光素
子の製造方法は、使用するウエハの構造のみが異なり、
上記図2に示したものと同様である。The electrode material for the p-side electrode 57 and the n-side electrode 58 is, for example, Ni as in the first embodiment.
Using a laminated alloy of Ti and Au, the manufacturing method of this semiconductor light emitting device is different only in the structure of the wafer used,
It is similar to that shown in FIG.
【0050】本実施形態においても、上記第1実施形態
と同様の効果が得られる。Also in this embodiment, the same effect as that of the first embodiment can be obtained.
【0051】図7は、本発明の第5実施形態に係る半導
体発光素子(ダブルヘテロ構造)の断面構造図である。FIG. 7 is a sectional structural view of a semiconductor light emitting device (double hetero structure) according to the fifth embodiment of the present invention.
【0052】この半導体発光素子は、絶縁性のサファイ
ア基板61上に、n−InGaAlN層62と、InG
aAlNからなる活性層63と、p−InGaAlN層
64とを積層したダブルヘテロ構造のウエハに対し、p
型層64の一部より選択的にエッチングしてn型層62
を露出させ、p型層64に対してはp側電極65を、n
型層62に対しては前記p側電極65と同一の電極材料
からなるn型電極66をそれぞれ形成している。In this semiconductor light emitting device, an n-InGaAlN layer 62 and InG are formed on an insulating sapphire substrate 61.
For a double heterostructure wafer in which an active layer 63 made of aAlN and a p-InGaAlN layer 64 are laminated,
The n-type layer 62 is selectively etched from a part of the mold layer 64.
To expose the p-side electrode 65 to the p-type layer 64,
An n-type electrode 66 made of the same electrode material as the p-side electrode 65 is formed on the mold layer 62.
【0053】ここで、p側電極65及びn型電極66
は、活性層63からの発光を透過する透光性の電極で構
成されている。この透光性の電極材料としては、例えば
厚さが0.001μmから0.05μm程度の金属単体
やこれらの金属より構成される合金、さらにはこれらの
金属や合金からなる層構造、あるいは酸化インジューム
錫(ITO)等の透光性の導電性酸化物膜などが用いら
れる。Here, the p-side electrode 65 and the n-type electrode 66
Is composed of a translucent electrode that transmits the light emitted from the active layer 63. The transparent electrode material is, for example, a simple metal having a thickness of about 0.001 μm to 0.05 μm, an alloy composed of these metals, a layer structure made of these metals or an alloy, or an oxide oxide. A transparent conductive oxide film such as jum tin (ITO) is used.
【0054】また、p型層64上面からp側電極65上
面の一部に積重する形でp側台座電極67が設けられ、
さらにn型層62上面からn側電極66上面の一部に積
重する形でn側台座電極68が設けられている。p側台
座電極67及びn側台座電極68の電極材料としては、
例えばTiとAuの積層膜あるいはNiとAuの積層膜
が用いられている。Further, a p-side pedestal electrode 67 is provided so as to be stacked from the upper surface of the p-type layer 64 to a part of the upper surface of the p-side electrode 65,
Further, an n-side pedestal electrode 68 is provided so as to be stacked from the upper surface of the n-type layer 62 to a part of the upper surface of the n-side electrode 66. As the electrode material of the p-side pedestal electrode 67 and the n-side pedestal electrode 68,
For example, a laminated film of Ti and Au or a laminated film of Ni and Au is used.
【0055】上述の本実施形態の半導体発光素子(ダブ
ルヘテロ構造)の平面構造図を図8(a),(b)に示
す。p側台座電極67及びn側台座電極68が、同図
(a)の例では矩形チップの横中央線上に配置されてい
るのに対し、同図(b)の例では矩形チップの右隅部に
寄った位置に配置されている。図8(b)の例では、同
図(a)の配置例に比べて、特にn側台座電極68に対
してワイヤボンディングする際に、ボンディングツール
用の領域が十分確保されているので、支障なく容易にボ
ンディングを行うことができる。8A and 8B are plan structural views of the semiconductor light emitting device (double heterostructure) of the present embodiment described above. While the p-side pedestal electrode 67 and the n-side pedestal electrode 68 are arranged on the horizontal center line of the rectangular chip in the example of FIG. 7A, the right corner of the rectangular chip is arranged in the example of FIG. It is located closer to. In the example of FIG. 8B, compared with the arrangement example of FIG. 8A, a sufficient area for the bonding tool is secured especially when wire bonding is performed on the n-side pedestal electrode 68, which causes a problem. It is possible to easily perform bonding without using.
【0056】この半導体発光素子の製造方法は、上記し
たダブルヘテロ構造のウエハを用いて上記第1実施形態
に示したものと同様の方法でp型層64及びn型層62
の上面にそれぞれ透光性のp側電極65及びn型電極6
6を形成し、さらに、前記p側台座電極67とn側台座
電極68を例えば前述の同一材料を用いて真空蒸着法に
より同時に形成する。The method of manufacturing this semiconductor light emitting device is the same method as that shown in the first embodiment using the above-mentioned double heterostructure wafer, and is the p-type layer 64 and the n-type layer 62.
On the upper surface of each of the transparent p-side electrode 65 and n-type electrode 6
6 is formed, and the p-side pedestal electrode 67 and the n-side pedestal electrode 68 are simultaneously formed by the vacuum deposition method using the same material as described above, for example.
【0057】本実施形態においては、上記第1実施形態
と同様の効果を得ることができるほか、p型電極65及
びn側電極66を透光性にしているので、上記第1〜第
4実施形態に比べて活性層からの発光をより有効に取り
出すことができる。特に、n側電極66をも透光性にし
ていることにより、裏面からの反射光をより有効に取り
出すことができ、チップ外部への光取り出し効率を一層
向上させることが可能になる。In this embodiment, the same effect as that of the first embodiment can be obtained, and the p-type electrode 65 and the n-side electrode 66 are made transparent, so that the first to fourth embodiments are performed. Light emitted from the active layer can be more effectively extracted as compared with the form. In particular, since the n-side electrode 66 is also transparent, the reflected light from the back surface can be more effectively extracted, and the light extraction efficiency to the outside of the chip can be further improved.
【0058】なお、本実施形態では、ダブルヘテロ構造
を例にとって、p側電極及びn型電極を透光性の電極で
構成する発明を説明したが、ダブルヘテロ構造に限ら
ず、シングルヘテロ構造やホモ構造、あるいは半導体レ
ーザであっても本発明の適用は可能である。In the present embodiment, the invention in which the p-side electrode and the n-type electrode are composed of translucent electrodes has been described by taking the double hetero structure as an example. However, the invention is not limited to the double hetero structure and a single hetero structure or The present invention can be applied to a homostructure or a semiconductor laser.
【0059】以下に、上記各実施形態で示された半導体
発光素子の実装例を図9及び図10を用いて説明する。
なお、半導体発光素子はダイシングで個々のチップに分
割してあるものとする。An example of mounting the semiconductor light emitting device shown in each of the above embodiments will be described below with reference to FIGS. 9 and 10.
Note that the semiconductor light emitting element is divided into individual chips by dicing.
【0060】図9は、本発明の半導体発光素子を実装し
たLED製品の断面構造図であり、チップ主面側から外
部に光を取り出すタイプを示したものである。なお、同
図9では、上記第5実施形態(図7)で説明したダブル
ヘテロ構造のLEDチップを実装した例を示している
が、他の第1〜第4実施形態に示すような構造のLED
チップであっても同様に説明される。FIG. 9 is a sectional structural view of an LED product on which the semiconductor light emitting element of the present invention is mounted, showing a type in which light is extracted from the main surface side of the chip to the outside. Note that FIG. 9 shows an example in which the LED chip having the double hetero structure described in the fifth embodiment (FIG. 7) is mounted, but the structure as shown in the other first to fourth embodiments is shown. LED
The same applies to chips.
【0061】図9において、まず、上記第5実施形態の
LEDチップ70をリードフレーム71のチップ搭載部
に固着しておく。そして、チップ70の前記n側台座電
極68と該リードフレーム71とをボンディングワイヤ
(例えばAu線)72を介して接合すると共に、p側台
座電極67とリードフレーム73をボンディングワイヤ
(例えばAu線)74を介して接合する。In FIG. 9, first, the LED chip 70 of the fifth embodiment is fixed to the chip mounting portion of the lead frame 71. Then, the n-side pedestal electrode 68 of the chip 70 and the lead frame 71 are bonded via a bonding wire (for example, Au wire) 72, and the p-side pedestal electrode 67 and the lead frame 73 are bonded by bonding wire (for example, Au wire). It joins via 74.
【0062】その後は、上記状態のLEDチップ70を
金型にセットして、加熱溶融された遮光性樹脂を金型ゲ
ート部より加圧状態で注入し、金型内で冷却・固化し
て、LEDチップ全体をレンズ形状の遮光性樹脂75で
取り囲むように封止すれば、図9に示すような構造で実
装することができる。After that, the LED chip 70 in the above state is set in a mold, the heat-melted light-shielding resin is injected under pressure from the mold gate portion, cooled and solidified in the mold, If the entire LED chip is sealed so as to be surrounded by the lens-shaped light-shielding resin 75, the structure as shown in FIG. 9 can be mounted.
【0063】本例のようなチップ主面側から外部に光を
取り出すタイプの実装例では、特に、p側電極及びn型
電極を透光性の電極で構成するような構造のLEDチッ
プ(第5実施形態)を用いることにより、より高輝度な
LED製品を実現することができる。In the mounting example of the type in which light is extracted to the outside from the chip main surface side as in this example, particularly, the LED chip (the first side) having a structure in which the p-side electrode and the n-type electrode are composed of transparent electrodes is used. By using the fifth embodiment, it is possible to realize an LED product with higher brightness.
【0064】図10は、本発明の半導体発光素子を実装
した他のLED製品の断面構造図であり、チップ裏面側
から外部に光を取り出すタイプを示したものである。な
お、本LED製品は、上記第5実施形態(図7)で示し
たようなp側電極及びn型電極を透光性の電極で構成す
る構造のLEDチップを実装する場合ではなく、第1〜
第4実施形態で示すような構造のLEDチップを実装す
る場合に適用される。このLED製品に搭載されるLE
Dチップ80は、例えば、絶縁性のサファイア基板81
上にn−InGaAlN層82と、InGaAlNから
なる活性層83と、p−InGaAlN層84とを積層
したダブルヘテロ構造のウエハに対し、p型層84の一
部より選択的にエッチングしてn型層82を露出させ、
p型層84に対してはp側電極85を、n型層82に対
しては前記p側電極85と同一の電極材料からなるn型
電極86を形成している。前記p側電極85及びn型電
極86の電極としては、上記第1実施形態と同様に、例
えばNiとTiとAuを積層した合金を用いている。FIG. 10 is a cross-sectional structural view of another LED product on which the semiconductor light emitting device of the present invention is mounted, showing a type in which light is extracted from the back side of the chip to the outside. This LED product is not the case where the LED chip having the structure in which the p-side electrode and the n-type electrode are composed of the translucent electrodes is mounted as shown in the fifth embodiment (FIG. 7), but the first LED product is mounted. ~
It is applied when mounting the LED chip having the structure as shown in the fourth embodiment. LE installed in this LED product
The D chip 80 is, for example, an insulating sapphire substrate 81.
A double heterostructure wafer having an n-InGaAlN layer 82, an active layer 83 made of InGaAlN, and a p-InGaAlN layer 84 stacked thereon is selectively etched from a part of the p-type layer 84 to be n-type. Expose layer 82,
A p-side electrode 85 is formed on the p-type layer 84, and an n-type electrode 86 made of the same electrode material as the p-side electrode 85 is formed on the n-type layer 82. As the electrodes of the p-side electrode 85 and the n-type electrode 86, an alloy in which, for example, Ni, Ti, and Au are laminated is used as in the first embodiment.
【0065】このような構造のLEDチップ80の実装
は、フリップチップ方式で行われる。すなわち、サファ
イア基板81の裏面側を上向きにしたフェースダウン
で、チップ80のp側電極85及びn型電極86をそれ
ぞれ半田(例えばIn、PbSn)91,92を用いて
リードフレーム93,94に溶着し、電気的に接続す
る。そして、図9に示した実装例と同様に、チップ全体
をレンズ形状の樹脂95でモールドすれば、図10に示
すような構造で実装することができる。The LED chip 80 having such a structure is mounted by a flip chip method. That is, the p-side electrode 85 and the n-type electrode 86 of the chip 80 are welded to the lead frames 93 and 94 using solder (for example, In and PbSn) 91 and 92, respectively, with the face down with the back surface of the sapphire substrate 81 facing upward. Then connect electrically. Then, similarly to the mounting example shown in FIG. 9, if the entire chip is molded with the lens-shaped resin 95, the structure as shown in FIG. 10 can be mounted.
【0066】上記第1〜第4実施形態のLEDチップ
(n側電極及びp側電極が透光性でない)を、本例のよ
うなチップ裏面側から光を取り出すタイプで実装すれ
ば、図9に示す上記実装タイプ(チップ主面側から光を
取り出すタイプ)で実装した場合に比べて、活性層から
の発光をより有効に取り出すことができる。特に、n側
電極とp側電極に同一の電極を用いているので、均質な
反射特性が得られ、配光特性の優れたLED製品を実現
することができる。If the LED chips of the above-mentioned first to fourth embodiments (where the n-side electrode and the p-side electrode are not translucent) are mounted in a type in which light is extracted from the back side of the chip as in this example, FIG. Light emission from the active layer can be more effectively extracted as compared with the case of mounting with the above-described mounting type (type in which light is extracted from the chip main surface side) shown in. In particular, since the same electrode is used for the n-side electrode and the p-side electrode, a uniform reflection characteristic can be obtained, and an LED product having excellent light distribution characteristics can be realized.
【0067】[0067]
【発明の効果】以上詳細に説明したように、第1の発明
である半導体発光素子によれば、p側電極とn側電極を
同一の金属単体または合金、もしくはそれらからなる層
構造で構成したので、電極の形成工程を簡素化して製造
工程の短縮を図ることができ、良好な素子特性を得るこ
とが可能となる。As described in detail above, according to the semiconductor light emitting device of the first invention, the p-side electrode and the n-side electrode are formed of the same metal simple substance or alloy, or a layered structure composed of them. Therefore, it is possible to simplify the electrode forming process, shorten the manufacturing process, and obtain good device characteristics.
【0068】第2の発明である半導体発光素子によれ
ば、上記第1の発明において、前記p側電極と前記n側
電極を少なくともTiとAuとが積層するようにしたの
で、良好なオーミック特性を得ることが可能となる。According to the semiconductor light-emitting device of the second invention, in the first invention, at least Ti and Au are laminated on the p-side electrode and the n-side electrode, so that good ohmic characteristics are obtained. Can be obtained.
【0069】第3の発明である半導体発光素子によれ
ば、上記第1の発明において、前記p側電極と前記n側
電極を少なくともNiとAuとが積層するようにしたの
で、良好なオーミック特性を得ることが可能となる。According to the semiconductor light emitting element of the third invention, in the above first invention, at least Ni and Au are laminated on the p-side electrode and the n-side electrode, so that good ohmic characteristics are obtained. Can be obtained.
【0070】第4の発明である半導体発光素子によれ
ば、上記第1乃至第3の発明において、前記p側電極及
び前記n側電極がフリップチップ方式で第1及び第2の
外部リードにそれぞれ接続され、フェースダウンで前記
基板の裏面側より外部へ光を取り出すように構成されて
いるので、配光特性の優れたLED製品を実現すること
が可能になる。According to the semiconductor light emitting element of the fourth invention, in the above-mentioned first to third inventions, the p-side electrode and the n-side electrode are respectively flip-chip type to the first and second external leads. Since it is connected and the light is extracted from the back side of the substrate to the outside with the face down, it is possible to realize an LED product having excellent light distribution characteristics.
【0071】第5の発明である半導体発光素子によれ
ば、p側電極とn側電極は、同一の導電性材料の単体ま
たは複合体、もしくはそれらからなる層構造で構成され
且つ同一工程で形成された透光性の電極であるので、上
記第1乃至第3の発明に比べて光をより有効に取り出す
ことができ、チップ外部への光取り出し効率を一層向上
させることが可能になる。According to the semiconductor light emitting element of the fifth invention, the p-side electrode and the n-side electrode are composed of the same conductive material alone or in the form of a composite, or are formed in the same step. Since it is a transparent electrode, the light can be extracted more effectively as compared with the first to third inventions, and the light extraction efficiency to the outside of the chip can be further improved.
【0072】第6の発明である半導体発光素子の製造方
法によれば、基板の同一面側に窒化ガリウム系化合物半
導体からなるp型層とn型層を形成し、前記p型層とn
型層の全面または一部に、同一の金属単体または合金、
もしくはそれらからなる層構造で構成される電極を同時
に形成して、それぞれp側電極及びn側電極とするよう
にしたので、電極の形成工程が簡素化して全体の製造工
程を短くすることが可能となる。これにより、製造時間
が短縮化されるだけでなく、再現性が増すため良好な素
子特性が得られる歩留を高めることができ、品質に高い
信頼性を得ることができる。According to the method for manufacturing a semiconductor light emitting device of the sixth invention, a p-type layer and an n-type layer made of a gallium nitride compound semiconductor are formed on the same surface side of a substrate, and the p-type layer and the n-type layer are formed.
The same metal element or alloy, on all or part of the mold layer,
Alternatively, since electrodes having a layered structure made of them are formed at the same time to form a p-side electrode and an n-side electrode, respectively, the electrode forming process can be simplified and the whole manufacturing process can be shortened. Becomes As a result, not only the manufacturing time is shortened, but also the reproducibility is increased, so that the yield yielding good element characteristics can be increased, and high reliability in quality can be obtained.
【0073】第7の発明である半導体発光素子の製造方
法によれば、基板の同一面側に窒化ガリウム系化合物半
導体からなるp型層とn型層を形成し、前記p型層とn
型層の全面または一部に、同一の導電性材料の単体また
は複合体、もしくはそれらからなる層構造で構成される
透光性の電極を同時に形成して、それぞれp側電極及び
n側電極としたので、上記第5の発明と同等の半導体発
光素子を製造するに際して、電極の形成工程が簡素化し
て全体の製造工程の短縮を図ることが可能になり、上記
第6の発明と同等の効果を得ることができる。According to the method of manufacturing a semiconductor light emitting device of the seventh invention, a p-type layer and an n-type layer made of a gallium nitride compound semiconductor are formed on the same surface side of a substrate, and the p-type layer and the n-type layer are formed.
A transparent electrode composed of a single or composite of the same conductive material, or a layered structure composed of the same is simultaneously formed on the entire surface or a part of the mold layer to form a p-side electrode and an n-side electrode, respectively. Therefore, when manufacturing a semiconductor light emitting device equivalent to the fifth invention, it is possible to simplify the electrode forming process and shorten the entire manufacturing process, and the same effect as the sixth invention. Can be obtained.
【図1】本発明の第1実施形態に係る半導体発光素子の
断面構造図である。FIG. 1 is a cross-sectional structural diagram of a semiconductor light emitting device according to a first embodiment of the present invention.
【図2】図1に示した半導体発光素子の製造工程を示す
断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor light emitting device shown in FIG.
【図3】素子の動作電圧及び電極の密着性とNi,Ti
の厚さとの関係を示すグラフである。FIG. 3 shows the operating voltage of the device, the adhesion of the electrodes, and Ni, Ti.
Is a graph showing the relationship with the thickness of the.
【図4】本発明の第2実施形態に係る半導体発光素子
(シングルヘテロ構造)の断面構造図である。FIG. 4 is a sectional structural view of a semiconductor light emitting device (single hetero structure) according to a second embodiment of the present invention.
【図5】本発明の第3実施形態に係る半導体発光素子
(ダブルヘテロ構造)の断面構造図である。FIG. 5 is a sectional structural view of a semiconductor light emitting device (double hetero structure) according to a third embodiment of the present invention.
【図6】本発明の第4実施形態に係る半導体発光素子
(半導体レーザ)の断面構造図である。FIG. 6 is a sectional structural view of a semiconductor light emitting device (semiconductor laser) according to a fourth embodiment of the present invention.
【図7】本発明の第5実施形態に係る半導体発光素子
(ダブルヘテロ構造)の断面構造図である。FIG. 7 is a sectional structural view of a semiconductor light emitting device (double hetero structure) according to a fifth embodiment of the present invention.
【図8】第5実施形態の半導体発光素子の平面構造図で
ある。FIG. 8 is a plan structural view of a semiconductor light emitting device of a fifth embodiment.
【図9】本発明の半導体発光素子を実装したLED製品
の断面構造図である。FIG. 9 is a sectional structural view of an LED product on which the semiconductor light emitting device of the present invention is mounted.
【図10】本発明の半導体発光素子を実装した他のLE
D製品の断面構造図である。FIG. 10 is another LE in which the semiconductor light emitting device of the present invention is mounted.
It is a cross-section figure of D product.
【図11】従来の窒化ガリウム系化合物半導体発光素子
の構造を示す断面図である。FIG. 11 is a cross-sectional view showing a structure of a conventional gallium nitride-based compound semiconductor light emitting device.
【図12】上記図11に示した半導体発光素子の製造工
程を示す断面図である。12 is a cross-sectional view showing a manufacturing process of the semiconductor light emitting device shown in FIG.
【図13】図12の続きの断面図である。FIG. 13 is a cross-sectional view following FIG.
11,31,41,51,61 サファイア基板 12,32,42,52,62 n型層 13,33,34,44,54,56,64 p型層 14,35,45,57,65 p側電極 15,36,46,58,66 n側電極 21 マスクパターン 22 金属層 43,53,63 活性層 55 n型領域 11, 31, 41, 51, 61 Sapphire substrate 12, 32, 42, 52, 62 n-type layer 13, 33, 34, 44, 54, 56, 64 p-type layer 14, 35, 45, 57, 65 p-side Electrode 15, 36, 46, 58, 66 n-side electrode 21 mask pattern 22 metal layer 43, 53, 63 active layer 55 n-type region
Claims (7)
系化合物半導体からなるp型層及びn型層と、前記p型
層及び前記n型層上にそれぞれ形成されたp側電極及び
n側電極とを備えた半導体発光素子において、 前記p側電極と前記n側電極は、同一の金属単体または
合金、もしくはそれらからなる層構造で構成され且つ同
一工程で形成された電極であることを特徴とする半導体
発光素子。1. A p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor formed on the same surface side of a substrate, and a p-side electrode and an n-side formed on the p-type layer and the n-type layer, respectively. In a semiconductor light emitting device including an electrode, the p-side electrode and the n-side electrode are electrodes formed of the same metal simple substance or alloy, or a layered structure including them in the same step. Semiconductor light emitting device.
ともTiとAuとが積層されてなることを特徴とする請
求項1記載の半導体発光素子。2. The semiconductor light emitting device according to claim 1, wherein the p-side electrode and the n-side electrode are formed by stacking at least Ti and Au.
ともNiとAuとが積層されてなることを特徴とする請
求項1記載の半導体発光素子。3. The semiconductor light emitting device according to claim 1, wherein the p-side electrode and the n-side electrode are formed by stacking at least Ni and Au.
プチップ方式で第1及び第2の外部リードにそれぞれ接
続され、フェースダウンで前記基板の裏面側より外部へ
光を取り出すように構成されたことを特徴とする請求項
1乃至請求項3記載の半導体発光素子。4. The p-side electrode and the n-side electrode are respectively connected to the first and second external leads by a flip chip method, and the face down is used to extract light from the back surface side of the substrate to the outside. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is a semiconductor light emitting device.
系化合物半導体からなるp型層及びn型層と、前記p型
層及び前記n型層上にそれぞれ形成されたp側電極及び
n側電極とを備えた半導体発光素子において、 前記p側電極と前記n側電極は、同一の導電性材料の単
体または複合体、もしくはそれらからなる層構造で構成
され且つ同一工程で形成された透光性の電極であること
を特徴とする半導体発光素子。5. A p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor formed on the same surface side of the substrate, and a p-side electrode and an n-side formed on the p-type layer and the n-type layer, respectively. In a semiconductor light emitting device including an electrode, the p-side electrode and the n-side electrode are composed of a simple substance or a complex of the same conductive material, or a layered structure made of them, and are transparent in the same process. A semiconductor light-emitting device, which is a conductive electrode.
半導体からなるp型層とn型層を形成し、 前記p型層とn型層の全面または一部に、同一の金属単
体または合金、もしくはそれらからなる層構造で構成さ
れる電極を同時に形成して、それぞれp側電極及びn側
電極とすることを特徴とする半導体発光素子の製造方
法。6. A p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor are formed on the same surface side of a substrate, and the same metal simple substance or alloy is formed on all or part of the p-type layer and the n-type layer. Or a method of manufacturing a semiconductor light emitting device, characterized in that an electrode having a layered structure composed of them is simultaneously formed to form a p-side electrode and an n-side electrode, respectively.
半導体からなるp型層とn型層を形成し、 前記p型層とn型層の全面または一部に、同一の導電性
材料の単体または複合体、もしくはそれらからなる層構
造で構成される透光性の電極を同時に形成して、それぞ
れp側電極及びn側電極とすることを特徴とする半導体
発光素子の製造方法。7. A p-type layer and an n-type layer made of a gallium nitride-based compound semiconductor are formed on the same surface side of a substrate, and the same conductive material is formed on all or part of the p-type layer and the n-type layer. A method for manufacturing a semiconductor light-emitting device, characterized in that a light-transmitting electrode composed of a single substance or a composite or a layered structure composed of them is simultaneously formed to form a p-side electrode and an n-side electrode, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34161296A JPH09232632A (en) | 1995-12-22 | 1996-12-20 | Semiconductor light emitting device and method of manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33541295 | 1995-12-22 | ||
| JP7-335412 | 1995-12-22 | ||
| JP34161296A JPH09232632A (en) | 1995-12-22 | 1996-12-20 | Semiconductor light emitting device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09232632A true JPH09232632A (en) | 1997-09-05 |
Family
ID=26575165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34161296A Pending JPH09232632A (en) | 1995-12-22 | 1996-12-20 | Semiconductor light emitting device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09232632A (en) |
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