JPH09244960A - フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム - Google Patents

フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム

Info

Publication number: JPH09244960A
Authority: JP; Japan
Prior art keywords: data; memory; packet; message; register
Prior art date: 1995-06-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Pending

Application number

JP8146057A

Other languages

English (en)

Japanese (ja)

Inventor

Robert W Horst

ダブリューホーストロバート

William Edward Baker

エドワードベイカーウィリアム

William Patterson Bunton

パターソンバントンウィリアム

Gary F Campbell

エフキャンベルゲアリー

Richard W Cutts Jr

ダブリューカッツジュニアリチャード

Daniel L Fowler

エルファウラーダニエル

David J Garcia

ジェイガーシアディヴィッド

Paul N Hintikka

エヌヒンティッカポール

Geoffrey I Iswandhi

アイイスワンディージェフリー

David Paul Sonnier

ポールソーニアディヴィッド

William Joel Watson

ジョエルワトソンウィリアム

Frank A Williams

エイウィリアムスフランク

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Tandem Computers Inc

Original Assignee

Tandem Computers Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1995-06-07

Filing date

1996-06-07

Publication date

1997-09-19

1995-06-07 Priority claimed from US08/482,618 external-priority patent/US5964835A/en

1996-06-07 Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc

1997-09-19 Publication of JPH09244960A publication Critical patent/JPH09244960A/ja

Status Pending legal-status Critical Current

Links

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Landscapes

Hardware Redundancy (AREA)
Storage Device Security (AREA)

JP8146057A 1995-06-07 1996-06-07 フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム Pending JPH09244960A (ja)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US08/482618		1995-06-07
US08/482,618 US5964835A (en)	1992-12-17	1995-06-07	Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source

Publications (1)

Publication Number	Publication Date
JPH09244960A true JPH09244960A (ja)	1997-09-19

Family

ID=23916759

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP8146057A Pending JPH09244960A (ja)	1995-06-07	1996-06-07	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム

Country Status (2)

Country	Link
JP (1)	JPH09244960A (fr)
CA (1)	CA2178456A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CN103077152A (zh) *	2012-12-25	2013-05-01	北京四方继保自动化股份有限公司	一种用于智能变电站终端设备芯片间的通信加速方法

1996
- 1996-06-06 CA CA 2178456 patent/CA2178456A1/fr not_active Abandoned
- 1996-06-07 JP JP8146057A patent/JPH09244960A/ja active Pending

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CN103077152A (zh) *	2012-12-25	2013-05-01	北京四方继保自动化股份有限公司	一种用于智能变电站终端设备芯片间的通信加速方法

Also Published As

Publication number	Publication date
CA2178456A1 (fr)	1996-12-08

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2007-03-06

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Publication	Publication Date	Title
JP3800564B2 (ja)	2006-07-26	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム
US6157967A (en)	2000-12-05	Method of data communication flow control in a data processing system using busy/ready commands
US5751932A (en)	1998-05-12	Fail-fast, fail-functional, fault-tolerant multiprocessor system
US5867501A (en)	1999-02-02	Encoding for communicating data and commands
US6151689A (en)	2000-11-21	Detecting and isolating errors occurring in data communication in a multiple processor system
US5675807A (en)	1997-10-07	Interrupt message delivery identified by storage location of received interrupt data
US5964835A (en)	1999-10-12	Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
JP3871732B2 (ja)	2007-01-24	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム
JPH09128347A (ja)	1997-05-16	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム
JPH09244960A (ja)	1997-09-19	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム
JPH09244906A (ja)	1997-09-19	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム
JPH09134333A (ja)	1997-05-20	フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム

JPH09244960A - フェイル−ファースト、フェイル−ファンクショナル、フォルトトレラント・マルチプロセッサ・システム - Google Patents

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Applications Claiming Priority (2)

Publications (1)

Family

ID=23916759

Family Applications (1)

Country Status (2)

Cited By (1)

Cited By (1)

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