JPH09246371A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH09246371A
JPH09246371A JP5722296A JP5722296A JPH09246371A JP H09246371 A JPH09246371 A JP H09246371A JP 5722296 A JP5722296 A JP 5722296A JP 5722296 A JP5722296 A JP 5722296A JP H09246371 A JPH09246371 A JP H09246371A
Authority
JP
Japan
Prior art keywords
type impurity
semiconductor substrate
conductivity type
type semiconductor
impurity layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5722296A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Sugiura
義幸 杉浦
Kazuyuki Tomii
和志 富井
Hideo Nagahama
英雄 長浜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP5722296A priority Critical patent/JPH09246371A/en
Publication of JPH09246371A publication Critical patent/JPH09246371A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, where a time required for an element isolation process can be shortened. SOLUTION: An N-type impurity layer 2 is formed on a P-type semiconductor substrate 1, and an insulating film 3 of silicon oxide is formed thereon. Then, a part of the insulating film 3 is removed through a photolithography technique and an etching technique for the formation of an opening at a required position, the semiconductor substrate 1 is anisotropiccally etched with alkali etchant such as potassium hydroxide (KOH) water solution using the insulating film 3 with an opening as a mask to form a groove 4 which reaches to the a P-type semiconductor substrate 1. In succession, P-type impurity ions of baron (B) or the like are implanted only into the groove 4 and thermally diffused to form a P-type impurity region 5, and the P-type semiconductor substrate 1 and the P-type impurity region 5 are connected together to carry out element isolation for the formation of an N-type semiconductor region 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、接合分離を利用し
た半導体装置及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device utilizing junction separation and a method of manufacturing the same.

【0002】[0002]

【従来の技術】図は、従来例に係る半導体装置を示す略
断面図である。従来の半導体装置は、第1導電型半導体
基板であるp型半導体基板1上に第2導電型不純物層か
ら成る支持体層としてのn型不純物層2を形成し、n型
不純物層2の素子間分離を行いたい箇所にボロン(B)
等のp型不純物を拡散して第1導電型不純物層であるp
型不純物領域4を形成して第2導電型半導体領域である
n型半導体領域6を形成し、シリコン酸化膜等の絶縁膜
3により表面を成膜する。そして、p型半導体基板1及
びp型不純物領域4に素子全体の最低電位を印加するこ
とによりpn接合の整流性を利用して各素子間の分離を
行っていた。
2. Description of the Related Art FIG. 1 is a schematic sectional view showing a semiconductor device according to a conventional example. In a conventional semiconductor device, an n-type impurity layer 2 as a support layer composed of a second conductivity-type impurity layer is formed on a p-type semiconductor substrate 1 which is a first conductivity-type semiconductor substrate, and an element of the n-type impurity layer 2 is formed. Boron (B) at the location where separation is desired
Which is a first conductivity type impurity layer by diffusing p-type impurities such as
A type impurity region 4 is formed to form an n-type semiconductor region 6 which is a second conductivity type semiconductor region, and a surface of the insulating film 3 such as a silicon oxide film is formed. Then, by applying the lowest potential of the entire element to the p-type semiconductor substrate 1 and the p-type impurity region 4, the elements are separated by utilizing the rectifying property of the pn junction.

【0003】[0003]

【発明が解決しようとする課題】ところが、上述のよう
な構成の半導体装置においては、n型不純物層2の厚み
が増すに従って、接合分離のためのp型不純物領域4の
拡散深さが深くなり、その結果、例えばn型不純物層2
の厚みが20μm程度であってもp型半導体基板1に到
達するp型不純物領域4を形成するために数十時間かか
り、工程の長時間化につながっていた。
However, in the semiconductor device having the above-described structure, as the thickness of the n-type impurity layer 2 increases, the diffusion depth of the p-type impurity region 4 for junction isolation becomes deeper. As a result, for example, the n-type impurity layer 2
Even if the thickness is about 20 μm, it takes several tens of hours to form the p-type impurity region 4 reaching the p-type semiconductor substrate 1, resulting in a longer process.

【0004】本発明は、上記の点に鑑みて成されたもの
であり、その目的とするところは、素子間分離に伴う工
程時間を短縮することのできる半導体装置及びその製造
方法を提供することにある。
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of shortening the process time associated with element isolation. It is in.

【0005】[0005]

【課題を解決するための手段】請求項1記載の発明は、
第1導電型半導体基板と、該第1導電型半導体基板上に
形成された第2導電型不純物層から成る支持体層と、該
支持体層に前記第1導電型半導体基板に到達するように
形成された溝部と、該溝部に第1導電型不純物を拡散す
ることにより形成された第1導電型不純物層とを有して
成り、該第1導電型不純物層と前記第1導電型半導体基
板とで分離された第2導電型半導体領域を形成したこと
を特徴とするものである。
According to the first aspect of the present invention,
A support layer composed of a first conductivity type semiconductor substrate, a second conductivity type impurity layer formed on the first conductivity type semiconductor substrate, and the support layer reaching the first conductivity type semiconductor substrate. A first conductive type impurity layer formed by diffusing a first conductive type impurity into the groove, and the first conductive type impurity layer and the first conductive type semiconductor substrate. The second conductivity type semiconductor region separated by and is formed.

【0006】請求項2記載の発明は、第1導電型半導体
基板上に第2導電型不純物層から成る支持体層を形成
し、該支持体層上に絶縁膜を形成した後、該絶縁膜の所
望の部分の絶縁膜を除去し、前記絶縁膜をマスクとして
前記第1導電型半導体基板に到達するまでエッチングを
行って溝部を形成し、該溝部に第1導電型不純物を拡散
することにより第1導電型不純物層を形成して、該第1
導電型不純物層と前記第1導電型半導体基板とで分離さ
れた第2導電型半導体領域を形成したことを特徴とする
ものである。
According to a second aspect of the present invention, a support layer made of a second conductivity type impurity layer is formed on the first conductivity type semiconductor substrate, an insulating film is formed on the support layer, and then the insulating film is formed. By removing the insulating film at a desired portion of the substrate, etching the insulating film as a mask until reaching the first conductivity type semiconductor substrate to form a groove, and diffusing the first conductivity type impurity into the groove. Forming a first conductivity type impurity layer,
A second conductivity type semiconductor region separated by a conductivity type impurity layer and the first conductivity type semiconductor substrate is formed.

【0007】[0007]

【発明の実施の形態】以下、本発明の一実施形態につい
て図面に基づき説明する。図1は、本発明の一実施形態
に係る半導体装置の製造工程を示す略断面図である。先
ず、第1導電型半導体基板であるp型半導体基板1上
に、第2導電型不純物層であるn型不純物層2を形成
し、その上にシリコン酸化膜等の絶縁膜3を形成する
(図1(a))。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention. First, an n-type impurity layer 2 which is a second conductivity type impurity layer is formed on a p-type semiconductor substrate 1 which is a first conductivity type semiconductor substrate, and an insulating film 3 such as a silicon oxide film is formed thereon ( FIG. 1 (a)).

【0008】次に、絶縁膜3の所望の位置に、フォトリ
ソグラフィ技術及びエッチング技術を用いて絶縁膜3の
一部を除去して開口部を形成し、開口部が形成された絶
縁膜5をマスクとして水酸化カリウム(KOH)水溶液
等のアルカリ系のエッチャントにより異方性エッチング
を行い、p型半導体基板1に到達する溝部4を形成する
(図1(b))。
Next, at a desired position of the insulating film 3, a part of the insulating film 3 is removed by using a photolithography technique and an etching technique to form an opening, and the insulating film 5 having the opening is formed. Anisotropic etching is performed using an alkaline etchant such as an aqueous potassium hydroxide (KOH) solution as a mask to form a groove 4 reaching the p-type semiconductor substrate 1 (FIG. 1B).

【0009】続いて、ボロン(B)等のp型不純物を溝
部4にのみイオン注入及び熱拡散を行って第1導電型不
純物層であるp型不純物領域5を形成し、p型半導体基
板1とp型不純物領域5とを接続させることにより素子
間分離されて成る第2導電型半導体領域であるn型半導
体領域6を形成する(図1(c))。
Subsequently, a p-type impurity such as boron (B) is ion-implanted and thermally diffused only in the groove 4 to form a p-type impurity region 5 which is a first conductivity type impurity layer, and the p-type semiconductor substrate 1 is formed. And the p-type impurity region 5 are connected to form an n-type semiconductor region 6 which is a second conductivity type semiconductor region separated from each other (FIG. 1C).

【0010】従って、本実施形態においては、n型不純
物層2に溝部4を形成し、溝部4にのみp型不純物をイ
オン注入及び熱拡散してp型不純物領域5を形成するよ
うにしたので、n型不純物層2の厚みが増した場合にお
いてもp型半導体基板1に接続するようにp型不純物層
5を形成することが比較的短時間ですみ、大幅な工程時
間の短縮が可能となる。
Therefore, in the present embodiment, the groove 4 is formed in the n-type impurity layer 2, and the p-type impurity is ion-implanted and thermally diffused only in the groove 4 to form the p-type impurity region 5. Even when the thickness of the n-type impurity layer 2 is increased, it is possible to form the p-type impurity layer 5 so as to be connected to the p-type semiconductor substrate 1 in a relatively short time, and it is possible to significantly reduce the process time. Become.

【0011】[0011]

【発明の効果】請求項1または請求項2記載の発明は、
第1導電型半導体基板と、第1導電型半導体基板上に形
成された第2導電型不純物層から成る支持体層と、支持
体層に第1導電型半導体基板に到達するように形成され
た溝部と、溝部に第1導電型不純物を拡散することによ
り形成された第1導電型不純物層とを有して成り、第1
導電型不純物層と第1導電型半導体基板とで分離された
第2導電型半導体領域を形成したので、例えば、支持体
層の厚みが増した場合においても、第1導電型半導体基
板に接続するように第1導電型不純物層を形成すること
が比較的短時間ですみ、従来に比べて大幅な工程時間の
短縮がはかれ、素子間分離に伴う工程時間を短縮するこ
とのできる半導体装置及びその製造方法を提供すること
ができた。
The invention according to claim 1 or 2 is
A first conductive type semiconductor substrate, a support layer made of a second conductive type impurity layer formed on the first conductive type semiconductor substrate, and a support layer formed so as to reach the first conductive type semiconductor substrate. A first conductive type impurity layer formed by diffusing a first conductive type impurity into the groove;
Since the second conductivity type semiconductor region separated by the conductivity type impurity layer and the first conductivity type semiconductor substrate is formed, for example, even when the thickness of the support layer is increased, the second conductivity type semiconductor region is connected to the first conductivity type semiconductor substrate. As described above, it is possible to form the first conductivity type impurity layer in a relatively short time, and the process time can be significantly shortened as compared with the conventional one, and the semiconductor device capable of shortening the process time associated with element isolation can be provided. It was possible to provide the manufacturing method.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態に係る半導体装置の製造工
程を示す略断面図である。
FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

【図2】従来例に係る半導体装置を示す略断面図であ
る。
FIG. 2 is a schematic cross-sectional view showing a semiconductor device according to a conventional example.

【符号の説明】[Explanation of symbols]

1 p型半導体基板 2 n型不純物層 3 絶縁膜 4 溝部 5 p型不純物領域 6 n型半導体領域 1 p-type semiconductor substrate 2 n-type impurity layer 3 insulating film 4 groove 5 p-type impurity region 6 n-type semiconductor region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型半導体基板と、該第1導電型
半導体基板上に形成された第2導電型不純物層から成る
支持体層と、該支持体層に前記第1導電型半導体基板に
到達するように形成された溝部と、該溝部に第1導電型
不純物を拡散することにより形成された第1導電型不純
物層とを有して成り、該第1導電型不純物層と前記第1
導電型半導体基板とで分離された第2導電型半導体領域
を形成したことを特徴とする半導体装置。
1. A support layer composed of a first conductivity type semiconductor substrate, a second conductivity type impurity layer formed on the first conductivity type semiconductor substrate, and the first conductivity type semiconductor substrate on the support layer. And a first conductivity type impurity layer formed by diffusing the first conductivity type impurity into the groove part. The first conductivity type impurity layer and the first conductivity type impurity layer 1
A semiconductor device having a second conductivity type semiconductor region separated from a conductivity type semiconductor substrate.
【請求項2】 第1導電型半導体基板上に第2導電型不
純物層から成る支持体層を形成し、該支持体層上に絶縁
膜を形成した後、該絶縁膜の所望の部分の絶縁膜を除去
し、前記絶縁膜をマスクとして前記第1導電型半導体基
板に到達するまでエッチングを行って溝部を形成し、該
溝部に第1導電型不純物を拡散することにより第1導電
型不純物層を形成して、該第1導電型不純物層と前記第
1導電型半導体基板とで分離された第2導電型半導体領
域を形成したことを特徴とする半導体装置の製造方法。
2. A support layer made of a second conductivity type impurity layer is formed on a first conductivity type semiconductor substrate, an insulating film is formed on the support layer, and then a desired portion of the insulation film is insulated. The first conductive type impurity layer is formed by removing the film, performing etching using the insulating film as a mask until reaching the first conductive type semiconductor substrate to form a groove, and diffusing the first conductive type impurity into the groove. And a second conductivity type semiconductor region separated by the first conductivity type impurity layer and the first conductivity type semiconductor substrate are formed.
JP5722296A 1996-03-14 1996-03-14 Semiconductor device and manufacture thereof Pending JPH09246371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5722296A JPH09246371A (en) 1996-03-14 1996-03-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5722296A JPH09246371A (en) 1996-03-14 1996-03-14 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH09246371A true JPH09246371A (en) 1997-09-19

Family

ID=13049513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5722296A Pending JPH09246371A (en) 1996-03-14 1996-03-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH09246371A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156926A (en) * 2004-08-19 2006-06-15 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof
JP2006303410A (en) * 2005-03-25 2006-11-02 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof
US8697558B2 (en) 2004-08-19 2014-04-15 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156926A (en) * 2004-08-19 2006-06-15 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof
US8119496B2 (en) 2004-08-19 2012-02-21 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US8697558B2 (en) 2004-08-19 2014-04-15 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US8759870B2 (en) 2004-08-19 2014-06-24 Fuji Electric Co., Ltd. Semiconductor device
JP2006303410A (en) * 2005-03-25 2006-11-02 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof

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