JPH09246376A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) [PROBLEMS] To provide a technique for processing via holes that connect wirings arranged above and below in a desired shape with good reproducibility. An interlayer insulating film is composed of a silicon oxide film and a silicon nitride film, and the silicon oxide film is processed by wet etching using the silicon nitride film as a stopper layer. By processing by dry etching, a via hole 7 for connecting the upper layer wiring 8 and the lower layer wiring 3 is formed in the interlayer insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having via holes connecting upper and lower wirings. is there.

[0002]

2. Description of the Related Art Via holes connecting upper and lower wirings with an interlayer insulating film made of a silicon oxide film having a thickness of 2.0 μm or more interposed therebetween are formed by wet etching or dry etching. However, the following problems occur when forming the via hole by wet etching or dry etching.

That is, in the case of wet etching,
The surface of the underlying wiring (lower wiring) is easily etched by the etching solution for the silicon oxide film. For this reason, at the time of over-etching after processing the silicon oxide film by wet etching, the film thickness of the portion of the lower layer wiring that is in contact with the formed via hole is reduced and wiring resistance is increased.

Further, since the penetration rate of the etching solution between the photoresist used as a mask for wet etching and the silicon oxide film is as high as about 0.25 μm / min, the above photoresist is oxidized by the wet etching for a long time. It peels off from the surface of the silicon film.

Further, in the case of dry etching, a reaction product of a photoresist used as a mask for dry etching and an etching gas or a reaction product of a lower layer wiring and an etching gas adheres to a sidewall of a via hole during dry etching. Therefore, it is difficult to control the shape and size of the via hole.

Therefore, there is a method in which the upper portion of the silicon oxide film forming the interlayer insulating film is processed by wet etching, and then the lower portion of the remaining silicon oxide film thinned by dry etching is processed to form a via hole. Is being considered.

In the method using both wet etching and dry etching, since the etching solution for wet etching does not contact the lower layer wiring, the lower layer wiring is not etched and the wiring resistance of the lower layer wiring can be prevented from increasing. Further, since the silicon oxide film processed by dry etching has a small thickness, it is possible to reduce reaction products attached to the sidewalls of the via holes during dry etching.

[0008]

However, when a via hole is formed in an interlayer insulating film made of a silicon oxide film having a thickness of 2.0 μm or more by a method using both wet etching and dry etching, it is processed by wet etching. The thickness of the remaining silicon oxide film after the formation becomes uneven, and even if the remaining silicon oxide film is processed by dry etching after that, the reproducibility of the shape of the formed via hole is poor, which is desirable. The present inventor has found that there is a problem that a via hole having a processed shape cannot be obtained.

An object of the present invention is to provide a technique capable of processing via holes connecting upper and lower wirings sandwiching an interlayer insulating film into a desired shape with good reproducibility.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) in the semiconductor integrated circuit device of the present invention, via holes are formed in the interlayer insulating film for connecting the wirings arranged above and below with the interlayer insulating film interposed therebetween, and the interlayer insulating film is oxidized. It is composed of a silicon film and a silicon nitride film.

(2) Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing an interlayer insulating film and a via hole provided in the interlayer insulating film according to the above (1). After sequentially depositing a silicon nitride film and a silicon oxide film on the wiring, the patterned resist is used as a mask to process the silicon oxide film by wet etching, and subsequently, the silicon nitride film is processed by dry etching. A via hole is formed in an interlayer insulating film made of a silicon oxide film and a silicon nitride film.

(3) The method for manufacturing a semiconductor integrated circuit device of the present invention is the method for manufacturing an interlayer insulating film and the via hole provided in the interlayer insulating film according to the above (1). A lower silicon nitride film, a silicon oxide film, and an upper silicon nitride film are sequentially deposited on the wiring to be processed, and then the patterned upper silicon nitride film is used as a mask to process the silicon oxide film by wet etching, followed by dry etching. The lower silicon nitride film is processed by, then the upper silicon nitride film is removed, and a via hole is formed in the interlayer insulating film composed of the silicon oxide film and the lower silicon nitride film.

According to the above means, the wet etching of the silicon oxide film stops on the silicon nitride film.
By wet etching, a part of the via hole can be formed in the silicon oxide film with good reproducibility. further,
Since the silicon nitride film has a uniform film thickness, another part of the via hole can be formed in the silicon nitride film with good reproducibility by dry etching.

FIG. 10 shows a plasma CVD (Chemical Vap
The etching rates of the silicon nitride film and the silicon oxide film formed by the (or Deposition) method with respect to the fluorine (F) -based etching solution (HF: NH ₄ F: CH ₃ COOH = 1: 20: 7) are shown. The etching rate of the silicon nitride film is about 1/10 of the etching rate of the silicon oxide film, and it can be seen that the silicon nitride film can be used as a stopper layer during wet etching of the silicon oxide film.

Further, according to the above-mentioned means (3), since the silicon nitride film having good adhesion to the silicon oxide film is used as the mask during the wet etching of the silicon oxide film, the silicon oxide film is wet for a long time. Even after etching, the silicon nitride film that is the mask does not peel off. Therefore, a thick silicon oxide film can be used as the interlayer insulating film.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing an interlayer insulating film and a via hole formed in this interlayer insulating film according to an embodiment of the present invention.

The interlayer insulating film located between the upper layer wiring 8 and the lower layer wiring 3 is composed of the silicon oxide film 5 and the silicon nitride film 4, and the silicon oxide film 5 is formed by wet etching and also by the silicon nitride film. The via hole 7 is formed in the interlayer insulating film 4 by being processed by dry etching.

Next, a method of manufacturing the via hole according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 1, a conductive film (for example, an aluminum alloy film or a tungsten film) is deposited on a semiconductor substrate 1 having a semiconductor element formed thereon by a sputtering method or an evaporation method, and then this conductive film is formed. Is processed using the patterned photoresist as a mask,
The lower layer wiring 3 is formed.

Next, TEOS (Tetra Ethyl Ortho Sili
After a silicon nitride film 4 and a silicon oxide film 5 are sequentially deposited on the semiconductor substrate 1 by a plasma CVD method using cate; Si (OC ₂ H ₅ ) ₄ ) as a source to form an interlayer insulating film having a two-layer structure. A photoresist 6 having a film thickness of about 3.0 μm is applied on the semiconductor substrate 1 and patterned.

The film thicknesses of the silicon nitride film 4 and the silicon oxide film 5 are, for example, about 0.4 μm and about respectively.
The thickness of the silicon oxide film 5 is 6.0 μm, and the thickness of the silicon oxide film 5 is set so that the silicon oxide film 5 can be processed by wet etching within a period in which the photoresist 6 is not peeled off.

Next, as shown in FIG. 2, using the photoresist 6 as a mask, an F-based etching solution (for example, HF: NH _{4) is used.}
The silicon oxide film 5 is processed by F: CH ₃ COOH = 1: 20: 7), and then, as shown in FIG. 3, for example, reactive ion etching (Reacti) using a parallel plate type etching apparatus is performed.
The silicon nitride film 4 is processed by ve Ion Etching (RIE) to form a via hole 7.

Next, as shown in FIG. 4, after removing the photoresist 6, a conductive film (for example, an aluminum alloy film or a tungsten film) is deposited on the semiconductor substrate 1 by a sputtering method or a vapor deposition method, and then, The conductive film is processed using the patterned photoresist as a mask to form the upper wiring 8.

As described above, according to the first embodiment, the silicon nitride film 4 having a thickness of 1.0 μm or less is arranged between the silicon oxide film 5 and the lower wiring 3, and the silicon nitride film 4 is used as a stopper layer. Since the silicon oxide film 5 is processed by wet etching and then the silicon nitride film 4 is processed by dry etching, the via hole 7 with good reproducibility of the processed shape is formed.
Can be formed in the interlayer insulating film.

That is, the F-based etching solution (HF: NH ₄ F: CH
_Since the etching rate of the silicon nitride film 4 with respect to ( ₃ COOH) is about 1/10 of the etching rate of the silicon oxide film 5, the wet etching of the silicon oxide film 5 stops on the silicon nitride film 4. Therefore, the via hole 7 is formed on the silicon oxide film 5 by wet etching with good reproducibility.
Can be formed. Further, the film thickness of the silicon nitride film 4 is not decreased by the above wet etching and is uniform, and since the film thickness is as thin as 1.0 μm or less, even if the silicon nitride film 4 is processed by dry etching, The reaction product attached to the side wall of the via hole 7 formed is small. Therefore, another part of the via hole 7 can be formed in the silicon nitride film 4 with good reproducibility by dry etching.

(Embodiment 2) FIG. 5 is a cross-sectional view of an essential part of a semiconductor substrate showing an interlayer insulating film and a via hole formed in the interlayer insulating film according to another embodiment of the present invention.

The interlayer insulating film located between the upper wiring 8 and the lower wiring 3 is composed of an upper silicon oxide film 11, a silicon nitride film 10 and a lower silicon oxide film 9, and the upper silicon oxide film 11 is wet. Via holes 7 are formed in the interlayer insulating film by etching and by sequentially processing the silicon nitride film 10 and the lower silicon oxide film 9 by dry etching.

The thickness of the lower silicon oxide film 9 is set so that the lower silicon oxide film 9 is processed by dry etching within a time in which an amount of a reaction product that affects the shape and size of the via hole 7 is not generated. The upper silicon oxide film 11, the silicon nitride film 10, and the lower silicon oxide film 9 have a film thickness of, for example, about 6.0 μm and about 0.4 μm, respectively.
And about 0.9 μm.

Thus, according to the second embodiment, similarly to the first embodiment, the upper silicon oxide film 11 is processed by wet etching using the silicon nitride film 10 as a stopper layer, and subsequently, the silicon nitride film is formed. Since the 10 and the lower silicon oxide film 9 are sequentially processed by dry etching, the via hole 7 with good reproducibility of the processed shape can be formed in the interlayer insulating film.

Further, since the upper silicon oxide film 11 must be processed by wet etching within the time during which the photoresist used for the mask during processing cannot be removed, the upper silicon oxide film 11 has a limited film thickness. . However, by forming the lower silicon oxide film 9 under the silicon nitride film 10 provided as the stopper layer, the total thickness of the interlayer insulating film can be increased. As a result, the interlayer capacitance of the interlayer insulating film can be reduced.

(Third Embodiment) FIG. 9 is a cross-sectional view of an essential part of a semiconductor substrate showing an interlayer insulating film and a via hole formed in the interlayer insulating film according to another embodiment of the present invention.

The interlayer insulating film located between the upper layer wiring 8 and the lower layer wiring 3 is composed of a silicon oxide film 13 and a lower layer silicon nitride film 12, and the silicon oxide film 1
3 is processed by wet etching, and the lower silicon nitride film 12 is processed by dry etching to form a via hole 7 in the interlayer insulating film.

Next, a method of manufacturing via holes according to the third embodiment will be described with reference to FIGS.

First, as shown in FIG. 6, a conductive film (for example, an aluminum alloy film or a tungsten film) is deposited on the semiconductor substrate 1 having semiconductor elements formed thereon by a sputtering method or a vapor deposition method, and then this conductive film is formed. Is processed using the patterned photoresist as a mask,
The lower layer wiring 3 is formed.

Next, plasma C using TEOS as a source
The lower silicon nitride film 12, the silicon oxide film 13, and the upper silicon nitride film 1 are formed on the semiconductor substrate 1 by the VD method.
After sequentially depositing 4 to form an interlayer insulating film having a three-layer structure,
A photoresist 15 is applied on the semiconductor substrate 1 and patterned.

The film thicknesses of the upper silicon nitride film 14, the silicon oxide film 13 and the lower silicon nitride film 12 are, for example, about 0.4 μm, about 7.0 μm and about 0.4 μm, respectively.
m.

Next, as shown in FIG. 7, the upper silicon nitride film 14 is processed by dry etching using the photoresist 15 as a mask, the photoresist 15 is removed, and then the patterned upper silicon nitride film is formed. 14 as a mask and an F-based etching solution (for example, H
F: NH ₄ F: CH ₃ COOH = 1: 20: 7)
To process.

Next, as shown in FIG. 8, the upper silicon nitride film 14 and the exposed lower silicon nitride film 12 are removed by dry etching to form a via hole 7.

Next, as shown in FIG. 9, a conductive film (for example, an aluminum alloy film or a tungsten film) is deposited on the semiconductor substrate 1 by a sputtering method or an evaporation method, and then the conductive film is patterned. Processing is performed using the resist as a mask to form the upper wiring 8.

Thus, according to the third embodiment, as in the first embodiment, the silicon oxide film 13 is processed by wet etching using the lower silicon nitride film 12 as a stopper layer, and then the lower silicon nitride film is processed. Since the film 12 is processed by dry etching, the via hole 7 with good reproducibility of the processed shape can be formed in the interlayer insulating film.

Furthermore, since the upper silicon nitride film 14 has good adhesion to the silicon oxide film 13, the etching liquid hardly penetrates between them, and the upper silicon nitride film 14 used as a mask during processing is the silicon oxide film. 13 Hard to peel off from above. Therefore, the degree of freedom in setting the thickness of the silicon oxide film 13 and the wet etching time can be increased, and the thick silicon oxide film 13 can be used as the interlayer insulating film. As a result, the interlayer capacitance of the interlayer insulating film can be reduced.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, since a silicon nitride film having a uniform film thickness is provided under the silicon oxide film as a stopper layer for wet etching of the silicon oxide film, the silicon oxide film is wet-etched and further By processing the silicon nitride film by dry etching, a via hole having a desired shape can be formed in the interlayer insulating film formed of the silicon oxide film and the silicon nitride film with good reproducibility.

Further, according to the present invention, since it is possible to increase the film thickness of the interlayer insulating film, the interlayer capacitance of the interlayer insulating film is reduced and the operating speed of the semiconductor integrated circuit device is improved. You can

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 10 is a graph showing etching rates of a silicon oxide film and a silicon nitride film formed by a plasma CVD method with respect to a fluorine-based etching solution.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Film 3 Lower Wiring 4 Silicon Nitride Film 5 Silicon Oxide Film 6 Photoresist 7 Via Hole 8 Upper Wiring 9 Lower Silicon Oxide Film 10 Silicon Nitride Film 11 Upper Silicon Oxide Film 12 Lower Silicon Nitride Film 13 Silicon Oxide Film 14 Upper Layer Silicon nitride film 15 Photoresist

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 21/306 D (72) Inventor Shinichi Tanabe 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hiritsu Super LSI Engineering Co., Ltd. (72) Inventor Mitsuaki Horiuchi 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (8)

[Claims] 1. A semiconductor integrated circuit device in which a via hole for connecting wirings arranged above and below with an interlayer insulating film interposed therebetween is formed in the interlayer insulating film, wherein the interlayer insulating film is a silicon oxide film. And a semiconductor integrated circuit device comprising a silicon nitride film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a silicon nitride film and a silicon oxide film are sequentially deposited on the underlying wiring, and the patterned resist is used as a mask. A method of manufacturing a semiconductor integrated circuit device, wherein the silicon oxide film is processed by wet etching, and then the silicon nitride film is processed by dry etching. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a lower layer silicon nitride film, a silicon oxide film and an upper layer silicon nitride film are sequentially deposited on a wiring located in a lower layer and then patterned. The silicon oxide film is processed by wet etching using the upper silicon nitride film as a mask, the lower silicon nitride film is subsequently processed by dry etching, and then the upper silicon nitride film is removed. Method for manufacturing semiconductor integrated circuit device. 4. A semiconductor integrated circuit device in which via holes for connecting wirings arranged above and below with an interlayer insulating film interposed therebetween are formed in the interlayer insulating film, wherein the interlayer insulating film is an upper layer silicon oxide. A semiconductor integrated circuit device comprising a film, a silicon nitride film, and a lower silicon oxide film. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein a lower layer silicon oxide film, a silicon nitride film and an upper layer silicon oxide film are sequentially deposited on the wiring located in the lower layer and then patterned. A method of manufacturing a semiconductor integrated circuit device, wherein the upper layer silicon oxide film is processed by wet etching using a resist as a mask, and then the silicon nitride film and the lower layer silicon oxide film are sequentially processed by dry etching. . 6. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the silicon nitride film is used as a stopper layer during wet etching of the silicon oxide film. Manufacturing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the lower silicon nitride film is used as a stopper layer during wet etching of the silicon oxide film. Device manufacturing method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the silicon nitride film is used as a stopper layer during wet etching of the upper silicon oxide film. Device manufacturing method.