JPH09246381A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Problem] Since a diffusion layer is designed with a margin for alignment with a contact hole, it hinders miniaturization. Further, the lateral diffusion of the diffusion layer is promoted by the heat treatment after the diffusion layer is formed, and the short channel effect is increased. In addition, junction defects occur due to crystal defects in the semiconductor substrate near the element isolation film,
The data retention characteristics of DRAM deteriorate. A gate (22) is formed in a device forming region (13) provided on a semiconductor substrate (11) via a gate insulating film (21), an interlayer insulating film (31) is formed on the entire surface on the gate (22) side, and then a gate
After forming a contact hole 32 in the interlayer insulating film 31 on at least one side or both sides of the gate 22 so as to be circumscribed to the gate 22 or to overlap with one side wall of the gate 22, the semiconductor substrate 11 is formed from the contact hole 32. Impurities are introduced to form the n-type diffusion layer 26. Contact hole
When the element isolation film is formed on the bottom of 32, the element isolation film is removed and then the diffusion layer is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a semiconductor device is
Dynamic random access memory (hereinafter referred to as DRAM
Will be described with reference to FIG.

As shown in FIG. 4A, a local oxidation method [eg, LOCOS (Local Oxidation of Silicon)]
Method, a device isolation film 112 is formed on the p-type silicon substrate 111 (or p-well) by 100 nm to 800 nm.
The element formation region 113 is formed to have a predetermined film thickness within a certain range.
Is separated. Then, the gate oxide film 114 is set to 3 nm to 30 nm.
It is formed to have a predetermined film thickness in the range of about nm, and then the gate 115 made of polycrystalline silicon is formed.

After that, after forming a resist film (not shown) having an opening in a region to be an n-channel, for example, phosphorus ions (P ⁺ ) and By introducing impurities (here, for example, arsenic ions) for forming an n-type semiconductor such as arsenic ions (As ⁺ ),
A low concentration n-type diffusion layer 116 is formed.

Then, a silicon oxide-based film or a silicon nitride-based film is formed to a predetermined thickness in the range of about 30 nm to 400 nm by a chemical vapor deposition (hereinafter, CVD is an abbreviation for Chemical Vapor Deposition) method. After the formation, the entire surface is etched by an anisotropic etching technique such as reactive ion etching. Then, on each side wall of the gate 115, a sidewall insulating film 11 made of a silicon oxide based film or a silicon nitride based film is formed.
7 is formed.

After forming a resist film (not shown) having an opening in the region to be an n-channel again, phosphorus ions (P ⁺ ) and arsenic ions are formed by a doping technique using the resist film as a mask, for example, by ion implantation. Impurities such as (As ⁺ ) for forming an n-type semiconductor (here, for example, arsenic ions) are introduced to form a high-concentration n ⁺ -type diffusion layer 118. The n ⁺ type diffusion layer 1
There is also a case where only the n-type diffusion layer 116 is formed without forming 18.

Then, as shown in (2) of FIG.
Method, a silicon oxide-based low-melting-point interlayer insulating film 121 is formed on the entire surface of each gate 115 side by 50 nm to 800 n.
After the film is formed to have a predetermined film thickness in the range of about m, it is heated and reflowed to flatten the surface. Alternatively, the silicon oxide-based low-melting-point interlayer insulating film 121 is formed by a CVD method.
After forming to a predetermined film thickness in the range of nm to 800 nm,
It is also possible to perform flattening by etching back or chemical mechanical polishing (hereinafter, referred to as CMP, CMP is an abbreviation for Chemical Mechanical Polising).

Subsequently, as shown in FIG. 4C, a resist film 131 is formed on the interlayer insulating film 121 by a coating method, and then the n ⁺ type diffusion layers 118 (118a), 118 are formed by a lithography technique. Opening patterns 132 (132a, 132b) for forming node contact holes are formed in the resist film 131 on (118c). At this time, each opening pattern 132 is formed in the n-type diffusion layer 1
16 and the n ⁺ -type diffusion layer 118 (118a, 118c) must be formed so as not to extend over the combined region. This is because, when forming the opening pattern 132, a misalignment margin is taken into consideration in consideration of misalignment with respect to the combined region of the n-type diffusion layer 116 and the n ⁺ -type diffusion layer 118.

Then, as shown in FIG. 4 (4), by anisotropic etching such as reactive ion etching,
Node contact holes 122 (122a, 12a) reaching the n ⁺ type diffusion layers 118a, 118c are formed in the interlayer insulating film 121.
2b) is formed, and then the resist film 131 is removed. (4) of the figure shows a state in which the resist film 131 is removed.

Then, as shown in FIG. 4 (5), a storage electrode 141 made of polycrystalline silicon doped with a high concentration of an n-type impurity is formed on each node contact hole 122 and the surrounding interlayer insulating film 121. Form. Although not shown, a DRAM memory cell is formed by subsequently forming a dielectric film and a plate electrode on the surface of the storage electrode 141 and further forming a bit line.

[0011]

However, the conventional manufacturing method has the following problems. That is, (1) the active region (the n ⁺ type diffusion layer in the above-mentioned conventional example) must have a margin for alignment with the node contact hole. That hinders miniaturization. (2) Since the diffusion layer spreads in the so-called lateral direction by the heat treatment process, the short channel effect becomes large. That hinders the miniaturization of the gate. That is, it is necessary to reduce the heat treatment process after forming the diffusion layer. (3) Crystal defects occur in the semiconductor substrate near the bird's beak due to the stress generated near the so-called bird's beak during LOCOS oxidation. Junction leakage occurs due to this crystal defect, which deteriorates the data retention characteristics of the DRAM.

[0012]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems. That is, after performing a step of forming a gate in an element formation region provided on a semiconductor substrate via an insulating film, a step of forming an interlayer insulating film on the entire surface of the semiconductor substrate on the gate side is performed. Then, a step of forming a contact hole is formed in at least one side or both sides of the gate so as to be in contact with the gate or to overlap the side portion of the gate. Then, a step of forming a diffusion layer by doping impurities into the semiconductor substrate through the contact hole is performed. When an element isolation film is formed on the bottom of the contact hole, the element isolation film is removed and then the diffusion layer is formed.

In the method of manufacturing a semiconductor device described above, a contact hole is formed in at least one side or both sides of the gate so as to be in contact with the gate or overlap the side of the gate, and the contact hole is formed from the contact hole. Since the semiconductor substrate is doped with impurities to form the diffusion layer, the diffusion layer is formed in self-alignment with the contact holes. Therefore, it is not necessary to have a margin for alignment with the contact hole when forming the diffusion layer as in the conventional case. Further, since the diffusion layer is formed after forming the interlayer insulating film, the heat process applied to the diffusion layer is reduced. Further, since the diffusion layer is formed at the end of the element isolation film, the region where crystal defects are generated in the semiconductor substrate due to the stress due to the bird's beak of the element isolation film is included in the diffusion layer, so that a junction leak occurs. Can be suppressed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An example of the first embodiment of the present invention will be described with reference to the manufacturing process chart of FIG. FIG. 1 shows, as an example, a manufacturing process of a DRAM memory cell.

As shown in FIG. 1A, a gate oxide film 21 having a thickness of 3 nm to 30 nm is formed on a semiconductor substrate (for example, a p-type silicon substrate or a substrate on which a p-well is formed) 11.
It is formed to have a predetermined film thickness within a certain range. Subsequently, the gate 22 (22a, 22b) made of polycrystalline silicon is formed.
The gate 22 serves as a word line in a memory cell of DRAM, and can be formed, for example, in a so-called polycide structure.

Then, after forming a resist film (not shown) having an opening in the region between the gates 22a and 22b, phosphorus ions (P) are formed by, for example, an ion implantation method as a doping technique using the resist film as a mask. ⁺ )
Then, an impurity (here, for example, arsenic ion) for forming an n-type semiconductor such as arsenic ion (As ⁺ ) is introduced to form the low-concentration n-type diffusion layer 23. afterwards,
The resist film is removed.

Then, a silicon oxide-based film or a silicon nitride-based film is deposited to 30 nm to 400 nm by the CVD method.
After forming a predetermined film thickness within a certain range, the entire surface is etched by an anisotropic etching technique such as reactive ion etching. Then, a sidewall insulating film 24 made of a silicon oxide based film or a silicon nitride based film is formed on the side wall of the gate 22.

After again forming a resist film (not shown) having an opening in the region between the gates 22a and 22b,
As a doping technique using the resist film as a mask,
For example, by an ion implantation method, impurities (here, for example, arsenic ion) for forming an n-type semiconductor such as phosphorus ion (P ⁺ ) and arsenic ion (As ⁺ ) are introduced, and the n-type diffusion formed previously is introduced. An n ⁺ type diffusion layer 25 having a higher concentration than the layer 23 is formed. Then, the resist film is removed. Note that the diffusion layer may be the n-type diffusion layer 23 alone without forming the n ⁺ -type diffusion layer 25.

Then, as shown in (2) of FIG.
Method, a low-melting silicon oxide-based interlayer insulating film 31 having a thickness of 50 nm to 800 nm is formed on the entire surface on the side of each gate 22.
After the film is formed to a predetermined film thickness within a certain range, it is heated and reflowed to flatten the surface. Alternatively, a silicon oxide-based low-melting-point interlayer insulating film 31 having a thickness of 50 n is formed by a CVD method.
It is also possible to perform flattening by etching back or CMP after forming a predetermined film thickness in the range of about m to 800 nm.

Subsequently, as shown in FIG. 1C, a resist film 41 is formed on the interlayer insulating film 31 by a coating method, and then the resist film 41 is formed on a region to be a node contact by the lithography technique. Opening pattern 4
2 (42a, 42b) is formed. At this time, the opening pattern 42a is formed in a state of being circumscribed in a plan view with respect to a side wall of the gate 22a opposite to the gate 22b, or in a so-called overlapping state in a plan view. Forming the opening pattern 42b to the gate 22b
It is necessary to form a state in which the side wall of the above is circumscribing in a plan view with respect to a side wall opposite to the gate 22a, or is formed in a so-called overlapping state in a plan view. In this figure, when viewed in a plan view, the opening pattern 42a is formed so as to circumscribe a side wall of the gate 22a opposite to the gate 22b (hereinafter referred to as an outer side wall). Of the side walls of the gate 22b, the side wall opposite to the gate 22a (hereinafter referred to as the outer side wall) is formed so as to be circumscribed.

After that, anisotropic etching such as reactive ion etching is performed using the resist film 41 as a mask, and as shown in FIG.
Contact holes (here, node contact holes) 32 reaching the semiconductor substrate 11 (32a, 32b)
To form The contact hole 32 (32a) is
Is formed so as to be circumscribed on the outer side wall of the gate 22a,
The contact hole 32 (32b) is formed so as to be in contact with the outer side wall of the gate 22b. In this etching, the sidewall insulating film 2 below the opening pattern 42 is formed.
4 [shown in (3) of the above figure] is also etched, and the side wall outside the gate 22 is exposed. Then, the resist film 41 is removed.

As a matter of course, the formation position of the contact hole 32 changes depending on the formation position of the opening pattern 42 shown in (3) of FIG. In the example described above, the outer sidewall of the gate 22 and the contact hole 32 are formed in contact with each other. However, for example, the outer sidewall of the gate 22 and the contact hole 32 are formed in a so-called overlapping state. May be.

Then, as shown in FIG. 1 (5), impurities for forming an n-type semiconductor such as phosphorus (P) and arsenic (As) are formed through the contact hole 32 by the ion implantation method. Introduced in 11.
Then, a diffusion layer (hereinafter referred to as an n-type diffusion layer) 26 is formed. Further, in the above-mentioned ion implantation, the interlayer insulating film 31 serves as a mask, and therefore a resist film is not formed and patterned to form a mask.

First, the n-type diffusion layer 23 and n
Without forming the ⁺ type diffusion layer 25, the gates 22a and 22b are formed.
In the same manner as above, an opening is formed in the resist film 41, and a contact hole is formed in the interlayer insulating film 31 through the opening. Then, the n-type diffusion layer 23 may be formed on the semiconductor substrate 11 through the contact hole.

In the manufacturing method of the first embodiment described above, the contact hole 32 is formed in the interlayer insulating film 31 so as to circumscribe or overlap the outer sidewall of the gate 22,
Since the semiconductor substrate 11 is doped with impurities from the contact hole 32 to form the n-type diffusion layer 26,
The n-type diffusion layer 26 is formed in self-alignment with the contact hole 32. Therefore, when forming the n-type diffusion layer 26, it is not necessary to have a margin for alignment with the contact hole 32 as in the conventional case. Further, the n-type diffusion layer 26 is formed in self alignment with the gate 22.
This is because the gate 22 serves as a mask during ion implantation even if the contact hole 32 is formed so as to overlap the gate 22. Further, since the n-type diffusion layer 26 is formed after the interlayer insulating film 31 is formed, the heat process applied to the n-type diffusion layer 26 is reduced.

Next, an example of the second embodiment will be described with reference to the manufacturing process diagram of FIG. In FIG. 2, as an example, DRA
The manufacturing process of the M memory cell is shown, and the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 2A, the element isolation film 12 (12) is formed on the p-type silicon substrate 11 (or p well) by the local oxidation method (eg, LOCOS method).
a, 12b) is formed to a predetermined film thickness in the range of about 100 nm to 800 nm to separate the element formation region 13. Then, a gate oxide film 21 is formed with a predetermined film thickness in the range of about 3 nm to 30 nm, and then a gate 22 (22a, 22b) made of polycrystalline silicon is formed on one end of the element isolation film 12 at one end thereof. Are formed so that the side portions of the contact. That is, the gate 22a is formed at the end of the device isolation film 12a.
The gate 12a is formed in a state where the side portions of the gate 22b contact each other, and the gate 12b is formed in a state where the side portion of the gate 22b contacts the end portion of the element isolation film 12b. In addition, each gate 22
It becomes a word line in a memory cell of a DRAM, and can be formed by a so-called polycide structure, for example. In the above description, the edge of the element isolation film 12 and the gate 22 are
Although the example of the state where the side surface of the element contacts the side surface of the element separation film 1 has been described.
The gate 22 may be formed in a state in which the end portion of 2 and the side portion of the gate 22 are apart from each other by a predetermined distance. This predetermined distance is set to a distance smaller than the diameter of a contact hole formed later, for example.

After that, a low concentration n-type diffusion layer 23 is formed on the semiconductor substrate 11 between the gates 22a and 22b in the same manner as described in the first embodiment. Then CV
After a silicon oxide-based film or a silicon nitride-based film is formed by the D method, the entire surface is etched back to form a sidewall insulating film 24 made of a silicon oxide-based film or a silicon nitride-based film on the sidewall of the gate 22. To form. Further, an n ⁺ type diffusion layer 25 having a higher concentration than the n type diffusion layer 23 previously formed is formed on the semiconductor substrate 11 between the gates 22a and 22b. Note that the diffusion layer may be the n-type diffusion layer 23 alone without forming the n ⁺ -type diffusion layer 25.

Then, in the same manner as described in the first embodiment, as shown in (2) of FIG.
A low melting point interlayer insulating film 3 made of silicon oxide is formed on the entire surface on the second side.
1 is formed to have a predetermined film thickness in the range of about 50 nm to 800 nm, then heated and reflowed to flatten the surface.
Alternatively, it is also possible to form the silicon oxide-based low-melting-point interlayer insulating film 31 with a predetermined film thickness in the range of about 50 nm to 800 nm by the CVD method, and then perform flattening by etching back or CMP.

Then, in the same manner as described in the first embodiment, as shown in FIG. 2C, a resist film 41 is formed on the interlayer insulating film 31 by a coating method. After that, an opening pattern 4 is formed in the resist film 41 on the region where the node contact is to be formed by a lithography technique.
2 (42a, 42b) is formed. Here, as an example, in plan view, the opening pattern 42a is formed so as to be in contact with the sidewall of the gate 22a on the element isolation film 12a side (hereinafter referred to as the outer sidewall), and the opening pattern 42b is formed.
Is formed so as to be in contact with the sidewall of the gate 22b on the element isolation film 12b side (hereinafter referred to as the outer sidewall).

After that, anisotropic etching such as reactive ion etching using the resist film 41 as a mask is performed, and as shown in FIG.
A contact hole (here, a node contact hole) 32 (32a, 32b) is formed. The contact hole 32a is formed so as to be in contact with the outer side wall of the gate 22a, and the contact hole 32b is formed in the gate 2a.
It is formed to be in contact with the outer side wall of 2b. In this etching, the sidewall insulating film 24 (shown in FIG. 3) and the element isolation film 12 below the opening pattern 42 are formed.
The semiconductor substrate 11 (shown in FIG. 3) is also removed by etching so that the sidewalls outside the gate 22 are exposed.
Appears. Therefore, the so-called bird's beak portion of the element isolation film 12 is removed by this etching. Then, the resist film 41 is removed.

As a matter of course, the formation position of the contact hole 32 changes depending on the formation position of the opening pattern 42 shown in (3) of the figure. In the example described above, the gate 2
Although the outer sidewall of 2 and the contact hole 32 are formed in contact with each other, for example, the outer sidewall of the gate 22 and the contact hole 32 may be formed in a so-called overlapping state. Also in this case, similarly to the above, the sidewall insulating film 2 below the opening pattern 42 is formed.
4 and the element isolation film 12 are also removed by etching, and the side wall outside the gate 22 is exposed and the semiconductor substrate 11 is exposed. Therefore, the so-called bird's beak portion of the element isolation film 12 is also removed.

Then, in the same manner as described in the first embodiment, as shown in (5) of FIG. 1, ion implantation is performed through the contact hole 32 to remove, for example, phosphorus (P) and arsenic (As). Impurities for forming such an n-type semiconductor are introduced into the semiconductor substrate 11. Then, the n-type diffusion layer 26 is formed. Here, since the interlayer insulating film 31 serves as a mask, a resist film is not formed and patterned to form a mask.

First, the n-type diffusion layers 23 and n
Without forming the ⁺ type diffusion layer 25, the gates 22a and 22b are formed.
In the same manner as above, an opening is formed in the resist film 41, and a contact hole is formed in the interlayer insulating film 31 through the opening. Then, the n-type diffusion layer 23 may be formed on the semiconductor substrate 11 through the contact hole.

In the manufacturing method of the second embodiment, as in the case of the first embodiment, there is no need to make a margin for the contact hole 32 when forming the diffusion layer 26, and the n-type diffusion layer is formed. The heat steps added to 26 are reduced. At the same time, since the n-type diffusion layer 26 is formed at the end of the element isolation film 12, the crystal defects generated by the LOCOS oxidation are included in the n-type diffusion layer 26. Therefore, the occurrence of junction leak can be suppressed.

Next, an example of the third embodiment will be described with reference to the manufacturing process diagram of FIG. As an example, FIG. 3 shows a continuation of the manufacturing process of the memory cell of the DRAM described with reference to FIG. 2, and the same components as those described in the first and second embodiments are designated by the same reference numerals.

As shown in FIG. 3A, after a silicon oxide-based or silicon nitride-based insulating film is formed to a predetermined thickness in the range of about 5 nm to 50 nm by the CVD method,
Anisotropic etching such as reactive ion etching is performed on the entire surface. Then, the sidewall insulating film 33 is formed on the sidewall of the contact hole 32. Then, an impurity such as phosphorus (P) and arsenic (As) for forming an n-type semiconductor is introduced into the semiconductor substrate 11 through the contact hole 32 by an ion implantation method. Then, the n ⁺ type diffusion layer 27 having a higher concentration than the n type diffusion layer 26 formed previously is formed. Therefore, the formed n-type diffusion layer 26 becomes a so-called LDD diffusion layer. Further, in the above ion implantation, the interlayer insulating film 31 and the sidewall insulating film 33 serve as a mask, and therefore a resist film is not formed and patterned to form a mask. The n ⁺ type diffusion layer 27 may not be formed and only the n type diffusion layer 26 may be formed.

Then, as shown in FIG. 3B, the storage electrode 51 made of a conductor is formed on the contact hole 32 and the interlayer insulating film 31 around the contact hole 32. This conductor is
For example, it is made of polycrystalline silicon that is highly doped with n-type impurities. Of course, it is also possible to form other conductors such as metals or metal-based compounds.
Here, an example of a method of forming the storage electrode 51 made of polycrystalline silicon will be described. First, a CVD method is used to fill the contact holes 32 and form a polycrystalline silicon film on the interlayer insulating film 31. After that, n-type impurities are ion-implanted into the entire surface to make the conductivity type of the polycrystalline silicon n-type. Then, the polycrystal silicon film is patterned by a lithography technique and an etching technique to form a storage electrode 51. Alternatively, the storage electrode 51 may be formed by forming a polycrystalline silicon film containing an n-type impurity by a CVD method and then performing patterning.

Although not shown, a DRAM memory cell is formed by subsequently forming a dielectric film and a plate electrode on the surface of the storage electrode 51 and further forming a bit line.

Further, in the third embodiment, after the sidewall insulating film 33 is formed, the following steps may be performed without introducing the impurities by the ion implantation method described above.
That is, as described above, after the storage electrode 51 made of polycrystalline silicon heavily doped with impurities is formed, or inside the contact hole 32, polycrystalline silicon made of polycrystalline silicon heavily doped with impurities is formed. After forming the silicon plug (not shown), impurities may be diffused from the storage electrode 51 or the polycrystalline silicon plug to form the high-concentration n ⁺ type diffusion layer 27.

In the manufacturing method of the third embodiment, the side wall insulating film 33 is formed on the side wall of the contact hole 32 so that the n-type diffusion layer 26 previously formed is a so-called LDD (Lightly Doped Drain). Will be possible. Therefore, the hot carrier effect is suppressed.

[0042]

As described above, according to the present invention,
Since the diffusion layer is formed on the semiconductor substrate through the contact hole, the diffusion layer can be formed in self-alignment with the contact hole. Therefore, when forming the diffusion layer, it is not necessary to consider misalignment with the contact hole, so that the diffusion layer can be reduced in size. Therefore, the area of the memory cell can be reduced, and further miniaturization can be promoted. Further, according to the manufacturing method of forming the diffusion layer after forming the interlayer insulating film, the diffusion layer is formed after the conventional process, so that the number of heat treatment steps applied to the diffusion layer is reduced. Therefore, the lateral diffusion of impurities in the diffusion layer is reduced as compared with the conventional case, and the short channel effect is suppressed. Therefore, since the gate can be reduced, the size of the memory cell can be reduced and further miniaturization can be achieved. Further, according to the manufacturing method in which the element isolation film in the contact hole is removed and the diffusion layer is formed in the semiconductor substrate in the removed region, the crystal defect caused by the stress generated in the semiconductor substrate in the vicinity of the bird's beak of the element isolation film. Are contained by the diffusion layer. Therefore, the junction leak caused by the crystal defect can be suppressed, and the data retention characteristic of the DRAM can be improved.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a first embodiment according to the present invention.

FIG. 2 is a manufacturing process drawing of the second embodiment according to the present invention.

FIG. 3 is a manufacturing process drawing of the third embodiment according to the present invention.

FIG. 4 is a manufacturing process diagram illustrating a conventional technique.

[Explanation of symbols]

11 semiconductor substrate 12 element isolation film 13 element formation region 22 gate 26 n-type diffusion layer 31 interlayer insulating film 32 contact hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display part H01L 29/78 21/336

Claims (9)

[Claims] 1. A step of forming a gate in an element formation region provided on a semiconductor substrate via an insulating film, a step of forming an interlayer insulating film so as to cover the entire surface of the semiconductor substrate on the gate side, the gate A step of forming a contact hole in the interlayer insulating film on at least one side or both sides thereof in a state of circumscribing the side wall of the gate or overlapping with a side portion of the gate, and impurities from the contact hole into the semiconductor substrate. And a step of forming a diffusion layer by doping the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the gate, an element isolation film for isolating the element formation region is formed on the semiconductor substrate, and then an edge of the element isolation film is formed. In the step of forming the gate and forming the contact hole in a state in which one side of the gate is in contact with the portion or in a state in which the end of the element isolation film and one side of the gate are separated by a predetermined distance, After forming a contact hole in the interlayer insulating film at least on the element isolation film side of the gate so as to be in contact with the gate or to overlap the side portion of the gate, the element isolation film at the bottom of the contact hole is further removed. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the gate, an element isolation film for isolating the element formation region is formed on the semiconductor substrate, and then an edge of the element isolation film is formed. In the step of forming the gate and forming the contact hole in a state in which one side of the gate is in contact with the portion or in a state in which the end of the element isolation film and one side of the gate are separated by a predetermined distance, A contact hole is formed in the interlayer insulating film on both sides of the gate so as to be circumscribed to the gate or to overlap a side portion of the gate, and then the element isolation film at the bottom of the contact hole is removed. A method for manufacturing a characteristic semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a sidewall insulating film on a side wall of the contact hole. 5. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming a sidewall insulating film on a side wall of the contact hole. 6. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a sidewall insulating film on a side wall of the contact hole. 7. The method of manufacturing a semiconductor device according to claim 4, wherein before forming a sidewall insulating film on the sidewall of the contact hole, the semiconductor substrate is doped with an impurity from the contact hole to form a low concentration diffusion layer. And a step of forming a high-concentration diffusion layer by forming a sidewall insulating film on the sidewall of the contact hole and then doping an impurity into the semiconductor substrate through the contact hole. Of manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 5, wherein, before forming a sidewall insulating film on the sidewall of the contact hole, the semiconductor substrate is doped with impurities from the contact hole to form a low concentration diffusion layer. And a step of forming a high-concentration diffusion layer by forming a sidewall insulating film on the sidewall of the contact hole and then doping an impurity into the semiconductor substrate through the contact hole. Of manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 6, wherein, before forming a sidewall insulating film on the sidewall of the contact hole, the semiconductor substrate is doped with an impurity through the contact hole to form a low concentration diffusion layer. And a step of forming a high-concentration diffusion layer by forming a sidewall insulating film on the sidewall of the contact hole and then doping an impurity into the semiconductor substrate through the contact hole. Of manufacturing a semiconductor device.