JPH09246872A - Bias stabilization circuit for transistor - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To attach an output matching circuit externally without increasing the number of terminals as compared with the case of incorporating an output matching circuit without incorporating a bias stabilizing circuit and an output matching circuit. To realize the IC. A bias stabilization circuit includes a power supply terminal.
3 and a resistor R _e1 provided between the drain of the FET 15 and
And a transistor 17 for negatively feeding back the voltage drop across the resistor R _e1 to the bias for the FET 15, and a resistor R
_The resistor R _e2 is provided between _e1 and the emitter of the transistor 17, and the capacitor C _e is provided between the resistor R _e2 and the ground terminal 14. An output matching circuit 30 is externally attached to the output terminal 12 of the MMIC 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor bias stabilization circuit for stabilizing the bias of a transistor in, for example, a monolithic microwave integrated circuit.

[0002]

2. Description of the Related Art A monolithic microwave integrated circuit (hereinafter referred to as MMIC) having a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as gallium arsenide and a silicon MOS (metal oxide semiconductor) FET. .) Has excellent high frequency characteristics and low noise,
It is widely used in high frequency systems represented by mobile communications. In equipment in such high frequency systems,
It is very important to suppress the fluctuation of the operating current of an integrated circuit (hereinafter referred to as IC) in order to secure the performance of the IC and improve the usability.

From the viewpoint of preventing the fluctuation of the operating current as described above, an MMIC incorporating a bias stabilizing circuit has been proposed as disclosed in, for example, Japanese Patent Laid-Open No. 6-283942. An example of the configuration of such an MMIC is shown in FIG. The MMIC 100 uses a single positive power supply. The MMIC 100 includes an input terminal 101 for inputting a radio frequency (hereinafter referred to as RF) input signal, an output terminal 102 for outputting an RF output signal, a power supply terminal 103, a ground terminal 104, and a gallium. An FET 105 using a compound semiconductor such as arsenic, an input matching circuit 106 provided between the input terminal 101 and the gate of the FET 105 for obtaining gain and input impedance matching in a desired frequency band, and an FET 1
05, and an output matching circuit 107 for gain and output impedance matching in a desired frequency band, and a power supply terminal 103.
And a bias stabilizing circuit 108 that is connected to the output matching circuit 107 and applies a bias to the FET 105 and stabilizes the bias, and a bias stabilizing circuit 108 and F.
It has a resistor 109 provided between the gate of the ET 105. The source of the FET 105 is connected to the ground terminal 104. The power supply terminal 103 is connected to a positive power supply and grounded via an external bypass capacitor C _vdd . The ground terminal 104 is designed to be grounded.

The input matching circuit 106 has one end at the input terminal 1
01, the other end of which is connected to the gate of the FET 105, the coil 111 whose one end is connected to the gate of the FET 105, one end of which is connected to the other end of the coil 112, and the other end of which is connected to the ground terminal 104. And a condenser 113.

The output matching circuit 107 has the FET 10 at one end.
5, a capacitor 114 having the other end connected to the output terminal 102, a coil 115 having one end connected to the drain of the FET 105, one end connected to the other end of the coil 115, and the other end connected to the ground terminal 104. And a connected capacitor 116.

The bias stabilizing circuit 108 includes a PNP bipolar transistor 117, a resistor R ₁ having one end connected to the base of the transistor 117 and the other end connected to the ground terminal 104, and one end connected to the base of the transistor 117. And a resistor R ₂ whose other end is connected to the power supply terminal 103
A resistor R _e having one end connected to the emitter of the transistor 117 and the other end connected to the power supply terminal 103, and a resistor R _c having one end connected to the collector of the transistor 117 and the other end connected to the ground terminal 104. Have Resistance R _e
And the emitter of the transistor 117 are connected to the connection point between the coil 115 and the capacitor 116 of the output matching circuit 107. The collector of the transistor 117 is connected to one end of the resistor 109, and the other end of the resistor 109 is connected to the gate of the FET 105.

The bias stabilizing circuit 108 shown in FIG.
Since it is not necessary to provide a bypass capacitor on the source side as compared with a bias stabilization circuit using a self-bias method in which a resistor is provided between the source of the FET 105 and the ground terminal 104, the chip area can be reduced. . In the self-bias method, in order to prevent the distortion characteristics from deteriorating, it is necessary to increase the capacitance of the bypass capacitor to some extent depending on the circuit form of the output matching circuit 107. In that case, in order to avoid an increase in the chip area. In some cases, a bypass capacitor may be attached externally. However, in this case, a terminal for connecting an external bypass capacitor is provided on the source side of the FET 105, and there is a drawback that the number of pins is increased in the usual case where the FET 105 is mounted alone in a package.

The operation of the bias stabilizing circuit 108 shown in FIG. 3 will be described. First, as shown in FIG. 3, the power supply voltage V _dd, the current passing through the power supply terminal 103 I _total, the resistance R _e and voltage V _d at the point A which is the connection point between the emitter of the transistor 117, A The current flowing from the point to the drain side of the FET 105 through the output matching circuit 107 is I _dd , the emitter current of the transistor 117 is I _e , the base current is I _b , the collector current is I _c , the base-emitter diffusion potential is V _be , and the FET 107 is Let the DC gate bias voltage of V _gg be V _gg . As a general use condition of the MMIC 100, the DC gate bias voltage V _gg of the FET 105 is smaller than the gate forward turn-on voltage of the FET 105, and the gate current is sufficiently small. Therefore, the collector voltage of the transistor 117 is also V
It will be _gg .

Under the above conditions, the bias stabilizing circuit 10
8, the following three relational expressions (a1) to (a3) are established. In the following equation, the resistances R ₁ , R ₂ , R _e , R
The resistance values of _c are R ₁ , R ₂ , R _e , and R _c , respectively.

[0010]

[Number 1] _{V dd -V d = (I dd} + I e) · R e ... (a1) V dd -V d = (I total -I e -I dd) · R 2 -V be ... (a2) V _dd = (I _total −I _e −I _dd ) · R ₂ + (I _total −I _e −I _dd + I _b ) · R ₁ (a3)

The equation (a1) expresses the voltage drop across the resistor R _e as V _dd
Expression represented by −V _d , Expression (a2) is an expression represented by V _dd −V _d by a voltage drop across the resistor R ₂ and V _be, and Expression (a3) is represented by the resistance R ₁ ,
It is an expression showing that the sum of the voltage drops of R ₂ is equal to the power supply voltage V _dd .

Below, V _d and I are calculated from the equations (a1) to (a3).
Delete _total . First, the following (a
Equation 4) holds.

[0013]

(I _total −I _e −I _dd ) (R ₁ + R ₂ ) = V _dd −I _b R ₁ ∴I _total −I _e −I _dd = (V _dd −I _b R ₁ ) / (R ₁ + R ₂ ) ... (a4)

From the expressions (a1), (a2) and (a4), the following expression is established.

[0015]

[Number 3] _{(V dd -I b R 1)} R 2 / (R 1 + R 2) -V
_{be = I dd R e + I} e R e

Here, I _e = I _b + I _c , I _b = I _c /
Since h _fe (however, h _fe is the direct current amplification factor), the above equation is as follows.

[0017]

Equation 4] _{R 2 V dd / (R 1} + R 2) - {R 1 R 2 / (R 1 + R 2)} · (1 / h fe) · I c -V be = I dd R e + (R _e / h _fe ) · I _c + R _e I _c ∴I _c = [R ₂ V _dd / (R ₁ + R ₂ ) −V _be −R _e I _dd ] / [R _e + (1 / h _fe ) {R _e + R ₁ R ₂ / (R ₁ + R ₂ )}] ... (a5)

From the collector of the transistor 117 to the resistor 1
Since the 09 side has high impedance, V _gg = R _c I _c
By substituting the equation (a5) into this, the following equation is obtained.

[0019]

[Equation 5] R _e I _dd / [R _e + (1 / h _fe ) {R _e + R ₁
R ₂ / (R ₁ + R ₂ )}] = − V _gg / R _c + [R ₂ V _dd
/ (R ₁ + R ₂ ) -V _be ] / [R _e + (1 / h _fe ) {R
_e + R ₁ R ₂ / (R ₁ + R ₂ )}]

The above equations are organized into the following equations (1) to (3). Further, the gate voltage-drain current characteristic represented by the equations (1) to (3) is shown by a characteristic line 141 in FIG.

[0021]

(6) I _dd = -mV _gg + n (1) m = [R _e + (1 / h _fe ) {R _e + R ₁ R ₂ / (R ₁ + R ₂ )}] / R _{c Re} ... ( _{2) n = [R 2 V} dd / (R 1 + R 2) -V be] / R e ... (3)

On the other hand, the drain current I of the FET 105
_dd is approximated by the following characteristic equation (4). In addition,
In the equation (4), V _th is the threshold of the FET 105, k
Is a constant determined by the gate length, electron mobility, and gate capacitance of the FET 105. Further, the characteristic represented by the equation (4) is shown by a characteristic line 142 in FIG.

[0023]

## _EQU00007 ## I _dd = k (V _gg -V _th ) ² (4)

The drain current I _dd actually obtained is shown in FIG.
Current I _{0 at} the intersection of the characteristic lines 141 and 142 in
Becomes Therefore, in order to suppress the fluctuation of I _dd due to the variation of the threshold value V _th of the FET 105, it is necessary that the slope −m in the expression (1) be as small as possible. For example, the resistance values of the resistors R ₁ , R ₂ , R _e , and R _c and the transistor 1 so that m is on the order of 10 ^−4.
If the DC current amplification factor h _fe of 17 is selected, even if the variation of V _th is 1 V, the fluctuation of I _dd can be suppressed to a small value of about several hundred microamperes.

[0025]

Next, as in the example shown in FIG. 3, a resistor R _e is provided between the drain of the FET 105 or its extension and the positive power source, and a voltage drop occurs at the resistor R _e. Consider the number of terminals and available packages for an MMIC of the type that incorporates an active bias stabilizing circuit that negatively feeds back using an active element. Since the MMIC 100 shown in FIG. 3 also includes the input matching circuit 106 and the output matching circuit 107, the number of IC terminals is as follows: the input terminal 101, the output terminal 102, and the power supply terminal 103.
And a ground terminal 104. For example, a 4-pin package can be used when it is mounted alone in the package.

On the other hand, in the MMIC, a type that does not include the output matching circuit 107 occupying a relatively large area in the chip is often used from the viewpoint of reducing the loss of output power and reducing the cost by reducing the chip size. Therefore, an MMIC that includes an active bias stabilizing circuit equivalent to that in FIG. 3 but does not include the output matching circuit 107.
Considering this, this is shown in FIG.

In the MMIC 120 shown in FIG. 5, the output matching circuit 107 in the MMIC 100 shown in FIG. 3 is deleted and the output matching circuit 130 is externally attached. Therefore, the MMIC 120 is newly provided with a voltage drop monitor terminal 121. The voltage drop monitoring terminal 121 is connected to a connection point between the resistor R _e and the emitter of the transistor 117. Also, output terminal 1
The drain of the FET 105 is connected to 02. On the other hand, the output matching circuit 130 has a capacitor 131 having one end connected to the output terminal 102 of the MMIC 120 and the other end serving as an RF signal output end, and one end of the output matching circuit 130 of the MMIC 120.
02, the other end of which is connected to the voltage drop monitor terminal 121 of the MMIC 120, and one end of which is the MMIC
It has a capacitor 133 connected to the voltage drop monitor terminal 121 of the IC 120 and the other end of which is grounded.

However, in the configuration shown in FIG. 5, M
The number of terminals of the MIC 120 is five, and when packaged alone, for example, a 4-pin package can no longer be used. Therefore, in this case, it is necessary to use a package having a larger number of pins, which causes problems such as an increase in the IC package cost and an increase in the mounting area of the IC on the substrate.

The present invention has been made in view of the above problems, and its object is to provide a resistor between a transistor to be bias-stabilized and a power source, and use an active element to reduce the voltage drop at this resistor. In a bias stabilization circuit for a transistor that stabilizes the bias by negatively feeding back to the bias, the number of terminals compared to the case where this bias stabilization circuit is built-in and the output matching circuit is not built-in but the output matching circuit is built-in. Another object of the present invention is to provide a transistor bias stabilization circuit that can realize an IC in which an output matching circuit can be externally attached without increasing the number.

[0030]

According to a bias stabilizing circuit for a transistor of the present invention, one end is connected to a power source and the other end is connected to an electrode on a signal output side of a transistor to be bias-stabilized and passes through. A first resistor for detecting a voltage drop due to a bias current that operates, and an active element for negatively feeding back the voltage drop at the first resistor into a bias for a transistor to be bias-stabilized.
The second resistor is provided between the end of the transistor, which is the target of bias stabilization in the first resistor, on the signal output side of the transistor and the active element side.

In the bias stabilization circuit for this transistor, the bias is stabilized by negatively feeding back the voltage drop in the first resistor to the bias for the transistor to be bias-stabilized by using the active element.
In the bias stabilizing circuit for this transistor, the second resistor is provided between the end on the electrode side of the signal output side of the transistor which is the target of bias stabilization in the first resistor and the active element side. It is possible to directly connect the first resistor and the electrode on the signal output side of the transistor for which the bias is to be stabilized, and the number of terminals is increased by such a direct connection as compared with the case where the output matching circuit is built in. The output matching circuit can be attached externally.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a structure of an MMIC which includes a transistor bias stabilizing circuit according to an embodiment of the present invention and which constitutes a one-stage amplifier. This MMIC
10 uses a single positive power supply. This MM
The IC 10 has an input terminal 1 for inputting an RF input signal.
1 and an output terminal 12 for outputting an RF output signal,
Power supply terminal 13, ground terminal 14, FET 15 using a compound semiconductor such as gallium arsenide, input terminal 11 and FE
It is connected between the gate of T15 and the input matching circuit 16 for gain and input impedance matching in a desired frequency band, and is connected to the power supply terminal 13 and the drain of the FET 15 to bias the FET 15 and stabilize the bias. Bias stabilizing circuit 18 for
The bias stabilizing circuit 18 and a resistor 19 provided between the gate of the FET 15 are provided. The drain of the FET 15 on the signal output side is connected to the output terminal 12, and the source is connected to the ground terminal 14. The power supply terminal 13 is connected to a positive power supply and grounded via an external bypass capacitor C _vdd . The ground terminal 14 is grounded. FET15
Specifically, for example, MESFET (metal semiconductor junction type FET) or JFET (PN junction type FET) is used.

The input matching circuit 16 has an input terminal 11 at one end.
To the gate of the FET 15, the other end of which is connected to the gate of the FET 15, the coil 22 whose one end is connected to the gate of the FET 15, the one end of which is connected to the other end of the coil 22, and the other end of which is connected to the ground terminal 14. And a capacitor 23.

The bias stabilizing circuit 18 has a resistor R _e1 as a first resistor whose one end is connected to the power supply terminal 13 and the other end connected to the drain of the FET 15, and the voltage drop at this resistor R _e1 is bias-stabilized. Target FET15
As a second resistor having one end connected to the FET 15 side end of the resistor R _e1 and the other end connected to the emitter of the transistor 17 the resistor R _e2, capacitor C the other end connected to an end portion of one end transistor 17 side of the resistor R _e2 is connected to the ground terminal 14
_e , a resistor R _c having one end connected to the collector of the transistor 17 and the other end connected to the ground terminal 14, and a resistor R ₁ having _one end connected to the base of the transistor 17 and the other end connected to the ground terminal 14. , A resistor R ₂ having one end connected to the base of the transistor 17 and the other end connected to the power supply terminal 13.
And The collector of the transistor 17 is a resistor 1
9 is connected to one end, and the other end of the resistor 19 is FET 15
Connected to the gate.

An external output matching circuit 30 is connected to the output terminal 12. Output matching circuit 30
Is a capacitor 31 having one end connected to the output terminal 12 of the MMIC 10 and the other end serving as an RF signal output end,
It has a coil 32 connected to the output terminal 12 of the IC 10 and a capacitor 33 having one end connected to the other end of the coil 32 and the other end grounded.

As described above, in the MMIC 10 including the transistor bias stabilizing circuit according to the present embodiment, the drain of the FET 15 has a resistance R _e1 (resistor in FIG. 5) for voltage drop detection, as compared with the MMIC 120 shown in FIG. R
Corresponds to _e . ), A point at which a resistor R _e2 is inserted between the connection point between the resistor R _e1 and the drain of the FET 15 and the emitter of the transistor 17, and a resistor R
_The point where the capacitor C _e is provided between the ground terminal 14 and the connection point between _e2 and the emitter of the transistor 17, and accordingly, the voltage drop monitor terminal 1 in FIG.
The difference is that 21 is deleted.

Here, the reason why the voltage drop monitor terminal 121 in FIG. 5 can be eliminated by providing the resistor R _e2 and the capacitor C _e as described above will be described. First, the impedance seen from the drain of the FET 15 is the desired impedance ZL realized by the output matching circuit 30.
Therefore, the drain of the FET 15 cannot be connected to an impedance other than a sufficiently large impedance as compared with the impedance ZL. This is condition A. In the MMIC 100 shown in FIG. 3, nothing is connected to the drain of the FET 15 except the output matching circuit 107.

Further, in order to stabilize the bias of the FET 15, the bias stabilizing circuit 18 should not be affected by the drain voltage of the FET 15, that is, the high frequency fluctuation of the output signal. This is condition B.

Assuming that the resistor R _e2 and the capacitor C _e are eliminated in FIG. 1 (this is the FET 1 in FIG. 5).
This is equivalent to directly connecting the drain of No. 05 to the resistor R _e inside the IC, providing the external output matching circuit 30 shown in FIG. 1, and deleting the voltage drop monitor terminal 121. ), FET
The impedance seen by the bias stabilizing circuit 18 from the drain of the FET 15 affects the total impedance seen from the drain of the FET 15, which violates the condition A.

Even if the impedance of the bias stabilizing circuit 18 seen from the drain of the FET 15 is sufficiently large, the direct connection between the drain of the FET 15 and the bias stabilizing circuit 18 violates the condition B and is eliminated. FET1 is a ground capacitance such as a capacitor C _e
It becomes necessary to provide it on the drain side of 5, and as a result, FEE
The total impedance seen from the drain of T15 is greatly reduced, and as a result, the condition A is violated.

On the other hand, in the MMIC10 including the bias stabilizing circuit 18 according to the present embodiment, the FEET15
The total impedance seen from the drain of is capacitor C
The capacitances of _e and C _vdd are sufficiently large (capacitor C _e is in the chip, so capacitance of several picofarads, capacitor C _{e
If vdd} is a capacitance of an appropriate value higher than that, resistance R _e1
And the resistance R _e2 in parallel and the impedance ZL in parallel. Therefore, as shown in an example described later, if the resistance values of the resistors R _e1 and R _e2 are set to several hundreds to several kilo ohms, the parallel resistance of the resistors R _e1 and R _e2 does not significantly affect the impedance ZL. . That is, the condition A is satisfied. However, the parallel resistance of the resistors R _e1 and R _e2 may reduce the gain of the MMIC 10 in some cases. The condition B is also satisfied because the resistor R _e2 and the capacitor C _e are provided between the drain of the FET 15 and the emitter of the transistor 17. As described above, in the bias stabilizing circuit 18 according to the present embodiment, the resistor R _e2 and the capacitor C _e are provided, so that the voltage drop monitor terminal 121 in FIG. can do.

Next, the operation of the bias stabilizing circuit 18 according to this embodiment will be described. First, as shown in FIG. 1, the power supply voltage is V _dd , the current passing through the power supply terminal 13 is I _total , the voltage at the point B, which is the connection point between the resistors R _e1 and R _e2 , is V _d , The current flowing on the drain side of the FET 15 is I _dd , the emitter current of the transistor 17 is I _e ,
The base current is I _b , the collector current is I _c , the base-emitter diffusion potential is V _be , and the DC gate bias voltage of the FET 17 is V _gg . As a general condition of using the MMIC 10, the DC gate bias voltage V _gg of the FET 15 is
(> 0) is smaller than the gate forward turn-on voltage of the FET 15, and the gate current is sufficiently small. Therefore, the collector voltage of the transistor 17 also becomes V _gg .

Under the above conditions, the bias stabilizing circuit 18
Then, the following three relational expressions (a6) to (a8) hold. In the following equation, the resistances R ₁ , R ₂ , R _e1 ,
The resistance values of R _e2 and R _c are respectively R ₁ , R ₂ , R _e1 , and
It is _designated as R _e2 and R _c .

[0045]

[Equation 8] _{V dd -V d = (I dd} + I e) · R e1 ... (a6) V dd -V d = (I total -I e -I dd) · R 2 -V be -I e R e2 _{... (a7) V dd = (} I total -I e -I dd) · R 2 + (I total -I e -I dd + I b) · R 1 ... (a8)

The equation (a6) expresses the voltage drop across the resistor R _e1 as V _dd
Expression represented by −V _d , Expression (a7) is an expression represented by V _dd −V _d by a voltage drop across the resistor R ₂ and a voltage drop across V _be and the resistor R _e2 ,
The expression (a8) is an expression showing that the sum of the voltage drops of the resistors R ₁ and R ₂ is equal to the power supply voltage V _dd .

Below, V _d and I are calculated from the equations (a6) to (a8).
Delete _total . First, the following (a
Equation 9) holds.

[0048]

(I _total −I _e −I _dd ) (R ₁ + R ₂ ) = V _dd −I _b R ₁ ∴I _total −I _e −I _dd = (V _dd −I _b R ₁ ) / (R ₁ + R ₂ ) ... (a9)

From the expressions (a6), (a7) and (a9), the following expression is established.

[0050]

(V _dd −I _b R ₁ ) R ₂ / (R ₁ + R ₂ ) −V _be −I _e R _e2 = I _dd R _e1 + I _e R _e1 = I _dd R _e1 + (I _b + I _c ) R _e1 (∵I _e = I _b + I _c ).

Where I _b = I _c / h _fe (where h _fe
Is the DC current amplification factor), so the above equation is as follows.

[0052]

[Equation 11] R ₂ V _dd / (R ₁ + R ₂ ) − {R ₁ R ₂ / (R ₁ + R ₂ )} · (1 / h _fe ) · I _c −V _be − (I _c / h _fe ).・ R _e2 −I _c R _e2 = I _dd R _e1 + (R _e1 / h _fe ) · I _c + I _c R _e1 ∴I _c = [R ₂ V _dd / (R ₁ + R ₂ ) −V _be −R _e1 I _dd ] / [R _e1 + R _e2 + (1 / h _fe ) {R _e1 + R _e2 + R ₁ R ₂ / (R ₁ + R ₂ )}] (a10)

From the collector of the transistor 17 to the resistor 19
Since the side has high impedance, V _gg = R _c I _c , and by substituting the expression (a10) into this, the following expressions (5) to
Expression (7) is obtained. A gate voltage-drain current characteristic represented by the equations (5) to (7) is shown by a characteristic line 41 in FIG.

[0054]

I _dd = −pV _gg + q (5) p = [R _e1 + R _e2 + (1 / h _fe ) {R _e1 + R _e2 + R ₁ R ₂ / (R ₁ + R ₂ )}] / R _c R _e1 (6) q = [R ₂ V _dd / (R ₁ + R ₂ ) −V _be ] / R _e1 (7)

On the other hand, the drain current I _dd of the FET 15 is
It is approximated by the characteristic equation (4). In this case, V _th is a threshold value of the FET 15, and k is a constant determined by the gate length, electron mobility and gate capacitance of the FET 15.
Further, the characteristic represented by the equation (4) is shown in FIG.
Indicated by 2.

The drain current I _dd actually obtained is shown in FIG.
Is the current I _{1 at} the intersection of the characteristic lines 41 and 42. Therefore, in order to suppress the fluctuation of I _dd due to the variation of the threshold value V _th of the FET 15, it is necessary that the slope −p in the expression (5) is as small as possible. For example, resistors R ₁ , R ₂ , so that p is on the order of 10 ⁻⁴ ,
If the resistance values of R _e1 , R _e2 , and R _c and the DC current amplification factor h _fe of the transistor 17 are selected, even if the variation of V _th is 1 V, the fluctuation of I _dd is as small as several hundred microamperes. It can be suppressed to a value.

Here, a specific example in the present embodiment will be described. In this example, R ₁ = 5.3 kΩ, R ₂ =
14.7 kΩ, R _e1 = 500 Ω, R _e2 = 1 kΩ, R _c =
10 kΩ, h _fe = 10, V _dd = 3V, I _dd is about 2 m
Consider the A low noise amplifier. Here, it is assumed that V _th may fluctuate ± 0.2 V with respect to the central value 0.3 V. These assumptions are common in MMICs for mobile communications. Further, the current consumed by the bias stabilizing circuit 18 is on the order of several tens of microamperes, and I
Small enough compared to _dd . Under the above conditions, p was calculated to be about 4.08 × 10 ⁻⁴ from the equation (6), and V _th ± 0.
It can be seen that the variation of I _dd is about 82 microamps for a variation of 2V. Therefore, the MMIC shown in FIG.
10 shows that the output matching circuit 30 can be externally attached without increasing the number of IC terminals while maintaining the same excellent current stability as the MMIC 100 shown in FIG.

As described above, according to the bias stabilizing circuit 18 of the present embodiment, the number of terminals of the MMIC 10 is the input terminal 11, the output terminal 12, the power supply terminal 13 and the ground terminal 1.
The output matching circuit 30 includes the bias stabilizing circuit 18 and the output matching circuit 30 without the output matching circuit 30 (FIG. 3). It is possible to realize the MMIC 10 that can be externally attached. As a result, a 4-pin package can be used as in the case where the output matching circuit is built in (FIG. 3), which reduces the IC package cost and the mounting area on the IC substrate as compared with the configuration shown in FIG. Is possible.

The present invention is not limited to the above embodiment, and for example, the transistor for which the bias is to be stabilized is not limited to the FET and may be a bipolar transistor.
Further, the form of the bias stabilizing circuit is not limited to that shown in FIG. 1, and a resistor is provided between the transistor to be bias-stabilized and the power supply, and the voltage drop at this resistor is changed to the active element. Any type that uses negative feedback to the bias to stabilize the bias may be used. Further, the circuit including the transistor to which the present invention is applied and which is the target of bias stabilization is not limited to the one-stage amplifier including the FET 15 shown in FIG. Furthermore, the present invention can be applied not only to the MMIC but also to circuits for other purposes.

[0060]

As described above, according to the transistor bias stabilizing circuit of the present invention, the first resistor for detecting the voltage drop due to the passing bias current and the signal of the transistor to be bias-stabilized. Since the second electrode is directly connected to the electrode on the output side and the second resistor is provided between the end on the electrode side on the signal output side of the transistor to be bias-stabilized in the first resistor and the active element side, It is said that it is possible to realize an IC in which the output matching circuit can be externally attached without increasing the number of terminals as compared with the case where the output matching circuit is built-in without incorporating the bias matching circuit and the output matching circuit. Produce an effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an MMIC including a transistor bias stabilizing circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing gate voltage-drain current characteristics of the FET in FIG.

FIG. 3 is a circuit diagram showing a configuration of an MMIC including a conventional bias stabilizing circuit.

FIG. 4 is a characteristic diagram showing gate voltage-drain current characteristics of the FET in FIG.

5 is a circuit diagram showing a configuration example of an MMIC that includes a bias stabilizing circuit equivalent to the MMIC illustrated in FIG. 3 and does not include an output matching circuit.

[Explanation of symbols]

10 ... MMIC, 15 ... FET, 17 ... Bipolar transistor, 18 ... Bias stabilizing circuit, 30 ... Output matching circuit, R _e1 , R _e2 ... Resistor, C _e ... Capacitor

Claims (2)

[Claims] 1. A first resistor, one end of which is connected to a power supply and the other end of which is connected to an electrode on a signal output side of a transistor whose bias is to be stabilized, for detecting a voltage drop due to a passing bias current. An active element for negatively feeding back a voltage drop in the first resistor to a bias for a transistor to be bias-stabilized; and a signal output side of the transistor to be bias-stabilized in the first resistor. A bias stabilization circuit for a transistor, comprising a second resistor provided between an end portion on the electrode side and the active element side. 2. The bias stabilizing circuit for a transistor according to claim 1, further comprising a capacitor having one end connected to an end of the second resistor on the active element side and the other end grounded. .