JPH09247140A - Interconnection device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To realize a method for identifying parallel transfer data in an optimum phase by a reference clock of a receiving unit and ensuring bit synchronization for each channel. Kind Code: A1 # 1 to #n of transfer data 103 from a transmitter 1 that outputs a phase synchronization with a transmitter reference clock 102 to channels # 1 to #n of a transmitter data 101.
For each data having a skew equal to or less than 1/2 of the synchronization (T) of the receiver reference clock 104 in each n channel, the receiver 2 uses the common phase setting means 21 to receive the phase control signal 106 from the nth bit synchronizer 22. And the mode switching signal 107, common phase control is performed in the common phase setting mode, and the skew with respect to the receiver reference clock 104 is set to ± T / 2 or less. For the channels # 1 to #n of the common phase setting data 108 from the common phase setting means 21, the 1st to nth
Of the reference clock 10 of the receiving unit by the bit synchronizing units 22a and 22 of
4 and the mode switching signal 10 from the nth bit synchronization unit 22
7, the individual phase control is performed in the individual phase setting mode, bit synchronization is ensured for each channel, and each of the channels # 1 to #n of the reception unit data 105 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interconnection device which performs optimum phase identification on a digital parallel transfer data in / between devices by a reference clock of a receiver and secures bit synchronization for each channel.

[0002]

2. Description of the Related Art For example, as shown in FIG. 20, a conventional interconnection device disclosed in Japanese Patent Application Laid-Open No. 6-224962 has a transmitting section 1 for transmitting section reference clocks for # 1 to #n channels of transmitting section data 101. At 102, the bit and word phases are aligned and output as # 1 to #n channels of the transfer data 103. The receiving unit 2i is the first or nth data identifying unit 22d for the transfer data 103 of each channel from the transmitting unit 1 and is the normal rotation or inversion receiving unit reference which is farther from the change point of the transfer data 103. Clock 104
Is selected and identified as the identification data 113a for each channel. The identification data 113a is re-identified by the re-identification unit 21b including a D flip-flop (DFF) group with the common reception unit reference clock 104, and the bit phases are aligned to provide channels # 1 to #n of the reception unit data 105b. Generate as.

The above-mentioned conventional interconnection device adopts a system in which parallel transfer data is identified by a normal or inverted receiver reference clock and then re-identified by the common clock.

The first to n-th data identification sections 22d are shown in FIG.
As shown in FIG.
D flip-flop (DFF) for #n channel,
Synchronous identification is performed at the timing of the rise of the identification clock from the exclusive OR (XOR) gate, and identification data 113a is generated for each channel. Next, the identification data 1
13a to DFF and RS flip-flop (RS-F
In F), the transfer data 103 is phase-compared with the data inverted by the inverter to generate a phase comparison signal. Further, the phase control pulse obtained by logically adding the phase comparison signal and the inverted data by an AND gate is subjected to a clock control signal which is inverted by the DFF in synchronism with the falling timing. Clock 104
Generates an identification clock that is a normal rotation or a reverse rotation of.

[0005]

In the conventional interconnection device as described above, since the parallel transfer data is identified by the forward rotation or the inverted reception unit reference clock and is commonly identified, the re-identification is performed by the clock concerned. There was the following problem because the data could not be identified with the optimum phase. (1) The phase margin at the time of data identification becomes small. (2) Bit shift may occur in a skew state between parallel transfer data. (3) The auxiliary signal indicating the accompanying phase information / state of the data cannot be transmitted in parallel because of the possibility of bit shift. (4) Data cannot be transferred if the frame formats of the transmitter / receiver data and the transfer data are different. (5) Since there is no fault monitoring function, a fault (error, fault, etc.) during data transfer cannot be detected. (6) When transferring additional information, it is necessary to increase the number of channels or the amount of information per channel, which reduces transfer efficiency. (7) Data cannot be identified based on the normal phase with respect to transfer data having long continuous homo-codes.

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to identify data in parallel transfer data individually in an optimum phase by a reference clock of a receiving unit so as to solve the above-mentioned problems in an interconnection device, and perform bit synchronization for each channel. The purpose is to provide a method (optimal phase synchronization interconnection method) for ensuring the above.

[0007]

The interconnection device of the present invention includes a receiving unit for each channel of transfer data which is output from the transmitting unit in phase synchronization with each channel of the transmitting unit data and a reference clock of the transmitting unit. In order to solve the above problems, the following means are provided and an optimum phase synchronization interconnection system is adopted.

The synchronization pattern inserting section is provided in the transmitting section.
Each channel m (integer of 2 or more) A frame synchronization pattern is inserted into a specific channel of parallel transmitter data or all channels. Alternatively, a frame synchronization pattern is inserted together with each channel other than the specific channel by using the cell phase information in the auxiliary signal for the specific channel of the asynchronous transfer mode cell transmission unit data of each channel m in parallel.

The parallel / serial converter is provided in the transmitter. For each channel m from the synchronization pattern insertion unit, for each channel in which the frame synchronization pattern of parallel transmission unit data is inserted,
The parallel / serial conversion of m to 1 is performed in the same phase to generate each channel of m serial transfer data of each channel having the same speed as the transmission unit reference clock.

The parity calculation / insertion unit is provided in the transmission unit. Instead of the synchronization pattern insertion unit, even / odd parity codes generated by inverting each other are simultaneously or periodically switched and inserted together with the frame synchronization pattern for each channel of the transmission data of each channel m in parallel.

The additional information insertion unit is separately provided between the synchronization pattern insertion unit of the transmission unit and the parallel / serial conversion unit. The external additional information is stored in the empty area of the auxiliary signal that is recognized without being added to the data.

The signal exchange section is provided in the transmission section. common/
For each channel m of parallel transfer data from the serial converter, the signal replacement timing is controlled according to the cell phase information in the auxiliary signal to cycle the auxiliary signal of the specific channel and the data of each channel other than the specific channel. Each channel m to be replaced is generated as each channel of serial transfer data.

The common phase setting means is provided in the receiving section. For each channel of transfer data having a phase difference between parallel data less than 1/2 of the reference clock cycle (T) from the transmitter to the common, the phase control signal and the mode switching signal from the bit synchronization unit of the specific channel are common. The common phase control is performed in the phase setting mode, and the common phase setting data having a parallel data phase difference of ± T / 2 or less with respect to the reference clock of the receiving unit is generated as each channel. Alternatively, the counter controls the common variable delay amount by the phase control signal from the bit synchronization unit in the common phase setting mode by the mode switching signal from the bit synchronization unit of the specific channel, and stops the operation in the individual phase setting mode. In addition, the common variable delay circuit inserts a common variable delay amount to be determined for each channel of transfer data having a phase difference between parallel data of T / 2 or less from the transmission unit according to the address of the counter, and a ± It is generated as each channel of common phase setting data having a parallel data phase difference of T / 2 or less. Alternatively, an individual variable delay circuit provided in place of the common variable delay circuit generates a delay clock by inserting the individual variable delay amount determined according to the address from the counter into the reference clock of the receiving unit, and inputs it to each channel of the bit synchronization unit in common. The amount of phase control between the delay clock and each channel of the transfer data directly input from the transmitting unit is set to be the same for each channel. Alternatively, each channel of the channel m parallel identification data shifted by 1 bit by the receiving unit reference clock from the frame synchronization unit is written by the memory at an address assigned according to the serial / parallel phase control signal from each channel of the frame synchronization unit. Then, the common phase is read by the address generated in accordance with the reference frequency-divided clock from the 1 / m frequency divider, and each channel is generated as each channel of the parallel m reception data. Alternatively, it operates in the same manner as the common phase setting means described at the beginning except that it operates in each phase setting mode in common when an error is detected and in an individual phase setting mode when no error is detected in accordance with an error detection signal from the error monitoring unit.

The bit synchronizing section is provided in the receiving section. For each channel of the common phase setting data from the common phase setting means, individual phase control is performed in the individual phase setting mode by the receiving unit reference clock and the mode switching signal from the particular channel, and bit synchronization is secured for each channel for reception. A phase control signal that is generated for each channel of the partial data and that changes so that the phase relationship with respect to the reference clock of the receiving unit is detected and data can be identified by the optimum phase is generated for each channel, and the deviation from the optimum phase is ± T. / K (k> 2)
Depending on the above, a mode switching signal for setting the phase setting mode to either common or individual is generated only for the specific channel. Alternatively, the counter stops the operation in the common phase setting mode by the mode switching signal from the particular channel, and controls the individual variable delay amount by the phase control signal from each channel in the individual phase setting mode. Further, the individual variable delay circuit inserts the determined individual variable delay amount into each channel of the common phase setting data from the common phase setting means in accordance with the address of the counter and generates it as each channel of the delay data. In addition, the flip-flop performs data identification by the optimum phase for each channel of the delay data from the individual variable delay circuit, and generates each channel of the reception unit data. Further, the control circuit detects the phase relationship between the delay data of each channel from the individual variable delay circuit and the reference clock of the receiving section, and generates the phase control signal for each channel and the mode switching signal only for the specific channel. Alternatively, in a separately provided sector, the phase control signal from the control circuit of the specific channel in the common phase setting mode by the mode switching signal from the control circuit of the specific channel is the phase control signal from the control circuit of each channel other than the specific channel. In place of the common phase control means. Alternatively, instead of the selector, the address from the counter of the specific channel is loaded to the counter of each channel other than the specific in the common phase setting mode by the mode switching signal from the control circuit of the specific channel. Alternatively, according to the error detection signal from the error monitoring unit, it operates in the same manner as the bit synchronization unit described at the beginning except that it operates in each phase setting mode common when an error is detected and when no error is detected.

The serial / parallel converter is provided in the receiver. Each channel from the transmitting unit having a phase difference between parallel data of T / 2 or less m Each channel from the bit synchronization unit via common phase setting means (both described above at the beginning) for each channel of parallel transfer data The receiving unit reference from the specific channel, which performs 1-to-m serial / parallel conversion with the same phase on each channel of the m-series identification data and selects according to the serial / parallel phase control signal from each channel of the frame synchronization unit It generates each channel of the m-parallel receiver data having the same signal speed as the clock or the frequency-divided clock from the 1 / m frequency divider, and outputs the reference frequency-divided clock from the specific channel. Or each channel m from the bit synchronization section
Each channel of serial identification data is shifted by 1 bit by the reference clock of the receiving unit, and is generated as each channel of parallel identification data.

The frame synchronizing section is provided in the receiving section. straight/
Each channel of the same speed as the reference frequency-divided clock or frequency-divided clock from the parallel conversion unit m Outputs as it is to the specific channel or each channel of the reception unit data or identification data in parallel, and the frame synchronization inserted by the synchronization pattern insertion unit A pattern is detected and a serial / parallel phase signal is generated. Alternatively, each channel of the same speed as the frequency-divided clock from the serial / parallel conversion unit is output as it is to each channel of the identification data in parallel, and the synchronization pattern in the auxiliary signal is detected for the specific channel, and after the frame, the specific Only for the pulse period generated according to the cell phase information in the auxiliary signal for each channel other than the above, the frame synchronization pattern inserted by the synchronization frame insertion unit is detected and the serial / parallel phase control signal is generated.

The error monitoring unit is provided in the receiving unit. The even / odd parity code inserted by the parity calculation / insertion unit is collated and monitored with respect to each channel of m parallel reception units data from each serial / parallel conversion unit to generate an error detection signal.

The 1 / m frequency divider is provided in the receiving section. The reception unit reference clock is divided by 1 / m to generate a divided clock.

The electric / optical conversion section and the optical / electrical conversion section are provided at the output section of the transmission section and the input section of the reception section for transmitting and receiving optical signals.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION An interconnection device according to an embodiment of the present invention corresponds to FIG. 1 and a transmission section 1 corresponds to FIG. The receiving unit 2 transfers the transfer data 10 from the transmitting unit 1 having a skew (phase difference between parallel data) of 1/2 or less of the period (T) of the receiving unit reference clock 104.
Common phase setting means 2 for each of the channels # 1 to #n
1 is the phase control signal 106 from the nth bit synchronization unit 22.
And the mode switching signal 107 to perform the common phase control in the common phase setting mode, and generate the common phase setting data 108 for setting the skew with respect to the receiver reference clock 104 to ± T / 2 or less. The common phase setting data 108
For each of the channels # 1 to #n, the individual phase setting mode is set by the first to nth bit synchronizing units 22a and 22 by the receiving unit reference clock 104 and the mode switching signal 107 from the nth bit synchronizing unit 22. Individual phase control is performed, bit synchronization is ensured for each channel, and # 1 to #n of the reception unit data 105 are controlled.
Phase control signals 106a and 1 that are generated as each channel and change so that the phase relationship with respect to the receiver reference clock 104 is detected and data can be identified by the optimum phase.
06 is generated for each of the channels # 1 to #n, and the mode switching signal 107 for setting the phase setting mode to either common or individual depending on whether the deviation from the optimum phase is ± T / k (k> 2) or more. Are generated only for the #n channel. At the end of the common phase setting mode, the phase relationship of the common phase setting data 108 with respect to the receiving unit reference clock 104 is always in word phase. Therefore, the first to nth bit synchronizing units 22a and 22a
Even if the individual phase control is performed in 2, data can be identified with the optimum phase that does not cause bit shift.

The interconnection device according to the above-described embodiment is a method for individually identifying data in parallel transfer data at the optimum phase by the reference clock of the receiving section and ensuring bit synchronization for each channel (optimum phase synchronization interconnection method). Take.

As shown in FIG. 2, the common phase setting means 21 of the receiving section 2 is a counter, and the phase from the bit synchronizing section 22 is first set in the common phase setting mode by the mode switching signal 107 from the nth bit synchronizing section 22. The common variable delay amount is controlled by the control signal 106, and the operation is stopped in the individual phase setting mode. Then, according to the address of the counter, a common variable delay circuit (consisting of n variable delay circuits and subjected to the same control) transfers from the transmitter 1 to each channel # 1 to #n of the transfer data 103 having a skew of T / 2 or less. On the other hand, the common variable delay amount to be determined is inserted, and the reception unit reference clock 104
Is generated as common phase setting data 108 having a skew of ± T / 2 or less. The nth bit synchronization unit 22
First, a counter (which may be the same as the counter of the common phase setting means 21) uses the mode switching signal 1 from the internal control circuit.
After resetting in the common phase setting mode according to 07, a predetermined variable delay amount is set in advance by the phase control signal 106 from the internal control circuit. Next, an individual variable delay circuit (which may be the same as each variable delay circuit forming the common variable delay circuit of the common phase setting means 21) according to the address of the counter.
The common phase setting data 10 from the common phase setting means 21
The individual variable delay amount to be determined is inserted into 8 #n channels to generate delay data 109. Further, the D flip-flop (DFF) discriminates the delay data 109 according to the optimum phase and generates it as the #n channel of the receiver data 105. Further, the control circuit detects the phase relationship between the delay data 109 and the receiver reference clock 104 and generates the phase control signal 106 that changes so that the data can be discriminated by the optimum phase. Delay is delayed data 1
09) is detected, the counter is switched to the individual phase setting mode, and the counter of the common phase setting means 21 controls the common variable delay amount by the continuously changing phase control signal 106. / K (k>
2) When there is a deviation above, the mode switching signal 107 for setting the common phase setting mode is generated again. The 1st to (n-1) th bit synchronization units 22a first stop the operation in the common phase setting mode by the mode switching signal 107 from the nth bit synchronization unit 22 by the counter, and perform the internal control in the individual phase setting mode. The individual variable delay amount is controlled by the phase control signal 106a from the circuit. Next, the individual variable delay amount to be determined is inserted into each of the channels # 1 to # n-1 of the common phase setting data 108 from the common phase setting means 21 by the individual variable delay circuit according to the address of the counter, and the delay data 109a is inserted. Generate as. Further, the DFF discriminates the delay data 109a based on the optimum phase, and generates each of the channels # 1 to # n-1 of the reception unit data 105. Further, the control circuit detects the phase relationship between the delay data 109a and the reference clock 104 of the receiving unit and changes the phase control signal 10 so that the data can be identified by the optimum phase.
6a is generated. Also, the reference clock 1 of the receiver shown in FIG.
Common phase setting data 108 and delay data 1 for 04
Like the phase relationship between 09a and 109, #n and # 1 to # 1 of the transfer data 103 in the common and individual phase setting modes.
The common and individual phase control is performed so that the common and individual phase setting data 108 can be identified with the optimum phase for the # n-1 channel, and all the delay data 109a and 109 are set to the optimum phase.

In the embodiment of the invention shown in FIG. 2, it has been described that the common phase setting means 21 inserts the common variable delay amount into the transfer data 103 and sets the common phase.
As shown in FIG. 4, instead of the common variable delay circuit, an individual variable delay circuit (which may be the same as the individual variable delay circuit forming the first to nth synchronization bits 22a and 22) is provided, and the address from the counter is provided. The delay clock 104a is generated by inserting the individual variable delay amount determined according to the reference clock 104 into the reception unit reference clock 104 to generate the first to nth bit synchronization units 22a.
And 22 have the same phase control amount between the delay clock 104a commonly input to each channel and the transfer data 103 directly directly input from the transmission unit 1 (common phase setting is required). It may be configured as the common phase setting means 21a. Since only one circuit of variable delay circuit is required for setting the common phase, the circuit scale can be reduced.

In the embodiment of the invention shown in FIG. 2, the first to (n-1) th bit synchronizing units 22a are, as shown in FIG. 5, separately provided selectors (SEL) for the phase control signal 106a from the control circuit. Alternatively, in the common phase setting mode by the mode switching signal from the control circuit of the n-th bit synchronization unit 22, the first to first selection of the phase control signal 106 from the control circuit of the n-th bit synchronization unit 22 is performed. It may be configured as the (n-1) th bit synchronization unit 22b. In the common phase setting mode, the common phase control signal 106 is selected by the first to nth bit synchronization units 22a and 22 and all the variable delay amounts become the same, so that the common phase setting means is unnecessary for the common phase setting. The circuit scale can be reduced.

Further, in the embodiment of the invention shown in FIG. 5, the first to (n-1) th bit synchronization units 22b correspond to the counter instead of the selector as shown in FIG. In the common phase setting mode according to the mode switching signal from the control circuit, the address 110 from the counter of the n-th bit synchronization unit 22 is loaded from the first to the (n-1) th.
It may be configured as the bit synchronization unit 22c. In the common phase setting mode, the first to n-th bit synchronization units 22a and 22
Since all counter addresses are the same, no additional circuit (selector or the like) is separately required for common phase setting, and the circuit scale can be reduced.

In the embodiment of the invention shown in FIG. 1, the transmitting unit 1 and the receiving unit 2 have been described in the case where the data 101 and 105 and the reference clocks 102 and 104 have the same signal speed. 1 to m (integer of 2 or more)
If the signal speed is
The S conversion unit 12 may be provided as the transmission unit 1a, the first to nth S / P conversion units 23a and 23, and the frame synchronization unit 24 may be separately provided as the reception unit 2d. The transmission data can be reduced by the multiplexed transfer data, and the data transfer efficiency can be improved. The synchronization pattern insertion unit 11 inserts the frame synchronization pattern into the #n channel of the transmission unit data 101a in each channel m in parallel. The P / S conversion unit 12 has m / one parallel / serial (P / S) in-phase with respect to each channel of the m parallel transmission unit data 101a in which the frame synchronization pattern is inserted from the synchronization pattern insertion unit 11. ) Conversion is performed to generate # 1 to #n channels of serially transferred data 103 of each channel m having the same signal speed as the transmission unit reference clock 102. The first to nth S / P converters 23a and 2
3 indicates # 1 to # 1 of the transfer data 103 from the transmission unit 1a.
#N The first to nth bit synchronization units 22a and 2 via the common phase setting means 21 shown in FIG.
S / P phase control signals from the respective channels of the frame synchronization unit 24 by subjecting each channel of the serial identification data 113 from 2 to 1 to m in-phase serial / parallel (S / P) conversion. The channels # 1 to #n of the reception unit data 105a in parallel with each channel m are generated at the same signal speed as the reception unit reference clock 104 selected in accordance with 111. Further, the nth S / P converter 23 outputs the reference divided clock 112. The frame synchronization unit 24 uses the n-th S / P conversion unit 2
3 to #n of the receiver data 105a for each channel m in parallel
The frame synchronization pattern output to the channel as it is and the frame synchronization pattern inserted by the synchronization pattern insertion unit 11 are detected and S
/ P phase control signal 111 is generated. It should be noted that in the embodiment of the invention described above, the synchronization pattern insertion unit 11 and the frame synchronization unit 2
4 is data 101 for transmitter and receiver for each channel m in parallel.
Although the description has been given of the case where it is provided only for the #n channels of a and 105a, it goes without saying that it may be provided individually for other or all channels.

In the embodiment of the invention shown in FIG. 7, the transmitter 1a and the receiver 2d are common to the transmitter 1b provided with a parity calculator / inserter 13 instead of the sync pattern inserter 11, as shown in FIG. 21 instead of the phase setting means 21
2 instead of b and the first to n-th bit synchronization units 22a and 22.
Receiver 2 provided with 2c and 22b and an error monitor 25 separately
It may be configured as e. It is possible to secure the number of bits of the frame synchronization pattern even with transfer data having a small free space for inserting the frame synchronization pattern. Further, even if the nth bit synchronization unit 22b malfunctions, the common / individual phase setting mode can be normally switched. As shown in FIG. 9, the parity calculation / insertion unit includes # 1 to # 1 of the transmission unit data 101a for each channel m in parallel.
#N Even / with frame sync pattern for each channel
Insert an odd parity code. As shown in FIG. 9A, the parity calculation circuit simultaneously calculates even / odd parity codes,
Transmitter data 1 for each channel m in parallel by the parity insertion circuit
The even / odd parity code is simultaneously inserted into each of the channels # 1 to #n of 01a. At that time, the frame synchronization unit 24 detects the even / odd parity codes which are mutually inverted and establishes frame synchronization. Further, as shown in FIG. 9B, the parity calculation circuit simultaneously calculates even / odd parity, the selector selects one of the even / odd parity codes according to a separately generated parity selection signal, and the parity insertion circuit One of the even / odd parity codes is inserted into each of the channels # 1 to #n of the transmission data 101a in the channel m parallel. At that time, the frame synchronization unit 24 detects a pattern that is inverted at the switching timing of the parity selection signal that is periodically switched and establishes frame synchronization. The common phase setting unit 21b and the first to nth bit synchronization units 22c and 22b detect an error according to the error detection signal 114 from the error monitoring unit 25 instead of the mode switching signal 107 from the nth bit synchronization unit 22. In this case, the operation is the common phase setting mode, the operation is the individual phase setting mode when no error is detected, and the same operation as in FIG. 7 is performed.
The error monitoring unit 25 checks the parity calculation / insertion unit 13 for each of the channels # 1 to #n of the reception unit data 105a in parallel with each channel m from the first to n-th S / P conversion units 23a and 23.
The even / odd parity code inserted in the above step is checked to check whether there is an error in the monitoring section (between the parity calculation / insertion section 13 and the error monitoring section 25), and the error detection signal 11
4 is generated. Using even / odd parity codes, it is possible to detect a failure that results in a fixed data level, prevent the same code from continuing in the transfer data 103, and synchronize the first to n-th bit synchronization units 22c and 22b. Does not deteriorate the characteristics.

Further, in the embodiment of the invention shown in FIG. 7, the transmitting section 1a and the receiving section 2d are not limited to the specific channels of the synchronization pattern inserting section 11 as shown in FIG.
#N Transmitting section 1c provided with a synchronization pattern inserting section 11a for inserting a frame synchronization pattern into all channels
And common phase setting means 21 for the transfer data 103
Instead of the common phase setting means 21c for setting the common phase for the low-speed identification data 113 after the S / P conversion / frame synchronization of 1 to m, and the first to the common phase setting data 108
Transfer data 1 in place of the nth bit synchronization units 22a and 22
No. 03, the low speed identification data 113 via the 1st to nth bit synchronization sections 22d and the 1st to nth S / P conversion sections 23a and 23 which perform data identification independently for each channel in the optimum phase.
On the other hand, not only the #n channel but also the # 1 to #n channels are independently output as they are and the sync pattern is detected to generate the S / P phase control signal 111.
Frame synchronization unit 24 and separate reception unit reference clock 104
The receiving unit 2f may be configured to include a 1 / m frequency divider 26 that divides the frequency by 1 / m. Since the low-speed identification data 113 after S / P conversion of 1 to m has a signal speed of 1 / m of the transfer data 103 and a phase margin of m times, bit shift can be prevented for the transfer data 103 having a large skew. As shown in FIG. 11, the receiving unit 2f is the first to the n-th bit synchronization unit 22d for each of the channels # 1 to #n of the transfer data 103 serially transmitted from the transmission unit 1c for each channel m. Data identification is performed based on the optimum phase with respect to the receiving unit reference clock 104, and each channel of serial identification data 113 for each channel is generated. Next, the identification data 1
First to nth S / P converters 23 for each of the 13 channels
a and 23, S from the first to nth frame synchronization units 24
1 / m that divides the receiver reference clock 104 by 1 / m by a selector (SEL) according to the / P phase control signal 111
The clock 115 from the frequency divider 26 is selected, and S of 1 to m is selected.
/ P conversion is performed and low speed channel m parallel identification data 1
Expand to each of the 13 channels. Further, for each channel of the low speed identification data 113, the first to nth frame synchronization units 24 output the same independently for each channel, detect the frame synchronization pattern, and generate the S / P phase control signal 111. . Furthermore, from the nth S / P converter 23 which inverts the divided clock 115 by the DFF of the common phase setting means 21c for each channel of the low speed identification data 113 from the 1st to nth frame synchronization section 24. Data is identified according to the reference frequency-divided clock 112, and each channel m is generated as each channel of the reception unit data 105a in parallel. Here, even if the common phase is not set in the previous stage of bit synchronization, if the bit deviation is m / 4 bits or less with respect to the receiver reference clock 104, the bit deviation can be practically prevented.

In the embodiment of the invention shown in FIG. 11, the receiving section 2f is replaced with the first to n-th S / P converting sections 23a and 23 as shown in FIG. Synchronization part 2
1 to 1 generated from each channel m of serial identification data 113 from 2d as each channel of the parallel identification data 113 of each channel m shifted by 1 bit by the m-bit shift register by the receiving unit reference clock 104. Instead of the nth S / P conversion unit 23b and the common phase setting unit 21c, the first to nth frames of the shift identification data 113 via the first to nth frame synchronization unit 24
~ S / P phase control signal 1 from the 1st to nth frame synchronization section 24a by the nth elastic memory (ES)
Write at the write address assigned according to 11, and
The common phase is read by the read address from the read address generation circuit that is generated according to the reference frequency-divided clock 112 from the / m frequency divider 26a, and is used as the channels # 1 to #n of the reception unit data 105a in each channel m in parallel. The common phase setting means 21d to be generated and the low speed identification data 1 after S / P conversion
In place of the first to nth frame synchronization units 24 for 13, the synchronization pattern is detected independently for each channel in the shift identification data 113 after S / P conversion, and the S / P phase control signal 111 is generated. First to output as is
You may comprise as the receiving part 2g provided with the nth frame synchronizing part 24a. The bit shift can be corrected corresponding to the ES amount that can be stored in the identification data 11 after bit synchronization.

In addition, in the above-described embodiment of the invention, the transmission units 1, 1
a, 1b or 1c and the receiving unit 2, 2a, 2b, 2c, 2
d, 2e, 2f or 2g is an electric / optical (E / O) converter at the output part and an optical / electrical (O / E) at the input part.
An optical signal may be transmitted and received by providing a conversion unit separately. Compared to electrical signals, data transfer of optical signals can increase the speed and lengthen the distance.

Further, in the embodiment of the invention shown in FIG. 10, the transmitter 1c and the receiver 2f have an asynchronous transfer mode (ATM, Asynchronous Tra) as shown in FIG.
When the data transfer of the (nsfer Mode) system is applied, A in parallel with each channel m is used instead of the synchronization pattern insertion unit 11a.
In place of the transmission unit 1d and the first to nth frame synchronization units 24, the synchronization pattern insertion unit 11b for inserting the frame synchronization pattern using the cell phase information in the auxiliary signal is provided for each channel of the TM cell transmission unit data 101a. , First #
An nth frame synchronization unit 2 for performing frame synchronization of ATM cell data by using cell phase information in the auxiliary signal on the n channel
4 and the first to (n-1) th frame synchronization units 24b for frame synchronization in the channels # 1 to # n-1 may be provided as the reception unit 2h. By using the cell phase information in the auxiliary signal after the transfer, it is possible to shorten the required synchronization establishment time when the frame synchronization of the ATM cell data channel is taken. Also, frame synchronization for all channels can be achieved by inserting synchronization patterns in the switch headers for all channels. As shown in FIG. 14A, the synchronization pattern insertion unit 11b first generates a switch header portion for the #n channel of the ATM cell transmitter data of each channel m in parallel by the timing generation circuit according to the cell phase information in the auxiliary signal. The pattern generation circuit generates a synchronization pattern that is effective only during the period indicated by the timing pulse shown. Next, ATM cell data # 1 to #n
-1 An inserting circuit inserts the synchronization pattern into each channel and the #n channel of the auxiliary signal. The n-th frame synchronization unit 24 and the 1st to (n-1) th frame synchronization units 24b are shown in FIG.
4 (b), for each # 1 to #n channel of the low-speed channels m parallel ATM cell identification data 113 from the first to n-th S / P converters 23a and 23, #n is first set for each channel. When the synchronization pattern in the auxiliary signal is detected by the pattern detection circuit of the channel, the frame synchronization pattern is detected again at the detection timing after one frame indicated by the operating frame counter, and the S / P phase control signal 111 is generated. Next, the S / P phase control signal 111 is detected by the pattern detection circuit for the frame synchronization pattern only during the period indicated by the timing pulse generated by the timing generation circuit of the # 1 to # n-1 channels according to the cell phase information in the auxiliary signal. To generate. In the above embodiment, the synchronization pattern insertion unit 11b has been described as inserting the synchronization pattern into the switch header unit. However, according to the auxiliary signal, the insertion circuit is enabled only in the payload portion of the invalid cell and the synchronization pattern is inserted. In the (n-1) th frame synchronization unit 24b, the pattern detection circuit may be enabled only in the payload portion of the invalid cell according to the auxiliary signal from the nth frame synchronization unit 24. Synchronization patterns can be inserted into all channels of ATM cell data without switch headers.
Frame synchronization for all channels is possible. Figure 1 shows the ATM system
As shown in 5, valid cells that store useful data that cannot be processed and are composed of a header (5 bytes) that stores cell destination information and payload (48 bytes) and invalid cells for adjustment that are inserted periodically or randomly. If necessary, ATM cell data is formed by the switch header used in the ATM switch. The cell phase information indicates the start position when the switch header is present, and indicates the header start position when the switch header is not present. Therefore, in the transfer of ATM cell data, it is easy to post-transfer signal processing by transmitting the cell phase information indicating the cell head position and the cell valid / invalid information indicating the valid / invalid cell as an auxiliary signal. effective. For example, when it is necessary to insert the frame synchronization pattern into all channels, even if the synchronization pattern cannot be inserted into the ATM cell data of the valid cell portion, the frame synchronization pattern is inserted into the switch header portion that is not used by other than the ATM switch. It can be used as free space.

Further, in the embodiment of the invention shown in FIG. 15 described above, the transmitting unit 1d is described as transmitting the auxiliary signal in parallel with the data channel at the time of data transfer applying the ATM system.
As shown in FIG. 16, the additional information insertion unit 14 for storing the external additional information 116 in the empty area of the auxiliary signal recognized without being added to the data between the #n channels of the synchronization pattern insertion unit 11b and the P / S conversion unit 12 is provided. It may be provided separately. For example, when applying a transfer method that requires data error correction information in addition to the auxiliary signal shown in FIG.
As shown in (b), the additional information may be stored in the empty area of the auxiliary signal without being added to the data and may be transmitted in parallel with the data channel. Since the additional information can be transferred without increasing the number of transfer signals or the amount of transfer data per channel, the data transfer efficiency can be improved and the data rate conversion can be omitted to simplify the processing.

Further, in the embodiment of the invention shown in FIG. 13, the transmitter 1d transmits each channel m from the P / S converter 12 to the channels # 1 to #n of the serial transfer data 103 as shown in FIG. On the other hand, the transfer data 103 of each channel m serially controlling the signal switching timing according to the cell phase information in the auxiliary signal and periodically switching the data of each of the # 1 to # n-1 channels and the auxiliary signal of the #n channel. # 1 to #
It may be configured as the transmission unit 1f that is additionally provided with the signal exchange unit 15 that is generated for each channel. Transfer data 1
In 03, the same code is prevented from continuing, and the synchronization characteristic of the transfer data 103 by the cycle insertion auxiliary signal is not deteriorated during bit synchronization. As shown in FIG. 19, the signal exchange unit 15 receives from the P / S conversion unit 12 the data channels # 1 to # n−1 and the auxiliary signal channels #n for the first to nth.
-1 two-to-one selector selects one of the data of # 1 to # n-1 channel and the auxiliary signal of n channel according to the selection control signal from the selection control circuit, and then selects # 1 to # n-
It is output as the transfer data 103 of one channel. In addition, the n-th n-to-1 selector selects one of the data of the # 1 to # n-1 channels and the auxiliary signal of the n channel, and
It is output as the transfer data 103 of the channel. The selection control circuit generates a selection control signal that periodically changes according to the transmitting unit reference clock 102 so that the first to nth selectors sequentially select the auxiliary signal according to the phase information in the #n channel auxiliary signal. .

[0034]

According to the interconnection device of the present invention as described above, a method is adopted in which parallel transfer data is individually identified at the optimum phase based on the reference clock of the receiving section and bit synchronization is ensured for each channel. Each invention has the following effects as compared with the conventional method in which parallel transfer data is identified by the normal or inversion receiver reference clock and then re-identified by the common clock. (1) (2) Data can be identified with an optimum phase that does not cause a bit shift. (3) (4) (5) The circuit scale can be reduced. (6) The transmission medium can be reduced by the multiplexed transfer data, and the data transfer efficiency can be improved. (7) The number of bits of the frame synchronization pattern can be secured even for transfer data in which there is little free space for inserting the frame synchronization pattern. In addition, the common / individual phase setting mode can be normally switched even if the specific channel of the bit synchronization unit malfunctions. (8) Since the low-speed identification data after serial / parallel conversion of 1 to m has a signal speed of 1 / m of the transfer data and a phase margin of m times, bit shift can be prevented for transfer data having a large skew. (9) The bit shift can be corrected corresponding to the amount of memory that can be stored for the identification data after bit synchronization. (10) It is possible to increase the speed and lengthen the distance by transferring the data of the optical signal compared to the electric signal. (11) AT using the cell phase information in the auxiliary signal after transfer
It is possible to shorten the required synchronization establishment time when establishing frame synchronization of the M cell data channel. (12) Since the additional information can be transferred without increasing the number of transfer signals or the amount of transfer data per channel, the data transfer efficiency can be improved and the data rate conversion can be omitted to simplify the processing. (13) The same code is prevented from continuing in the transfer data, and the synchronization characteristic of the transfer data by the cycle insertion auxiliary signal is not deteriorated at the time of bit synchronization.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an interconnection device showing an embodiment of the present invention.

FIG. 2 is a functional block diagram of a common phase setting unit and first to n-th bit synchronization units which constitute the reception unit shown in FIG.

FIG. 3 is a timing diagram illustrating the operation of the receiving unit shown in FIG.

FIG. 4 is a functional block diagram of the other embodiment shown in FIG.

FIG. 5 is a functional block diagram of another embodiment shown in FIG.

FIG. 6 is a functional block diagram of the other embodiment shown in FIG.

FIG. 7 is a functional block diagram of another embodiment of the present invention.

FIG. 8 is a functional block diagram of another embodiment of the present invention.

FIG. 9 is a parity calculation that configures the transmission unit shown in FIG.
The functional block diagram of an insertion part, and the functional block diagram of the said other one Embodiment.

FIG. 10 is a functional block diagram of another embodiment of the present invention.

FIG. 11 is a diagram illustrating first to n-th constituent elements of the receiver shown in FIG.
3 is a functional block diagram of the S / P conversion unit and common phase setting means of FIG.

FIG. 12 is a functional block diagram of the other embodiment shown in FIG. 11.

FIG. 13 is a functional block diagram of another embodiment of the present invention.

FIG. 14 is a functional block diagram of a synchronization pattern insertion unit which constitutes the transmission unit shown in FIG. 13 and a first which constitutes the reception unit.
~ Functional block diagram of the n-th frame synchronization unit.

FIG. 15 is a diagram for explaining an ATM cell data format in the transmitter shown in FIG.

16 is a functional block diagram of another embodiment of the transmission unit shown in FIG.

FIG. 17 is a diagram for explaining a transfer data format in the transmitting unit shown in FIG.

FIG. 18 is a functional block diagram of another embodiment of the transmission unit shown in FIG.

FIG. 19 is a functional block diagram of the signal exchange unit shown in FIG. 18.

FIG. 20 is a functional block diagram of an interconnection device showing a conventional technique.

FIG. 21 is a functional block diagram of first to n-th data identification units shown in FIG. 20.

[Explanation of symbols]

1, 1a, 1b, 1c, 1d, 1e, 1f transmitter,
2, 2a, 2b, 2c, 2d, 2e receiving unit, 11, 1
1a synchronization pattern insertion unit, 12 P / S conversion unit, 13
Parity calculation / insertion unit, 14 Additional information insertion unit, 15
Signal replacement section, 21, 21a, 21b, 21c Common phase setting means, 22, 22b, 22d nth bit synchronization section, 22a, 22c, 22d 1st to n-1th bit synchronization section, 23, 23b nth S / P converter, 23
a, 23b 1st to n-1st S / P conversion units, 24 frame synchronization units and 1st to nth frame synchronization units, 24a
1st to nth frame synchronization unit, 24b 1st to nth-1
Frame synchronization unit, 25 error monitoring unit, 26, 26a
1 / m frequency divider, 101, 101a transmitter data, 10
2 transmitter reference clock, 103 transfer data, 10
4, 104a Delayed clock receiver reference clock, 10
5, 105a receiver data, 106, 106a phase control signal, 107 mode switching signal, 108 common phase setting data, 109, 109a delay data, 110 counter address, 111 S / P phase control signal, 112
Reference frequency division clock, 113 identification data, 114 error detection signal, 115 frequency division clock, 116 additional information. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (13)

[Claims] 1. A transmission unit for phase-synchronizing each channel of transmission unit data with a transmission unit reference clock and outputting as each channel of transfer data, and a reception unit reference for each channel of transfer data from the transmission unit. In an interconnection device including a receiver that performs a synchronization process with a clock and generates each channel of the receiver data, in the receiver, from the transmitter to the receiver reference clock cycle (T) of 1
For each channel of the transfer data having a phase difference between parallel data of less than or equal to / 2, common phase control is performed in the common phase setting mode by the phase control signal and the mode switching signal from the bit synchronization section of the specific channel, and the reception is performed. Common phase setting means for generating each channel of the common phase setting data having a parallel data phase difference of ± T / 2 or less with respect to the partial reference clock, and the common phase setting means for each channel of the common phase setting data, Individual phase control is performed in the individual phase setting mode by the receiving section reference clock and the mode switching signal from the specific channel, bit synchronization is ensured for each channel, and each channel of the receiving section data is generated, and the receiving section is also provided. The phase control signal that changes so as to detect the phase relationship with respect to the reference clock and enable data identification by the optimum phase is checked. For each channel, and generates the mode switching signal for the specific channel only to set the phase setting mode to either common or individual depending on whether the deviation from the optimum phase is ± T / k (k> 2) or more. An interconnection device comprising: the bit synchronization unit. 2. The common phase setting means controls the common variable delay amount by the phase control signal from the bit synchronization section in the common phase setting mode by the mode switching signal from the bit synchronization section of the specific channel, and in the individual phase setting mode. A counter that stops the operation, and the common variable delay amount to be determined is inserted into each channel of transfer data having a parallel data phase difference of T / 2 or less from the transmission unit according to the address of the counter, and the reception unit reference A common variable delay circuit for generating each channel of common phase setting data having a parallel data phase difference of ± T / 2 or less with respect to a clock is provided, and a common phase setting mode by a mode switching signal from the particular channel in a bit synchronization unit. And the counter that controls the individual variable delay amount by the phase control signal from each channel in the individual phase setting mode. An individual variable delay circuit that inserts the individual variable delay amount to be determined into each channel of the common phase setting data from the common phase setting means according to the address of the counter and generates each channel of the delay data, and the delay data of the delay data. For each channel, a flip-flop for performing data identification according to the optimum phase for each channel and generating it as each channel of the receiver data, and a phase relationship between the delay data of each channel from the individual variable delay circuit and the receiver reference clock are shown. 2. The interconnection device according to claim 1, further comprising a control circuit which detects the phase control signal for each channel and generates the mode switching signal only for the specific channel. 3. An individual variable delay circuit is provided in the common phase setting means instead of the common variable delay circuit, and an individual variable delay amount determined according to an address from the counter is inserted into a reception unit reference clock to generate a delay clock, The phase control amount between the delay clock commonly input to each channel of the bit synchronization unit and each channel of the transfer data directly input from the transmission unit is set to be the same for each channel. The interconnection device according to claim 2, wherein 4. The phase control signal from the control circuit of the specific channel is transferred from the control circuit of each channel other than the specific channel in the common phase setting mode by the mode switching signal from the control circuit of the specific channel in the bit synchronization unit. 3. The interconnection apparatus according to claim 2, wherein a selector for selecting instead of the phase control signal is separately provided, and the common phase setting means is unnecessary. 5. The bit synchronization unit loads the address from the counter of the specific channel to the counter of each channel other than the specific in the common phase setting mode by the mode switching signal from the control circuit of the specific channel, 5. The interconnection device according to claim 4, wherein the interconnection device has the same function as the above. 6. Each channel m (integer of 2 or more) in the transmitting unit
The synchronization pattern insertion unit that inserts the frame synchronization pattern into a specific channel of the transmission unit data in parallel, and m pairs of the same phase for each channel into which the frame synchronization pattern of the transmission unit data from the synchronization pattern insertion unit is inserted. A parallel / serial conversion unit for performing parallel / serial conversion of 1 to generate each channel of each channel m serial transfer data having the same signal speed as the transmission unit reference clock is provided, and the reception unit performs T / T conversion from the transmission unit.
2. Each channel m serial transfer data having a phase difference between parallel data of 2 or less is generated for each channel of serial transfer data of each channel m. On the other hand, m / m receiver data of each channel having the same signal speed as the reference clock of the receiver for selecting 1 / m serial / parallel conversion with the same phase and selecting according to the serial / parallel phase control signal from each channel of the frame synchronization part. And a serial / parallel converter that generates each reference channel and outputs a reference divided clock from the specific channel,
The serial / parallel phase is output as it is to the specific channel of the receiving unit data having the same signal speed as the reference divided clock from the serial / parallel conversion unit, and the frame synchronization pattern inserted by the synchronization pattern inserting unit is detected. The interconnection device according to claim 1, 2, 3, 4, or 5, further comprising a frame synchronization unit that generates a signal. 7. The transmitting section, instead of the synchronization pattern inserting section,
Each channel m For each channel of parallel transmitter data,
A parity calculation / insertion unit that inserts together with the frame synchronization pattern by switching even / odd parity codes generated by inverting each other at the same time or periodically is provided, and common in error detection according to the error detection signal from the error monitoring unit in the receiving unit, The common phase setting means and the bit synchronization section which operate in the same manner as in claim 1 except that they operate in individual phase setting modes when no error is detected, and the reception section data of each channel m parallel from the serial / parallel conversion section. 7. The interface according to claim 6, further comprising: an error monitoring unit for collating and monitoring the even / odd parity code inserted by the parity calculation / insertion unit and generating the error detection signal for each channel. Connection device. 8. A synchronization pattern insertion unit for inserting a frame synchronization pattern into all channels in the transmission unit, not only a specific channel of parallel transmission unit data, and a reception unit from the transmission unit to each channel m. For each channel of serial transfer data, a bit synchronization unit that independently detects the phase relationship with respect to the receiving unit reference clock for each channel, performs data identification by the optimum phase, and generates each channel of serial identification data for each channel m, 1 / m frequency division is performed according to the serial / parallel phase control signal from each channel of the frame synchronization unit by subjecting each channel of the identification data from the bit synchronization unit to 1 / m serial / parallel conversion in the same phase. Each channel m having the same signal speed as the frequency-divided clock from the signal generator, and each channel of the identification data in parallel are generated, and the reference frequency-divided Output to the serial / parallel conversion unit and the frame inserted by the synchronization pattern insertion unit while directly outputting to each channel of the identification data having the same signal speed as the divided clock from the serial / parallel conversion unit. A frame synchronization unit that detects a synchronization pattern and generates the serial / parallel phase control signal, and a reference frequency division from a specific channel of the serial / parallel conversion unit for each channel of the low-speed identification data from the frame synchronization unit. Common phase setting means for performing data identification according to the clock and generating each channel m as each channel of parallel receiving unit data, and 1 / m for dividing the receiving unit reference clock by 1 / m to generate the divided clock. 7. The interconnection device according to claim 6, further comprising a frequency divider. 9. A direct signal generated by the receiving unit for each channel m from the bit synchronization unit to each channel m serial identification data, which is shifted by 1 bit by the receiving unit reference clock, as m channels for parallel identification data. The parallel conversion unit and each channel of the shift identification data via the frame synchronization unit are written by the memory at an address assigned according to the serial / parallel phase control signal from each channel of the frame synchronization unit, and divided by 1 / m. 9. A common phase setting means for reading a common phase with an address generated in accordance with a reference frequency-divided clock from a signal generator and generating it as each channel of the reception data of each channel m in parallel is provided. Interconnection device. 10. The transmission section and the reception section are separately provided with an electric / optical conversion section at an output section and an optical / electric conversion section at an input section to transmit / receive an optical signal. The interconnection device according to 2, 3, 4, 5, 6, 7, 8 or 9. 11. A synchronization pattern insertion in which a frame synchronization pattern is inserted together with each channel other than the specified channel in the transmission section by using cell phase information in an auxiliary signal for a specific channel of asynchronous transfer mode cell transmission unit data of each channel m in parallel. A section is provided, and in the receiving section, each channel having the same speed as the frequency-divided clock from the serial / parallel conversion section is output as it is to each channel of the identification data in parallel and the synchronization pattern detection 1 in the auxiliary signal for the specific channel is performed. A frame for detecting a frame synchronization pattern inserted by the synchronization frame insertion unit and generating a serial / parallel phase control signal only for a pulse period generated according to cell phase information in the auxiliary signal for each channel other than the specific channel after the frame. 9. The interconnection device according to claim 8, further comprising a synchronization unit. 12. An additional information inserting section for storing external additional information is separately provided in a vacant area of an auxiliary signal which is recognized without being added to data between specific channels of a synchronization pattern inserting section and a parallel / serial converting section of a transmitting section. 11. The method according to claim 11, wherein
The interconnection device described. 13. The transmission unit controls the signal replacement timing for each channel of the m-serial transfer data from the parallel / serial conversion unit according to the cell phase information in the auxiliary signal, and the auxiliary signal of the specific channel and the auxiliary signal. 12. The interconnection device according to claim 11, further comprising a signal interchange section for separately generating data for each channel m serially transferred data for periodically exchanging data for each channel other than a specific channel.