JPH09247552A - Signal processing circuit of solid-state imaging device - Google Patents

Abstract

(57) Abstract: The OB level can be increased by the incidence of an excessive amount of light without making the CCD part have a special structure or adopting a structure for changing the substrate voltage of the CCD when an OB level abnormality occurs. A malfunction in the clamp circuit 101 when it fluctuates is avoided, and a display screen with a good image quality without a sense of discomfort is obtained. Based on an OB clamp pulse CP1,
A pulse generation circuit 105 for generating an auxiliary clamp pulse CP2 synchronized with a horizontal blanking period other than the OB period of the CDS output is provided, and when the OB level fluctuates due to the incidence of an excessively large amount of light, the clamp circuit 101 uses the auxiliary OB of CDS output by clamp pulse CP2
The signal level in the horizontal blanking period other than the period is clamped, and the video signal is generated based on the output of the clamp circuit 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a solid-state image pickup device, and more particularly to a surveillance camera, a doorphone camera, a videophone camera using a CCD type solid-state image pickup device,
The present invention relates to a clamp circuit for CCD output in a video camera such as a video movie.

[0002]

2. Description of the Related Art Conventionally, in CCD type solid-state image pickup devices,
By shielding a part of the CCD (a few pixels) from light,
The CD section is provided with an optical black section (hereinafter referred to as OB section) in which incident light is not photoelectrically converted.
The signal level (OB level) in the signal period (OB period) corresponding to the OB portion of the D output is an optical black level.

In a video camera using a CCD, this OB level is used as a reference for the black level of a video signal, and in a signal processing IC at the rear stage of the CCD section, a clamp (DC reproduction) for adjusting the OB level to the reference level. Processing is performed, and signal processing based on various television standards is performed based on the signal after the clamp processing.

FIG. 5 is a block diagram schematically showing the entire structure of a general monochrome video camera using a CCD.
In the figure, reference numeral 200 denotes a black and white video camera which picks up an image of a subject and outputs a video signal.
Is a CCD unit (CCD solid-state image sensor) for photoelectrically converting light coming from a subject obtained through the optical lens 201a.
It has 201 and a signal processing circuit 210 for processing the photoelectrically converted CCD output.

In the signal processing circuit 210, the CCD output is sampled and held by the CDS circuit 202.
Here, the CCD 201 is the C from the drive IC 208.
Driven by the CD drive pulse, photoelectric conversion signals corresponding to each pixel are sequentially supplied to the CDS circuit 202.

In the signal processing circuit 210, the CDS output is clamped by the clamp circuit 203 to fix the signal level corresponding to the OB period of the CCD output in a direct current manner. And this clamp circuit 2
The output of 03 is AGC (Automatic Gain Control) for automatic gain control.
The gain control circuit 204 controls the gain, and then the processing circuit 205 performs gamma correction processing and white clip processing that limits the peak of the white level. Further, the processing circuit 206 performs pedestal (black signal level in the video signal). ) Setting processing and synchronous MIX processing are performed. The CCD output subjected to such processing is output from the signal processing circuit 210 via the drive circuit 207 as a video output suitable for a display device such as a television monitor.

In the circuit 210 for performing the signal processing of the CCD output as described above, the gamma correction processing is performed by performing the clamp processing of fixing the signal level corresponding to the black level of the video signal of the CCD output to DC. It is common to start from.

[0008]

However, in the conventional video camera having the above-described structure, when an excessive amount of light enters the CCD type solid-state image pickup device, excess charges generated in the CCD section generate a signal due to the light. In some cases, it may overflow into the OB portion (light-shielded pixel portion). For example, in a surveillance camera installed outdoors or a doorphone camera directed to the outside, an excessive amount of light from the sun such as Seiyo may be incident, and in this case, an overflow photoelectric charge is generated in the OB portion due to the excessive amount of light. there's a possibility that.

By the way, in recent years, in surveillance cameras, door-phone cameras, etc., in order to reduce the size, cost, and weight of the lens, a fixed-brightness lens without an iris is used to electronically control the amount of light. The iris method is widely adopted. This is C depending on the amount of light incident on the CCD.
The accumulation time of the photoelectrically converted charges in the CD section is controlled by the shutter speed of the CCD so that the signal level of the CCD output becomes an appropriate level according to the light quantity.

That is, this electronic iris system is a CCD
Even when the portion is irradiated with an excessively large amount of light, an appropriate CCD output can be obtained by controlling the driving of the CCD. Therefore, in this method, when the extremely strong incident light is incident on the camera, the CCD unit is always irradiated with an excessive amount of light, and the mechanical iris (aperture) is used.
The mechanism controls the amount of light incident on the CCD to ensure proper CC
Compared with the method of obtaining the D output, overflow of photocharges to the OB portion is more likely to occur. For this reason, an excessive amount of light causes the CCD to
The photocharges overflowing into the OB portion of the area cause an erroneous operation in the OB clamp circuit in the subsequent stage that creates a black level reference on the screen, and the display state of the screen becomes unstable.

FIG. 6 shows the waveforms of the CCD output Sc, the video output Sv of the camera, and the state of the screen during normal operation (see FIG.
(A)) and an abnormal operation in which the photocharge overflows to the OB portion due to the incidence of an excessive amount of light (FIG. 6B).
It is shown in contrast with.

In the example of abnormal operation shown in FIG. 6B, C
Since the signal level of the CD output Sc in the OB period during which the overflow of photocharges has occurred is almost at the same level as the maximum level in the video signal period of the CCD output Sc, the display screen should be brighter in general. The screen becomes dark with brightness close to the black reference level.

By the way, the solid-state imaging device described in Japanese Patent Laid-Open No. 3-243075 (Prior Art 1) and Japanese Patent Laid-Open No.
In the solid-state imaging device described in Japanese Patent No. 274366 (Prior Art 2), by adopting a configuration in which charges are not read out from the OB portion of the CCD, the signal processing in which the OB level fluctuated due to the incidence of excessive light amount is in the subsequent stage. A method is disclosed for preventing the circuit from being fed.

Specifically, the above-mentioned Japanese Patent Laid-Open No. 3-243075.
In the solid-state imaging device of the publication, the OB portion has a structure that does not have either the charge reading gate or the photoelectric conversion element. In this case, as the signal level corresponding to the black level of the video signal, it is necessary to use not the OB level of the CCD output but the level of the pseudo-generated signal other than the CCD output.

In the solid-state image pickup device described in Japanese Patent Laid-Open No. 4-274366, a dummy pixel portion having a structure in which photoelectric charges are not read is provided between the photoelectric conversion pixel portion and the light shielding pixel portion, and the dummy pixel portion is provided. By bringing the surface of the light receiving element of the pixel portion into contact with the metal light-shielding film thereon, multiple reflections occur between the surface of the light-receiving element and the light-shielding film, and the O
The light is suppressed from entering the portion B. Further, by providing the dummy pixel section in this way, it is possible to suppress the photocharge overflowing from the photoelectric conversion section from flowing into the OB section.

However, in the method of the above-mentioned prior art document 1, since the reference level of the signal is not set to the OB section output (OB level) in the CCD output, the video signal section in the video signal section depends on the presence or absence of the charge transfer operation. A level difference is likely to occur between the black level and the pseudo black reference level used instead of the OB level. For this reason, when the normal light level is used instead of the strong light, this level difference causes the fluctuation of the pedestal level in the video output of the camera as a result of the gain adjustment by the AGC (Automatic Gain Control) processing which is the signal processing in the subsequent stage. Will cause.

That is, the AGC circuit increases the gain for CCD output in a range from a minute level to a normal level, while the AGC circuit has a high level C for strong light.
Since it is configured to reduce the gain for the CD output, instead of the OB level of the CCD output,
When a pseudo signal level other than the CCD output is used as the black reference level, the pseudo signal level may be amplified while being deviated from the black level in the photoelectric conversion pixel section.

As a result, the pedestal in the video signal rises in a dark scene, while the pedestal falls in a bright scene, resulting in deterioration of the contrast on the display screen.

Further, according to the method of the prior art document 1, O
Part B needs to have a special structure, and in particular, in the method of the prior art document 2, it is necessary to provide a dummy pixel part. In these methods, a solid-state imaging device having a normal CCD part is used. I can't.

Further, in Japanese Patent Application Laid-Open No. 5-176236 (Prior Art Document 3), an abnormality due to a smear component of an OB level is detected in a CCD image pickup circuit, and when there is an abnormality, the substrate voltage of the CCD is raised, A device for avoiding an abnormal state is disclosed. However, in this method, the substrate voltage is raised when an abnormality occurs, so that the saturation voltage of the CCD is entirely lowered, and the difference in the saturation level of the CCD between pixels is likely to appear on the screen. That is, in a pixel in which the saturation level of the CCD is originally small, the amount of accumulated photocharge is extremely small, and it may appear as a black dot on the screen.

In addition, in the one described in this Document 3, the abnormality detection by the smear component of the OB level is detected by the OB of the CCD output.
Since the signal level of the section is compared with the output level of the horizontal blanking section of the CCD output, the sample and hold circuits and the peak and hold circuits respectively perform the O conversion.
A unit corresponding to the B section and the horizontal blanking section is required, and the circuit configuration for abnormality detection becomes complicated.

The present invention has been made in order to solve the above problems, and provides a solid-state image pickup device capable of detecting a change in the OB level due to the incidence of an excessively large amount of light with a simple circuit configuration. The purpose is to obtain a signal processing circuit.

Further, according to the present invention, the OB level can be increased by the incidence of an excessive amount of light without the CCD part having a special structure or the structure in which the substrate voltage of the CCD is changed when the OB level is abnormal. An object of the present invention is to obtain a signal processing circuit of a solid-state image pickup device which can avoid a malfunction in the OB clamp circuit when it fluctuates and can obtain a display screen with a good image quality without a feeling of strangeness.

[0024]

A signal processing circuit of a solid-state image pickup device according to the present invention (claim 1) includes an image reproduction signal based on a CCD output from a CCD type solid-state image pickup device having a light-shielding pixel portion and a predetermined signal. It is provided with a function of receiving a timing signal and performing a clamping process for adjusting the signal level of the image reproduction signal for a predetermined period to a reference level.

Then, the signal processing circuit of this solid-state image pickup device performs a clamping process for adjusting the signal level of the image reproduction signal in the OB period corresponding to the light-shielded pixel portion to a reference level.
A clamp circuit for abnormality detection performed using an OB clamp pulse synchronized with the OB period, detection means for detecting the minimum level of the output of the clamp circuit for abnormality detection which is equal to or lower than the reference level, and the minimum level of the detection output. And a comparison means for comparing the comparison reference level corresponding to the reference level. Thereby, the above object is achieved.

According to a second aspect of the present invention, in the signal processing circuit of the solid-state image pickup device according to the first aspect, the OB of the image reproduction signal is generated based on the OB clamp pulse.
The timing signal based on the output signal from the pulse generating means for generating an auxiliary clamp pulse synchronized with the horizontal blanking period other than the period and the comparing means.
A signal switching means for switching between a clamp pulse and the auxiliary clamp pulse, and when the minimum level of the detection output is smaller than the comparison reference level, the signal level of the image reproduction signal during the horizontal blanking period. Is configured to be clamped so as to match the reference level.

According to a third aspect of the present invention, in the signal processing circuit of the solid-state image pickup device according to the first aspect, as the clamp processing function, an O signal for the image reproduction signal is output.
A signal processing clamp circuit for performing a clamping process for adjusting the signal level of the period B to the reference level, receiving a detection output from the detection means, and having an amplitude corresponding to the minimum level of the detection output, and a pulse A pulse signal generation circuit that generates a correction pulse signal whose section is synchronized with the OB clamp pulse, and the correction pulse signal is superimposed on the image reproduction signal based on the output signal from the comparison means. An adder circuit for supplying to a processing clamp circuit, and when the minimum level of the detection output is smaller than the comparison reference level, the signal level of the image reproduction signal in the OB period is corrected by the correction pulse signal. It was done.

Hereinafter, the operation of the present invention will be described.

In the present invention (claim 1), the clamp processing for adjusting the signal level of the image reproduction signal in the OB period corresponding to the light-shielded pixel portion to the reference level is performed by using the OB clamp pulse synchronized with the OB period. An abnormality detection clamp circuit is provided, and an output of the clamp circuit is provided with detection means for detecting a minimum level equal to or lower than the reference level, and the minimum level of the detection output is compared with a comparison reference level. The OB level due to the incidence of an excessively large amount of light is compared to the conventional method of detecting the abnormality of the OB level by comparing the signal level of the OB section of the CCD output with the output level of the horizontal blanking section of the CCD output. Can be detected with a simple circuit configuration.

In the present invention (claim 2), when the minimum level of the detection output is smaller than the comparison reference level, the clamp for adjusting the signal level of the image reproduction signal in the horizontal blanking period to the reference level. Since the processing is performed, even when an excessive amount of light is incident, the display screen does not become a dark screen and image quality is not deteriorated, and a screen suitable for the subject can be obtained.

In the present invention (claim 3), when the minimum level of the detection output is smaller than the comparison reference level, the signal level of the image reproduction signal in the OB period is corrected by the correction pulse signal. The OB level during normal operation is input to the clamp circuit that creates the black level reference on the screen, and the display screen becomes dark even when an excessive amount of light is input. A screen corresponding to is obtained.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of the present invention will be described.

In the signal processing circuit of the solid-state image pickup device of the present invention (claim 1), a clamp circuit for receiving the output of the CDS circuit for processing the CCD output and clamping the signal level during the OB period with the reference voltage (Vc). The signal processing system on the subsequent stage side is divided into two systems, a main processing circuit system for the CDS output and a circuit system for detecting an OB level abnormality.

In the main signal processing system, the CDS output is subjected to gamma correction, pedestal correction, synchronization signal superimposition, etc. on the subsequent stage of the clamp circuit for clamping the CDS output, and is output as a video signal. To be done.

On the other hand, in the circuit system for detecting the abnormality of the OB level, the detection circuit for detecting the negative peak voltage with respect to the reference voltage Vc is detected for the CDS output at the latter stage side of the clamp circuit for performing the clamp processing of the CDS output. A circuit is provided. Here, in the clamp circuit, when unnecessary excess charges are generated in the OB portion of the CCD output, the OB level changed by the unnecessary excess charges is adjusted to the reference voltage Vc.
At this time, in the horizontal blanking period and the video signal period, since there is a signal component equal to or lower than the reference voltage Vc, this level is detected by the negative peak detection circuit and compared with the comparison reference voltage Vc 'by the comparator. When a level equal to or lower than the comparison reference voltage occurs, that is, when an OB level abnormality occurs, the comparator output changes (Hi, L) as compared with a normal case in which no OB level abnormality occurs.
The output of ow changes). As a result, it is detected that an abnormality has occurred in the OB level.

Further, according to the present invention (claim 2), the clamp pulse of the video signal clamp circuit of the main signal processing system is switched based on the signal indicating the occurrence of the abnormality of the OB level. That is, in a normal operation state where there is no abnormality in the OB level, the OB clamp pulse synchronized with the OB period of the CCD output is used as the clamp pulse of the video signal clamp circuit, and when an abnormality occurs in the OB level, As the clamp pulse for the video signal clamp circuit, a clamp pulse synchronized with the horizontal blanking period in the CCD output is used.

Furthermore, the present invention (claim 3) provides the above-mentioned OB.
On the basis of a signal indicating the occurrence of an abnormal level, at the input node of the video signal clamp circuit of the main signal processing system, the signal level in the OB period of the CDS output has a pulse amplitude according to the amount of fluctuation of the OB level, A pulse signal synchronized with the clamp pulse is superimposed, the clamped portion of the CDS output is corrected to the normal level, and then the signal level of the OB period of the CDS output is clamped.

That is, in the signal processing circuit of the solid-state image pickup device of the present invention, an operational amplifier for detecting the level difference between the output of the peak detection circuit and the comparison reference voltage Vc 'and an OB clamp pulse (synchronized with the OB period). , And the amplitude of the inverted pulse is increased / decreased by the level difference between the OB abnormal detection output and the reference voltage Vc. Then, the inversion pulse is superimposed on the signal level of the CDS signal in the OB period by the addition circuit provided in the preceding stage of the video signal clamp circuit in the main signal processing system.

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
2 is a diagram showing a configuration of a signal processing circuit of the solid-state image pickup device according to FIG. 2, and FIG. 2 is a signal waveform diagram for explaining the operation of the signal processing circuit. In the figure, the same reference numerals as those in FIG. 5 denote the same parts as those of the conventional video camera 200. 100
Reference numeral a denotes a signal processing circuit mounted on the CCD video camera according to the first embodiment, which is a CDS circuit 201 for processing a CCD output from a CCD solid-state imaging device having a light-shielding pixel section.
And a predetermined timing signal St together with the CDS output, and based on the timing signal St, the signal level of the predetermined signal period for the CDS output is a reference black level (reference voltage Vc) in the video signal processing. And a first clamp circuit 101 for performing a clamp process according to the above.

Further, the signal processing circuit 100a has a signal level (OB level) in the OB period corresponding to the light-shielded pixel portion.
To the reference voltage Vc by using the reference clamp pulse CP1 synchronized with the OB period, and a detection circuit 103 for detecting the minimum level of the output of the clamp circuit 102 which is equal to or lower than the reference voltage Vc. When,
An operational amplifier (comparator circuit) 104 for comparing the potential level of the detection output with the comparison reference potential Vc 'is provided. The comparison reference voltage Vc 'is set to a level different from the reference voltage Vc so that the circuit operation does not become unstable. Reference numeral 107 is a power supply that supplies a reference voltage Vc, which serves as a reference for the clamp operation, to each of the clamp circuits 101 and 102.

Here, in the detection circuit 103, the cathode is connected to the output of the second clamp circuit 102, the diode D1, the resistor R1 connected between the anode and the power source 107, and the anode. And a capacitor C1 connected between the ground and the ground potential. The anode of the diode D1 is connected to the inverting input of the operational amplifier 104 via the resistor R2. The non-inverting input of the operational amplifier 104 has resistors R3 and R connected in series between the power source 107 and the ground.
It is connected to four connection points.

Further, the signal processing circuit 100a receives an OB clamp pulse CP1 synchronized with the OB period of the CCD output at its A input, and based on this pulse CP1,
Based on the output signal Vs from the monostable multivibrator 105 that outputs the auxiliary clamp pulse CP2 synchronized with the horizontal blanking period other than the OB period of the CCD output from its Q output, the timing signal A switch circuit 106 for switching St between the OB clamp pulse CP1 and the auxiliary clamp pulse CP2 is provided. A resistor R5 and a capacitor C2 are connected in series between the terminal that determines the time constant of the output of the monostable multivibrator 105 and the power supply of the circuit, and these connection points are different from those of the multivibrator 105. Is connected to the power supply side terminal of. The ground side terminal of the multivibrator 105 is grounded.

In the signal processing circuit 100a, when the minimum level Vp of the detection output is smaller than the comparison reference potential Vc ', the signal level of the CCD output in the horizontal blanking period is clamped.

Next, the operation will be described.

In a state where a standard amount of light does not overflow into the OB portion (see FIG. 2A), the OB level matches the black level of the video signal, Peak detection output V by diode D1 shown in FIG.
p is always at a positive level higher than the comparison reference voltage Vc '. In the first embodiment, the comparison reference voltage Vc 'input to the comparator is set to a value slightly lower than the reference voltage Vc in order to prevent malfunction. As a result, the comparator output Vs becomes LOW level (0V), and the switch circuit 10
The output of 6 becomes the OB clamp pulse CP1 that clamps the signal level in the normal OB period.

On the other hand, the irradiation state of an excessive amount of light (see FIG.
In (b)), when the OB level fluctuates due to unnecessary photocharges, the clamp circuit 102 clamps the signal level of the CCD output during the OB period in which the level has fluctuated to the reference voltage Vc by the reference clamp pulse CP1. Therefore, the black level during the video signal period becomes equal to or lower than the reference voltage Vc. As a result, the peak detection output Vp of the diode D1 becomes lower than the reference comparison voltage Vc '.

The comparator 104 compares the comparison reference voltage Vc 'with the peak detection output Vp. In this case, the comparator output Vs becomes high level, which causes the switch circuit 106 to move to the first clamp circuit 10
The timing signal St supplied to 1 is switched from the first clamp pulse CP1 to the second clamp pulse CP2 generated by the monostable multivibrator 105.

The second clamp pulse CP2 is synchronized with the horizontal blanking period in which the level fluctuation due to unnecessary photocharge does not occur even when an excessive amount of light is incident. As a result, the first clamp circuit 101 clamps the signal level of the CDS output in the horizontal blanking period by the second clamp pulse CP2.

As described above, in the first embodiment, when the CCD operates in the normal standard incident state of the amount of light in which no unnecessary signal is generated at the OB level of the CCD output, the output of the second clamp circuit 102 is output. In Sk, as shown in FIG. 2A, the signal level in the video signal period is always a positive level higher than the OB level, and the negative signal peak detection circuit 103
Of the comparator output Vp does not fall below the comparison reference voltage Vc '.
Based on s, the first clamp pulse CP1 for performing the normal OB clamp operation is supplied to the first clamp circuit 101 as the timing signal St.

On the other hand, when an excessive amount of light is incident on the CCD image pickup section and unnecessary photocharges overflow into the OB section of the CCD,
The OB level rises. Therefore, in the OB-clamped signal Sk after the CDS processing, as shown in FIG.
A negative signal level smaller than the B level is obtained, and the output Vp of the peak detection circuit 103 is the comparison reference voltage Vc '.
The following signals are generated. At this time, the switch circuit 106 supplies the second clamp pulse CP2 for clamping the signal level in the horizontal blanking period to the first clamp circuit 101 as the timing signal St based on the comparator output Vs.

As a result, even if an excessive amount of light is input, a dark screen is not generated, and the image quality is not deteriorated, and a screen suitable for the subject can be obtained.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
5 is a diagram showing a configuration of a signal processing circuit of the solid-state imaging device according to FIG. 4, and FIG. 4 is a signal waveform diagram for explaining the operation of the signal processing circuit. In the figure, 100b is the second embodiment.
Is a signal processing circuit mounted on the CCD type video lamella of the above, and is a C from the CCD type solid-state image pickup device having a light-shielding pixel section.
A CDS circuit 201 that processes a CD output, an impedance conversion circuit 118 connected to the output of the CDS circuit 201 via a resistor R11, a clamp pulse CP1 together with the output of the conversion circuit, and the clamp pulse CP1
Based on the above, the OB level of the CDS output is set to the reference black level (reference voltage Vc) in the video signal processing.
Clamp circuit 11 for performing clamp processing according to
1 is provided.

In the conversion circuit 118, the base of the conversion circuit 118 is connected to the output of the CDS circuit 201 through the resistor R11, and the collector of the conversion circuit 118 is connected to the power supply.
18a and a resistor R13 connected between the emitter of the transistor 118a and the ground potential, and the emitter is connected to the input of the first clamp circuit 111. The output Sk1 of the first clamp circuit 111 is
It is supplied to a signal processing unit for generating a video signal.

The signal processing circuit 100b is a CD
For the S output, an abnormality detection clamp circuit (second clamp circuit) 112 that performs a clamp process of adjusting the OB level to the reference voltage Vc by using the OB clamp pulse CP1 and an output Sk2 of the clamp circuit 112. ,
A detection circuit 113 for detecting a negative peak level smaller than the reference voltage Vc, and an operational amplifier (comparison circuit) 1 for comparing the potential level Vp of the detection output with the comparison reference voltage Vc '.
14 is provided. Reference numeral 117 is a power supply that supplies a reference potential Vc to the clamp circuits 111 and 112, which serves as a reference for the clamp operation.

The detection circuit 113 is composed of a diode D11 having a cathode connected to the output of the second clamp circuit 112 and a capacitor C11 connected between the anode and the ground potential. . Also,
The anode of the diode D11 is connected to the inverting input of the operational amplifier 114 via the resistor R14. The non-inverting input of the operational amplifier 114 is connected to the connection point of the resistors R15 and R16 connected in series between the power supply 117 and the ground.

Further, the signal processing circuit 100b receives the output of the detection circuit 113 and the clamp pulse CP1 and generates a pulse signal CPB for compensation, a pulse signal generation circuit 120, and an output signal Vs from the operational amplifier 114. Based on the
And an adding means for adding to the S output.

Here, the pulse signal generating circuit 120 is
The output of the detection circuit 113 has a resistor R1 at its non-inverting input.
An operational amplifier 115, which is supplied via 7 and receives the clamp pulse CP1 via its resistor R21 at its inverting input;
It is composed of a resistor R20 connected between the inverting input and the output of the operational amplifier 115, and resistors R18 and R19 connected in series between the non-inverting input and the inverting input. The connection point between the resistors R18 and R19 is a power supply 117.
It is connected to the. Here, the resistors R20 and R2 are
By changing the value of 1, the output level of the operational amplifier 115 can be adjusted. Further, the adding means is a switch 116a connected to the output of the operational amplifier 114.
A capacitor C12 having one end connected to the output terminal of the switch 114, and a resistor R12 connected between the other end of the capacitor C12 and the input of the impedance conversion circuit 118.

Next, the operation will be described.

The operations of the second clamp circuit 112 and the detection circuit 113 are the same as those of the first embodiment.

In a normal operation state in which a standard amount of light is incident, the floating of the OB level does not occur, and the output Vs of the comparator 114 causes the switch circuit 116a to switch to N level.
The output CPB of the operational amplifier 115 is connected to the terminal on the normal side. Therefore, the CCD output is the CDS as it is.
The first clamp circuit 111 is processed by the circuit 201 and further passes through the resistor R11 and the impedance conversion circuit 118.
Is supplied to. Then, the output of the clamp circuit 111 is subjected to signal processing for generating a video signal in the subsequent stage.

On the other hand, when an excessive amount of light is incident and the OB level fluctuates, the switch circuit 116a determines the operational amplifier 1 based on the output Vs of the abnormality detection comparator 114.
The output CPB of 15 is connected to the High-Light side output terminal. As a result, the output (compensation pulse signal) CPB of the operational amplifier 115 is superimposed on the CDS output in the preceding stage of the first clamp circuit 111.

That is, as shown in FIG. 4B, when the OB level fluctuates due to the incidence of excessive light, the output signal Vp of the peak detection circuit 113 falls below the comparison reference voltage Vc '. At this time, the operational amplifier 115 outputs an inversion pulse CPB of the clamp pulse CP1, and the inversion pulse CPB is the reference signal Vc and the peak detection output Vp.
The amplitude is controlled according to the difference between and. That is, the greater the degree of fluctuation of the OB level, the lower the peak detection output Vp, and the greater the amplitude of the operational amplifier output CPB. Here, Vcp is the operational amplifier 11 described above.
5, the level of the inverting input, v _cp is the clamp pulse CP
This pulse appears at the inverting input of the operational amplifier 115 in synchronization with 1.

In this case, this operational amplifier output CP
B will be added to the CDS output via the capacitor C11 and the resistor R12. This allows CDS
The output waveform (before correction) S1 is changed to the original OB level in which no abnormality occurs during the period in which the OB level is clamped by the clamp pulse CP1, as in the corrected CDS output waveform S2 shown in FIG. 4B. Can be corrected. As a result, in the first clamp circuit 111, the clamp processing is performed on the corrected CDS output S2, and the normal clamp operation is performed even if the OB level fluctuates due to the incidence of excess light. Be seen.

As described above, in the second embodiment, when the excessive light amount is incident, the OB level correction pulse CPB having the pulse amplitude corresponding to the variation amount of the OB level is generated and superposed on the CDS output S1. Therefore, even when an excessive amount of light is incident, it is possible to avoid image quality deterioration in which the screen brightness is reduced and the screen is dark, and it is possible to display an image with a brightness corresponding to the amount of incident light from the subject.

[0066]

As described above, according to the present invention (Claim 1), the fluctuation of the OB level in the CCD output due to the incidence of the excessive light quantity can be prevented from being caused by the signal level below the reference voltage in the CCD output only when the excessive light quantity is incident. Since the detection is performed by utilizing the circuit, it is possible to realize a circuit for detecting an OB level abnormality without malfunction by a simple circuit configuration.

According to the present invention (claim 2), the signal level in the horizontal blanking period of the CCD output which is not affected by the incidence of the excessive light amount is clamped only when the OB level changes due to the incidence of the excessive light amount. Therefore, it is possible to avoid the instability of the screen due to the change of the black level caused by the change of the OB level and the deterioration of the image quality in which the screen is dark despite the bright subject, and the image of the actual subject is more faithfully reproduced. Can be displayed.

According to the present invention (Claim 3), the signal level of the CCD output in the OB period is corrected according to the degree of fluctuation of the OB level due to the incidence of the excessive light amount.
It is possible to avoid instability of the screen due to a change in the black level caused by an abnormal change in the OB level, deterioration of image quality in which the screen is dark despite a bright subject, and an image of an actual subject can be displayed more faithfully.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a signal processing circuit of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the signal processing circuit according to the first embodiment, showing a waveform of a signal processed in the signal processing circuit.

FIG. 3 is a diagram showing a configuration of a signal processing circuit of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the signal processing circuit according to the second embodiment, showing a waveform of a signal processed in the signal processing circuit.

FIG. 5 is a diagram showing a configuration of a conventional general black-and-white CCD camera.

FIG. 6 is a diagram showing waveforms of a CCD output signal and a video output (camera output) signal in the above-mentioned conventional CCD camera in comparison between a normal operation and an OB abnormality due to excessive incident light.

[Explanation of symbols]

 100a, 100b Signal processing circuit 101,111 First clamp circuit 102,112 Second clamp circuit 103,113 Peak detection circuit 104,114 Comparator 105 Monostable multivibrator 106,116a Switch circuit 115 Comparator 118 Impedance conversion circuit 120 Pulse Generation circuit 201 CDS circuit C1, C2, C11, C12 Capacitors D1, D11 Diodes R1 to R5, R11 to R21 Resistances CP1, CP2 First and second clamp pulses St Timing signal Vc Reference potential Vc 'Comparison reference voltage Vp Peak detection Output Vs Comparator output

Claims (3)

[Claims] 1. An image reproduction signal and a predetermined timing signal based on a CCD output from a CCD type solid-state image pickup device having a light-shielded pixel section, and a signal level of the image reproduction signal during a predetermined period is a reference level. A signal processing circuit of a solid-state image pickup device having a function of performing a clamp process for adjusting the signal level, the clamp process for adjusting a signal level of an OB period corresponding to a light-shielded pixel portion of the image reproduction signal to a reference level.
An abnormality detection clamp circuit that uses an OB clamp pulse synchronized with the B period, a detection unit that detects a minimum level of the output of the abnormality detection clamp circuit that is equal to or lower than the reference level, and a minimum level of the detection output. A signal processing circuit of a solid-state imaging device, comprising: a comparison unit that compares a comparison reference level corresponding to the reference level. 2. The signal processing circuit of the solid-state imaging device according to claim 1, wherein an auxiliary clamp pulse synchronized with a horizontal blanking period other than the OB period of the image reproduction signal is generated based on the OB clamp pulse. Pulse generating means for generating, and signal switching means for switching the timing signal between the OB clamp pulse and the auxiliary clamp pulse based on the output signal from the comparing means, and the minimum level of the detection output is A signal processing circuit of a solid-state image pickup device, which is configured to perform a clamp process of adjusting a signal level of a horizontal blanking period of the image reproduction signal to the reference level when the signal is smaller than the comparison reference level. 3. The signal processing circuit of the solid-state image pickup device according to claim 1, wherein as the clamp processing function, a signal for performing a clamp processing for adjusting the signal level of the image reproduction signal during the OB period to the reference level. A correction pulse signal having a processing clamp circuit, receiving a detection output from the detection means, having an amplitude according to a minimum level of the detection output, and having a pulse section synchronized with the OB clamp pulse is generated. A pulse signal generating circuit for generating a pulse signal, and an adding circuit for superimposing the correction pulse signal on the image reproduction signal and supplying the signal processing clamp circuit to the signal processing clamp circuit on the basis of an output signal from the comparing means. When the minimum output level is lower than the comparison reference level, the signal level of the image reproduction signal during the OB period is corrected by the correction pulse signal. The signal processing circuit of the solid-state imaging apparatus that.