JPH09247568A - Image display device - Google Patents

Abstract

An object of the present invention is to provide an image display device which can realize sub-screen processing corresponding to a scanning format of a main-screen signal with a simple structure and can be economically advantageous. There is. SOLUTION: An image signal transmitted by a predetermined method is subjected to thinning processing at a preceding stage of memories 19 and 24 at a thinning rate set according to a format of a main screen signal output from a personal computer. Thus, the thinning means 43 for performing the sub-screen processing is provided, and when the image signals output from the thinning means 43 are written to and read from the memories 19 and 24, the write and read clocks WCK and PCK are given to the memories 19 and 24. The frequency is configured to be fixed to a constant value regardless of the format of the main screen signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention applies main screen processing to RGB signals output from a personal computer and, for example, NTSC (National Television System).
em Committee) method and PAL (Phase Alternation by L)
The present invention relates to an improvement of an image display device in which a sub-screen process is applied to an image signal transmitted by an ine) method or the like to display a multi-screen on the same display.

[0002]

2. Description of the Related Art As is well known, RGB signals output from a personal computer for image display have various formats depending on the mode. Therefore, the same display screen is divided into left and right halves, and the main screen display by RGB signals is performed on the left side.
For example, when a sub-screen is displayed on the right side by an image signal of the NTSC system or the like, it is necessary to perform adaptive processing on the NTSC system image signal of the sub-screen according to the scanning frequency of the RGB signal of the main screen. Occurs.

This process is basically carried out, for example, in NTSC.
Sampling the image signal of the system etc. with a clock having a frequency that can secure a necessary band,
After writing to the field memory, in consideration of the horizontal scanning frequency of the RGB signal and its 1/2 compression processing, the reading is performed using a clock having a frequency higher than the write clock. In practice, it is difficult to implement because there is a limit to the operating frequency of.

Therefore, conventionally, the read clock of the field memory is fixed to a constant frequency, and a VCO (Voltage Control Os) which is an oscillation source of the write clock is used.
Sub-screen processing is realized by preparing a plurality of cillator) and selectively switching a plurality of VCOs according to the mode of the personal computer. FIG.
Shows a conventional image display device provided with a sub-screen processing method for selectively switching a plurality of VCOs according to the mode of the personal computer.

That is, reference numeral 11 in the drawing denotes an input terminal to which an RGB signal to be subjected to main screen processing output from a personal computer (not shown) is supplied. The RGB signal supplied to the input terminal 11 is directly supplied to one input terminal of the selector 12, digitized by the A / D (analog / digital) conversion circuit 13, and horizontally 1 by the compression circuit 14. After being compressed to / 2, D
The analog signal is converted into an analog signal by the / A (digital / analog) conversion circuit 15 and supplied to the other input terminal of the selector 12.

The selector 12 selectively switches between the RGB signal supplied to the input terminal 11 and the RGB signal output from the D / A conversion circuit 15 and compressed in the horizontal direction to ½. It is output to one input terminal of the sub selector 16.

On the other hand, reference numeral 17 in the drawing is an input terminal to which a luminance signal Y included in an image signal of the NTSC system or the like to be subjected to the sub-screen processing is supplied. The luminance signal Y supplied to the input terminal 17 is digitized by the A / D conversion circuit 18 and then supplied to the field memory 19. Reference numerals 20 and 21 in the drawing are input terminals,
Color difference signals I and Q included in the image signal are supplied. Color difference signals I supplied to the input terminals 20 and 21
Q is multiplexed by the multiplexing circuit 22, and the A / D conversion circuit 2
3 is digitized and supplied to the field memory 24.

Reference numeral 25 in the drawing denotes an input terminal, to which the synchronizing signal included in the image signal is supplied. The sync signal supplied to the input terminal 25 is supplied to the write control circuit 26. The write control circuit 26 supplies the write control signal to the field memories 19 and 24 and the write clock generation circuit 2 based on the input synchronizing signal.
7 and the control signal to be given to

The write clock generation circuit 2
7 generates a write clock WCK based on the signal selected by the selector 29 among the oscillation signals output from the plurality of VCOs 281, ..., 28n, and outputs the write clock WCK to the field memories 19 and 24 via the connection terminal 30. It is outputting. As a result, the luminance signal Y supplied to the input terminal 17 and the color difference signal I supplied to the input terminals 20 and 21
Q and Q will be written in the field memories 19 and 24, respectively.

On the other hand, reference numeral 31 in FIG.
The synchronization signal included in the signal is supplied. The sync signal supplied to the input terminal 31 is supplied to the mode detection circuit 32,
Read control circuit 33 and read clock generation circuit 3
4 respectively. Of these, the mode detection circuit 3
Reference numeral 2 detects the mode of the personal computer based on the input synchronizing signal, and controls the switching operation of the selector 29 based on the detection result. The mode detection of the personal computer by the mode detection circuit 32 is realized, for example, by counting the number of horizontal synchronizing signals included in one field period or the number of clocks in one scanning period.

Further, the read control circuit 33, based on the input synchronizing signal, causes the field memory 19,
24 and the read control signal given to the main / sub selector 1
6 and a switching control signal to be given to No. 6 are generated. Also,
The read clock generation circuit 34 generates a read clock RCK based on the input synchronizing signal and outputs it to the field memories 19 and 24 via the connection terminal 35. As a result, the luminance signal Y and the color difference signals I and Q are read out from the field memories 19 and 24, respectively.

In this manner, the luminance signal Y and the color difference signals I and Q read out from the field memories 19 and 24 respectively in synchronization with the RGB signals that form the main screen are subjected to phase adjustment processing and color difference processing in the output processing circuit 36. After the separation processing of the signals I and Q, etc. is performed and after being analogized by the D / A conversion circuit 37,
The RGB signal is converted by the RGB conversion circuit 38 and supplied to the other input terminal of the main / sub selector 16.

The main / sub selector 16 is an RG corresponding to the main screen output from the selector 12 based on the switching control signal output from the read control circuit 33.
The B signal and the RGB signal corresponding to the sub-screen output from the RGB conversion circuit 38 are selectively switched to display 3
In this way, a two-screen display compressed to ½ in the horizontal direction is realized.

The series of operations described above is controlled by the microcomputer 40. That is, the microcomputer 40 generates a control signal for controlling each circuit block,
This control signal is decoded by the decoding circuit 41 and then led to each circuit block via the output terminal 42.

However, in the conventional image display device as described above, R output from the personal computer is used.
In order to perform sub-screen processing corresponding to various scanning formats of the GB signal, it is necessary to generate the write clock WCK to be supplied to the field memories 19 and 24 in accordance with the mode of the personal computer. Since it is necessary to install the VCOs 281, ..., 28n in advance, there arises a problem that the structure is complicated, the size becomes large, and it becomes economically disadvantageous.

Further, the horizontal scanning frequency of the RGB signal corresponding to the main screen output from the personal computer is 3 times the horizontal scanning frequency of the NTSC system image signal serving as the sub-screen.
When performing dual screen display in which the main screen and the sub screen are each horizontally compressed by 1/2 in the state of about 45 kHz, the frequency of the write clock WCK given to the field memories 19 and 24 is set to the image band in the NTSC system. If the frequency is set to about 10 MHz in consideration of the above, the frequency of the read clock RCK given to the field memories 19 and 24 is required to be about 6 times that of 60 MHz.

As described above, the read clock RC
How many times the frequency of the write clock WCK is required as K is determined by the display mode and the horizontal scanning frequency of the RGB signal output from the personal computer.

By the way, there is no memory capable of operating with a read clock having a high frequency of about 60 MHz at present, and even if it can be manufactured,
The cost becomes too high, which makes it unsuitable for practical use. Therefore, if the frequency of the read clock is set to a low value according to reality, the write clock is set to a low frequency accordingly.

In this case, it is necessary to change the characteristics of a front LPF (Low Pass Filter) (not shown) through which the luminance signal Y of the sub-screen passes, in order not to generate folding noise in the image displayed on the screen. There is also a problem in that the characteristics must be changed according to the horizontal scanning frequency of the RGB signal which is the main screen.

[0020]

As described above, in the conventional image display device, VCOs corresponding to the number of modes of the personal computer are installed in advance in order to perform sub-screen processing corresponding to the scanning format of the main-screen signal. However, there is a problem in that the structure is complicated and large in size, which is economically disadvantageous. There is also a problem in that the characteristics of the front LPF through which the luminance signal of the sub-screen passes must be changed according to the horizontal scanning frequency of the main-screen signal.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to realize the sub-screen processing corresponding to the scanning format of the main screen signal with a simple structure, which is economically advantageous. It is an object of the present invention to provide an extremely good image display device capable of performing the above.

[0022]

An image display device according to the present invention uses a memory for a main screen signal output from a personal computer and an image signal transmitted by a predetermined method, and according to the format of the main screen signal. It is intended for multi-screen display on the same screen with a sub-screen signal obtained by performing the sub-screen processing.

Further, a thinning means is provided in the preceding stage of the memory for thinning the image signal at a thinning rate set according to the format of the main screen signal, and the image signal output from the thinning means is sent to the memory. When writing and reading, the frequencies of the writing and reading clocks given to the memory are fixed to fixed values irrespective of the format of the main screen signal.

According to the above-mentioned configuration, the thinning-out means for performing the thinning-out process on the image signal transmitted by the predetermined method in the preceding stage of the memory at the thinning-out ratio set according to the format of the main screen signal. Since the frequency of the write and read clocks given to the memory is fixed to a fixed value independently of the format of the main screen signal, a simple configuration for sub-screen processing corresponding to the format of the main screen signal is provided. It is possible to realize it with, and it can be economically advantageous.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIG. 1 shows RGB output from a personal computer (not shown).
1 shows a first embodiment of an image display device that performs dual-screen display by using a signal as a main screen and an NTSC image signal as a sub-screen. In FIG. 1, the same parts as those in FIG. 8 are designated by the same reference numerals.

That is, the luminance signal Y digitized by the A / D conversion circuit 18 is supplied to the horizontal thinning circuit 43. The horizontal thinning circuit 43 incorporates a front LPF (not shown), changes the characteristics of the front LPF based on the horizontal thinning control signal output from the write control circuit 26, and inputs it. After the folding noise is removed from the digital luminance signal Y by band limitation, pixels in the horizontal direction are thinned out. This results in the same state as when the sampling rate of the A / D conversion circuit 18 is changed.

The output of the horizontal thinning circuit 43 is
It is supplied to the field memory 19. The write control circuit 26 generates a write control signal to be supplied to the field memories 19 and 24 and a control signal to be supplied to the write clock generation circuit 27, and also uses the mode detection signal of the personal computer output from the mode detection circuit 32. Based on this, the horizontal thinning control signal is also generated.

On the other hand, the color difference signals I and Q digitized by the A / D conversion circuit 23 are supplied to the horizontal thinning circuit 44. A horizontal thinning control signal output from the write control circuit 26 is supplied to the horizontal thinning circuit 44 at the connection terminal 4
5 is supplied. Then, the horizontal thinning circuit 44
Thins out pixels in the horizontal direction from the input digital color difference signals I and Q based on the horizontal thinning control signal. After that, the output of the horizontal thinning circuit 44 is supplied to the field memory 24.

Further, the write clock generating circuit 27
Generates a write clock WCK to be supplied to the field memories 19 and 24 based on the oscillation signal output from one VCO 46.

Here, FIG. 2 shows the scanning formats of the RGB signals output corresponding to various modes of the personal computer, and the image signals of the NTSC system in the horizontal direction so as to correspond to these various scanning formats. The relationship with the thinning rate for thinning is shown. However, in this case, the frequency of the write clock WCK is set to 9.
45 MHz, and the frequency of the read clock RCK is 3
The frequency is 7.8 MHz, and the effective rate for one horizontal pixel is 85%.

Then, the horizontal thinning circuits 43 and 4 described above are used.
Reference numeral 4 indicates a horizontal direction with respect to the input digital luminance signal Y and digital color difference signals I and Q at the thinning rate shown in FIG. 2 based on the mode detection signal of the personal computer output from the mode detection circuit 32. Pixels are thinned out.

Further, when the number of lines in one field period is considerably different between the RGB signal for main screen processing and the image signal for sub screen processing, display by continuous line reading as shown in FIG. 1 as shown in FIG.
It is possible to appropriately perform a plurality of types of display, such as interlaced display by line-by-line reading and display positions of the main screen and the sub screen which are reversed left and right.

In FIG. 3, the solid line is the data read line, the dotted line is the operation stop line, and the shaded area is the non-image area (not related to the number of lines on the main screen). In some cases).

Therefore, according to the above-described first embodiment, in accordance with the mode of the personal computer,
The sub-screen processing is performed by thinning out pixels in the horizontal direction of the image signal to be the sub-screen.
The write clock WCK given to 24 is one VCO.
Since it is generated based on the oscillating signal output from 46, the sub-screen processing corresponding to the scanning format of the RGB signal which is the main screen can be realized with a simple configuration, which is economically advantageous. be able to.

Next, FIG. 4 shows a second embodiment of the present invention, in which a sub-screen composed of an image signal of NTSC system is provided in a main screen composed of RGB signals output from a personal computer. Insert the so-called PIP (Pi (Pi
cture In Picture) is displayed. 4, the same parts as those in FIG. 1 are designated by the same reference numerals.

In this case, the selector 12 is switched so as to lead the RGB signals supplied to the input terminal 11 to the main / sub selector 16. In addition, the horizontal thinning circuit 4
Digital luminance signal Y in which pixels are thinned out in 3 in the horizontal direction
Is supplied to the vertical thinning circuit 47. The vertical thinning circuit 47 thins the input digital luminance signal Y in the vertical direction, that is, lines based on the vertical thinning control signal output from the write control circuit 26.

The output of the vertical thinning circuit 47 is
It is supplied to the field memory 19. The write control circuit 26 includes a write control signal for the field memories 19 and 24 and a write clock generation circuit 2.
7 and the horizontal thinning control signal given to the horizontal thinning circuit 43 are generated, and the vertical thinning circuit 47 is configured to set the number of lines specified by the microcomputer 40 with respect to the number of lines of the main screen. A vertical thinning control signal for thinning lines is generated.

On the other hand, the digital color difference signals I and Q from which pixels have been horizontally thinned by the horizontal thinning circuit 44 are supplied to the vertical thinning circuit 48. The vertical thinning control signal output from the write control circuit 26 is supplied to the vertical thinning circuit 48 via a connection terminal 49. And
The vertical thinning circuit 48 thins the lines of the input digital color difference signals I and Q based on the vertical thinning control signal, and outputs the thinned lines to the field memory 24.

According to the above-described second embodiment, PIP display can be realized without impairing the effects of the above-described first embodiment. Next, FIG.
Shows a third embodiment of the present invention, and the same portions as those in FIG. 4 are denoted by the same reference numerals. That is,
In the third embodiment, the mode detection circuit 32 is deleted so that the mode of the personal computer is not automatically detected. Then, based on an instruction from the microcomputer 40, the write control circuit 26 generates a horizontal thinning control signal and a vertical thinning control signal, respectively, so that the horizontal and vertical thinning rate of the sub-screen signal can be arbitrarily changed. If possible, a dual screen display is realized.

FIG. 6 shows a fourth embodiment of the present invention, in which the same parts as those in FIG. 4 are designated by the same reference numerals. That is, in the fourth embodiment, the horizontal thinning circuit 44, the vertical thinning circuit 48 and the field memory 24 are deleted, and the luminance signal Y digitized by the A / D conversion circuit 18 and the A / D conversion circuit 18 are deleted. The color difference signals I and Q digitized by the D conversion circuit 23 are multiplexed by being switched by the selector 50 for each sample and derived.

Then, the multiplexed signals Y, I, Q
However, the horizontal thinning circuit 43 performs thinning processing on pixels in the horizontal direction, the vertical thinning circuit 47 performs thinning processing on lines, and then, the data is written in the field memory 19. Further, the multiplexed signals Y, I, and Q read from the field memory 19 are separated into the luminance signal Y and the color difference signals I and Q by the output processing circuit 36, and output processing is performed. Will be realized.

According to the fourth embodiment, the horizontal thinning circuits 43 and 44, the vertical thinning circuits 47 and 48, and the field memory 19 which require two systems for the luminance signal Y and the color difference signals I and Q are used. , 24 can be reduced to one system, and the simplification of the configuration can be further promoted.

Next, FIG. 7 shows a fifth embodiment of the present invention, in which the same parts as those in FIG. 6 are designated by the same reference numerals. That is, in the fifth embodiment, the multiplexed signals Y, I, and
The data rate is lowered by converting Q into parallel data by an S / P (Serial / Parallel) conversion circuit 51, and then written into the two field memories 52 and 53. In this case, the S / P conversion ratio is 2: 1, but it can be changed by further increasing the number of field memories.

A plurality of signals read from the field memories 52 and 53 in synchronism with the main screen are P / S.
After being converted into serial data by the (Parallel / Serial) conversion circuit 54, output processing is performed by the output processing circuit 36 to realize a two-screen display. As a result, the frequencies of the write clock WCK and the read clock RCK of the field memories 52 and 53 can be reduced, and further, the horizontal and vertical thinning circuits can be reduced to one system. It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the present invention.

[0045]

As described in detail above, according to the present invention,
The sub-screen processing corresponding to the scanning format of the main screen signal can be realized with a simple configuration, and an extremely good image display device that can be economically advantageous can be provided.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of an image display device according to the present invention.

FIG. 2 is a diagram showing a relationship between a scanning format of a main screen signal and a thinning rate of a sub screen signal in the first embodiment.

FIG. 3 is a diagram showing an example of a two-screen display according to the first embodiment.

FIG. 4 is a block configuration diagram showing a second embodiment of an image display device according to the present invention.

FIG. 5 is a block configuration diagram showing a third embodiment of an image display device according to the present invention.

FIG. 6 is a block configuration diagram showing a fourth embodiment of an image display device according to the present invention.

FIG. 7 is a block configuration diagram showing a fifth embodiment of an image display device according to the present invention.

FIG. 8 is a block configuration diagram showing a conventional image display device.

[Explanation of symbols]

 11 ... Input terminal, 12 ... Selector, 13 ... A / D conversion circuit, 14 ... Compression circuit, 15 ... D / A conversion circuit, 16 ... Main / sub selector, 17 ... Input terminal, 18 ... A / D conversion circuit, 19 ... field memory, 20, 21 ... input terminal, 22 ... multiplexing circuit, 23 ... A / D conversion circuit, 24 ... field memory, 25 ... input terminal, 26 ... write control circuit, 27 ... write clock generation circuit, 281-1 28n ... VCO, 29 ... Selector, 30 ... Connection terminal, 31 ... Input terminal, 32 ... Mode detection circuit, 33 ... Read control circuit, 34 ... Read clock generation circuit, 35 ... Connection terminal, 36 ... Output processing circuit, 37 ... D / A conversion circuit, 38 ... RGB conversion circuit, 39 ... Display, 40 ... Microcomputer, 41 ... Decoding circuit, 42 ... Output terminal, 43, 44 ... Horizontal thinning circuit, 45 ... Connection terminal, 46 ... VCO, 47, 48 ... Vertical thinning circuit, 49 ... Connection terminal, 50 ... Selector, 51 ... S / P conversion circuit, 52, 53 ... Field memory , 54 ... P / S conversion circuit.

Continuation of the front page (72) Inventor Shigeki Kamimura 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E. Co., Ltd.

Claims (5)

[Claims] 1. A main screen signal output from a personal computer and a sub screen signal obtained by subjecting an image signal transmitted by a predetermined method to a sub screen processing according to a format of the main screen signal using a memory. In the image display device for multi-screen display on the same screen, a thinning means for performing thinning processing on the image signal at a thinning rate set according to the format of the main screen signal is provided in the preceding stage of the memory, When writing and reading the image signal output from the thinning-out means to and from the memory, the write and read clock frequencies given to the memory are fixed to fixed values irrespective of the format of the main screen signal. An image display device characterized by the following. 2. The first thinning means for thinning the luminance signal contained in the image signal at a thinning rate set according to the format of the main screen signal, and the image signal. Second thinning-out means for thinning out the color difference signal included in the first thinning-out means at the thinning-out ratio set in the first thinning-out means, and the memory outputs the luminance signal output from the first thinning-out means. And a second memory in which the color difference signals output from the second thinning means are written and read.
The image display device as described in the above. 3. The image display device according to claim 1, wherein the thinning means comprises horizontal thinning means for thinning out the image signals in the horizontal direction, and vertical thinning means for thinning out the lines of the image signals. 4. A detection means for automatically detecting the format of the main screen signal based on a synchronization signal included in the main screen signal, wherein the thinning means sets a thinning rate based on the detection result of the detection means. The image display device according to claim 1, wherein: 5. The image display device according to claim 1, further comprising input means for setting a thinning rate of the thinning means by an external operation.