JPH09252116A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce junction capacitance between a gate electrode and an impurity diffusion layer by separating the gate electrode and the diffusion layer by utilizing a groove formed to a substrate in a MOS transistor to be fined. SOLUTION: In a semiconductor device, a groove is formed to a substrate 1 on the drain diffusion layer 24, 25 sides, and a side wall spacer is formed so as to bury the groove. A layer insulating film 26 consisting of a BPSG film is formed on the whole surface of the substrate, and contact holes are shaped onto an N<+> type source-drain diffusion layer 24 and a P<+> type source-drain diffusion layer 25. Barrier films 27 composed of a titanium film and a titanium nitride film and metal electrodes 28 made up of an aluminum film are formed. Through the contact holes. Accordingly, fining is conducted, junction capacitance between a polycide-gate gate electrode and the drain diffusion layer is reduced, the depth of the drain diffusion layers 24, 25 can be deepened, and a power- supply voltage can be maintained at approximately 5V in accordance with conventional devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, in a miniaturized MOS transistor, by separating a gate electrode and an impurity diffusion layer by utilizing a groove formed in a substrate, The present invention relates to a technique for reducing the junction capacitance between a gate electrode and a diffusion layer.

[0002]

2. Description of the Related Art A semiconductor device in which a junction capacitance on the drain diffusion layer side is reduced in a miniaturized MOS transistor will be described below. First, in the conventional first semiconductor device shown in FIG. 11, the gate electrode made of a polysilicon film and the drain diffusion layer are separated by using the gate bird's beak technique. That is, for example, a P-type semiconductor substrate 5
1. A gate insulating film 53 having a thickness of about 140Å is formed on an element forming region surrounded by a LOCOS oxide film 52 as an element isolation film formed on the first insulating film 52, and about 2500Å by LPCVD on the gate insulating film 54. After forming the polysilicon film having the film thickness of, the gate electrode 54 having a gate length of about 0.7 μm is formed by patterning by a known patterning technique. Then, the gate electrode 5
Using 4 as a mask, for example, phosphorus ions (31P +) are accelerated at an acceleration voltage of 300 KeV and the dose is 1E13 / cm @ 2.
(Note that 1E13 means 1 times 10 to the 13th power. The same applies hereinafter), and an N − layer is formed so as to be adjacent to the gate electrode 54. Furthermore, the gate electrode 5
A side wall spacer 55 having a spacer width of about 0.15 μm is formed on the side wall portion of No. 4. Subsequently, using the gate electrode 54 and the sidewall spacer 55 as a mask, arsenic ions (75 As +) are accelerated at an acceleration voltage of about 60K.
After injection under the conditions of eV and an injection amount of 5E15 / cm2,
As shown in FIG. 11, thermal oxidation is performed in an O 2 atmosphere at about 900 ° C. for 3 hours to thermally oxidize the insulating film in the region not covered by the gate electrode 54 and the sidewall spacers 55, and the thickness of about 1500 Å. A thick insulating film 56 is formed, and a high-concentration N + type source / drain diffusion layer 57 is formed thereunder. Reference numeral 58 represents the diffusion of the above-mentioned pocket ion-implanted N-type layer by the thermal oxidation.

In the above-described semiconductor device, the junction capacitance between the gate electrode and the drain diffusion layer can be reduced by the gate bird's beak technique, but the N by thermal oxidation is reduced.
Since the diffusion is performed in consideration of the spread of the mold layer 58, the gate length of the gate electrode was not miniaturized. Next, FIG.
In the second conventional semiconductor device shown in FIG. 2, the gate electrode is formed of, for example, a polysilicon film and tungsten silicide (W
In the polycide gate structure made of a (Six) film, peeling occurs in the tungsten silicide film in the polycide gate electrode by the above-mentioned thermal oxidation method, so that the above-mentioned gate bird's beak technique cannot be used and the speedup is increased. By using an oxidation technique, the gate insulating film is made thick before the formation of the polycide gate electrode to reduce the junction capacitance between the gate electrode and the drain diffusion layer. That is, for example, phosphorus ions (31 P +) are implanted at an accelerating voltage of 100 KeV with a resist film (not shown) as a mask only in a certain region on the element formation region surrounded by the LOCOS oxide film 62 formed on the P type semiconductor substrate 61. Implantation is performed under the condition of an amount of 5E14 / cm @ 2 to form an N @ + type layer 63. Next, the entire surface of the substrate is thermally oxidized to form a gate insulating film 64 having a film thickness of about 140Å. By this oxidation step, the region in contact with the N + type layer 63 is subjected to accelerated oxidation to form a thick insulating film 65.
Then, the polysilicon film 66 and the tungsten silicide (WSi) are formed so as to extend over the insulating film 64 and the insulating film 65.
x) After forming a polycide gate electrode 68 made of the film 67 and having a gate length of about 2.0 μm, a sidewall spacer 69 having a spacer width of about 0.15 μm is formed on the side wall portion of the polycide gate electrode 68. To do. Then, using the sidewall spacers 69 covering the polycide gate electrodes 68 as a mask, ion implantation for forming source / drain diffusion layers is performed, and high concentration N ++
A source / drain diffusion layer 70 of the mold is formed.

In the semiconductor device described above, the N + type layer 6 is used although the junction capacitance between the polycide gate electrode and the drain diffusion layer can be reduced by the accelerated oxidation technique.
3 and a polycide gate electrode pattern when forming a resist film with a resist film, a sufficient space is secured for the positional deviation at the time of mask alignment, and an N + type layer and about 140
The gate length of the polycide gate electrode could not be miniaturized because it needs to overlap with a thin gate oxide film of about Å to cause thermal diffusion.

The conventional third semiconductor device shown in FIG. 13 has an LDD (Lightly Doped) for prioritizing miniaturization.
The gate electrode 74 is formed on the element formation region surrounded by the LOCOS oxide film 72 formed on the P-type semiconductor substrate 71 through the gate insulating film 73, and then the gate electrode 74 is formed. N − -type impurities are ion-implanted using 74 as a mask to form an N − -type source / drain diffusion layer 75. Next, after forming a sidewall spacer 76 on the sidewall of the gate electrode 74, the gate electrode 74 and the sidewall spacer 76 are used as a mask for N
Ion implantation of + type impurities is performed to form N + type source / drain diffusion layers 77.

Although the above-mentioned semiconductor device can be miniaturized, the above-mentioned junction capacitance becomes large and the junction breakdown voltage becomes low. Therefore, the power supply voltage had to be lower than 5V, for example.

[0007]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor device which can reduce the junction capacitance between the gate electrode and the drain diffusion layer and can be miniaturized, and a manufacturing method thereof.

[0008]

In view of the above, a semiconductor device of the present invention includes a gate electrode formed on a device forming region on a semiconductor substrate of one conductivity type via a gate insulating film, and adjacent to the gate electrode. A groove formed on at least one diffusion layer formation region side of the substrate, a sidewall spacer that fills the groove and covers the gate electrode, and a source / drain diffusion layer formed adjacent to the sidewall spacer And a metal electrode contacting the source / drain diffusion layer through a contact hole formed in the interlayer insulating film formed on the entire surface of the substrate.

Further, a method for manufacturing a semiconductor device according to the present invention
A step of forming a gate electrode on a device formation region surrounded by a device isolation film on a semiconductor substrate of one conductivity type through a gate insulating film; and using the resist film formed on the substrate as a mask to form the gate electrode A step of forming a groove on at least one diffusion layer formation region side of an adjacent substrate; and a sidewall spacer so as to fill the groove and cover the gate electrode by forming an insulating film on the entire surface of the substrate and then etching the entire surface. And a step of forming a source / drain diffusion layer of a reverse conductivity type so as to be adjacent to the sidewall spacer by implanting an impurity of a reverse conductivity type with the element isolation film and the sidewall spacer as a mask. When,
After forming an interlayer insulating film on the entire surface of the substrate, forming a metal electrode that contacts the source / drain diffusion layer through a contact hole formed in the interlayer insulating film.

Furthermore, the method of manufacturing a semiconductor device of the present invention is
A step of forming a gate electrode on a device formation region surrounded by a device isolation film on a semiconductor substrate of one conductivity type through a gate insulating film; and using the resist film formed on the substrate as a mask to form the gate electrode A step of forming a groove on at least one diffusion layer formation region side of an adjacent substrate; and a step of implanting a low concentration impurity of opposite conductivity type directly below the groove using the resist film formed on the substrate as a mask. Forming a low-concentration reverse-conductivity-type layer directly under the groove; and forming an insulating film on the entire surface of the substrate and then etching the entire surface to fill the groove and form a sidewall spacer so as to cover the gate electrode. Step, using the element isolation film and the sidewall spacer as a mask, injecting a high concentration of an impurity of the opposite conductivity type so as to be adjacent to the sidewall spacer. Forming a source / drain diffusion layer and contacting the high-concentration reverse conductivity type source / drain diffusion layer through a contact hole formed in the interlayer insulating film after forming an interlayer insulating film on the entire surface of the substrate. And the step of forming a metal electrode.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method of manufacturing a semiconductor device of the present invention will be described below with reference to the drawings of FIGS. First, as shown in FIG. 1, a LOCOS oxide film 4 having a thickness of about 7,000 Å is formed as an element isolation film on a P well 2 and an N well 3 formed on a semiconductor substrate 1 of one conductivity type, for example, P type. A gate oxide film 5 having a film thickness of approximately 140 Å is formed on the element formation region. Of course, ion implantation for threshold adjustment is performed in the substrate in the element formation region.

Next, a polysilicon film having a film thickness of about 1000 Å is formed on the entire surface of the substrate by a LPCVD method, and a tungsten silicide film (WSix) having a film thickness of about 1000 Å is formed thereon by a LPCVD method and a polysilicon film having a film thickness of about 2000 Å by the LPCVD method. After forming a SiO2 film having a film thickness, etching for forming a gate electrode is performed using the resist film 6 as a mask as shown in FIG.
A polycide gate electrode 10 having a gate length of about 0.35 μm, which is composed of a polysilicon film 8 having a 2 film 7 and a tungsten silicide film 9, is formed.

Then, as shown in FIG. 3, a resist film 11 is formed.
As a mask, N-channel type MOS transistor and P
The substrate on the side of forming each drain diffusion layer of the channel type MOS transistor is etched to form the polycide gate electrode 10
A groove 12 having a depth and a width of about 0.15 μm is formed from the end of the groove 12. Next, as shown in FIG. 4, a resist film 13 is formed so as to close the groove 12 on the N-channel MOS transistor side, and first pocket ion implantation is performed under the groove 12 on the P-channel MOS transistor side. That is, for example, phosphorus ions (31P +) are used for acceleration voltage of about 150 Ke.
Implantation is performed under the conditions of V and an implantation amount of 2E13 / cm @ 2 to deeply form the first N @-type layer 14 below the groove 12. Subsequently, for example, boron ions (11B +) are accelerated at an acceleration voltage of 40 Ke.
Implantation is performed under the conditions of V and an implantation amount of 8E11 / cm @ 2 to form a first P @-type layer 15 below the N @-type layer 14 under the groove 12. As shown in FIG.

Similarly, the second pocket ion implantation is also performed below the trench 12 on the N-channel MOS transistor side. In this case, for example, boron ions (11B +) are implanted under the conditions of an accelerating voltage of 160 KeV and an implantation dose of 2E13 / cm2 to form a deep second P-type layer 16 below the groove 12, and then, for example, arsenic. Ions (75 As +) are implanted under the conditions of an accelerating voltage of 80 KeV and an implantation dose of 4E13 / cm @ 2, and are shallower than the P @-type layer 16 under the groove 12
The N- type layer 17 is formed (see FIG. 5).

Subsequently, as shown in FIG. 5, the groove 12 is formed by using a resist film 19 including at least the groove 12 on the N-channel MOS transistor side and having an opening 18 larger than the groove 12 as a mask. On the side wall of the
Perform pocket ion implantation. In this case, for example, boron ions (11B +) are implanted under the conditions of an accelerating voltage of 160 KeV and an implantation dose of 2E13 / cm2 to form a deep third P- type layer 20 in the substrate adjacent to the sidewall of the groove 12. ,
Subsequently, for example, arsenic ions (75 As @ +) are implanted under the conditions of an accelerating voltage of 80 KeV and an implantation amount of 4E13 / cm @ 2 to form a third N @-type layer 21 shallower than the P @-type layer 20.

Next, after removing the resist film 19, an SiO2 film having a film thickness of about 2000 Å is formed on the entire surface of the substrate by the LPCVD method so as to completely fill the groove 12, and then the entire surface is etched. As shown in FIG. 2, the sidewall of the polycide gate electrode 10 is covered with the groove 12 so as to have a thickness of about 0.15 μm.
Sidewall spacers 22 having a spacer width of m and a depth of approximately 0.18 μm are formed, followed by thermal oxidation for 60 minutes in an N 2 / O 2 atmosphere at approximately 800 ° C.

Subsequently, as shown in FIG. 7, a resist film 23 is formed on the N well region 3, and then the sidewall film 22 which covers the resist film 23 and the polycide gate electrode 10 is used as a mask, for example. Arsenic ions (75 As +) are accelerated at an acceleration voltage of 100 KeV and an injection amount of 5
By implanting under the condition of E15 / cm @ 2, a high concentration N @ + type source / drain diffusion layer 24 is formed so as to be adjacent to the sidewall spacer 22. Similarly, after forming a resist film (not shown) on the P well region 2, using the sidewall spacer 22 covering the resist film and the polycide gate electrode 10 as a mask, for example, boron difluoride ion (49BF2 +) Acceleration voltage of 60 Ke
Implantation is performed under the conditions of V and an implantation amount of 5E15 / cm @ 2 to form a high concentration P @ + type source / drain diffusion layer 25 adjacent to the sidewall spacer 22 (see FIG. 8).
Then, annealing is performed in an O2 atmosphere at about 800 DEG C. for 30 minutes, and then in an N2 atmosphere at about 900 DEG C. for about 60 minutes. As a result, as shown in FIG.
The P− type layer 15 and the second N− type layer 17 are diffused and reach immediately below the gate. Further, the first N- type layer 14 and the second P- type layer 16 are also diffused. At this time, as shown in FIG. 8, the depth (XjN) of the N + type drain diffusion layer 24 of the P channel type MOS transistor is about 0.25 μm.
The depth (XjP) of the P + type drain diffusion layer 25 of the N channel type MOS transistor is about 0.3 μm.

Next, as shown in FIG. 9, after an interlayer insulating film 26 made of, for example, a BPSG film is formed on the entire surface of the substrate, the N + type source / drain diffusion layer 24 and the P + type source / drain diffusion layer 25 are formed. A contact hole is formed in. Then, a barrier film 27 made of a titanium (Ti) film and a titanium nitride (TiN) film is provided through the contact hole.
And a metal electrode 28 made of an aluminum (Al) film is formed.

A semiconductor device according to an embodiment of the present invention is manufactured through the above steps. Another embodiment of the present invention will be described with reference to FIG. The semiconductor device in this case is one in which the impurity layer is not ion-implanted under the groove 12 after the groove 12 according to the first embodiment is formed (see FIG. 3), and the groove is formed by the manufacturing method described above. After forming the side wall spacer 22 on the side wall of the polycide gate electrode 10 so as to bury the metal 12 therein, ion implantation is performed as described above, and the side wall spacer 22 is formed in an O2 atmosphere at 800.degree.
0 minutes, then 30 minutes in N2 atmosphere at about 1000 ° C
By annealing for about a minute, as shown in FIG. 10, an N + type source / drain diffusion layer 24A and a P + type source / drain diffusion layer 24A are formed.
The drain diffusion layer 25A is deeply formed. At this time, the N + type drain diffusion layer 2 of the P channel type MOS transistor
The depth (XjN) of 4A is about 0.32 μm, and the P + type drain diffusion layer 25 of the N channel type MOS transistor is formed.
The depth of A (XjP) is about 0.4 μm.

The semiconductor device manufactured by the above steps is
Since the structure is such that the groove is formed in the substrate on the side of the drain diffusion layer and the side wall spacer is formed so as to fill the groove, the drawbacks of the respective semiconductor devices described in the prior art can be solved, that is, miniaturization is achieved. The junction capacitance between the polycide gate electrode and the drain diffusion layer can be reduced, the depth of the drain diffusion layer (XjN, XjP) can be further increased, and the power supply voltage can be maintained at about 5V as in the conventional case.

[0021]

As described above, according to the semiconductor device manufactured by the present invention, the gate electrode line width can be reduced to about 0.35 μm. Further, the junction capacitance between the gate electrode and the drain diffusion layer can be reduced, the depth (XjN, XjP) of the drain diffusion layer can be further increased, and the power supply voltage can be maintained at about 5V as in the conventional case.

Further, the low-concentration drain diffusion layer is not located immediately below the high-concentration drain diffusion layer, and a groove formed on the low-concentration drain diffusion layer is about 200.
Since the SiO2 film having a thickness of about 0Å is formed so as to be positioned, it has an advantage of being resistant to electrostatic breakdown.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a sixth cross-sectional view showing the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a seventh cross-sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 8 is an eighth cross-sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 9 is a ninth cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing a semiconductor device of another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a first conventional semiconductor device.

FIG. 12 is a cross-sectional view showing a second conventional semiconductor device.

FIG. 13 is a sectional view showing a third conventional semiconductor device.

Claims (3)

[Claims] 1. A gate electrode formed on a device formation region on a semiconductor substrate of one conductivity type via a gate insulating film, and formed on at least one diffusion layer formation region side of a substrate adjacent to the gate electrode. Groove, a sidewall spacer that fills the groove and covers the gate electrode, a source / drain diffusion layer formed adjacent to the sidewall spacer, and an interlayer insulating film formed over the entire surface of the substrate And a metal electrode contacting the source / drain diffusion layer through the formed contact hole. 2. A step of forming a gate electrode on a device formation region surrounded by a device isolation film on a semiconductor substrate of one conductivity type via a gate insulating film, and using the resist film formed on the substrate as a mask. Forming a groove on at least one diffusion layer formation region side of the substrate adjacent to the gate electrode, and forming an insulating film on the entire surface of the substrate and then etching the entire surface to fill the groove and cover the gate electrode. Forming a side wall spacer as described above, and using the element isolation film and the side wall spacer as a mask, implanting an impurity of a reverse conductivity type to diffuse a source / drain of a reverse conductivity type so as to be adjacent to the sidewall spacer. A step of forming a layer, and the source / drain through a contact hole formed in the interlayer insulating film after forming an interlayer insulating film on the entire surface of the substrate. The method of manufacturing a semiconductor device characterized by comprising a step of forming a metal electrode to contact the distributed layer. 3. A step of forming a gate electrode through a gate insulating film on an element formation region surrounded by an element isolation film on a semiconductor substrate of one conductivity type, and using the resist film formed on the substrate as a mask. Forming a groove on at least one diffusion layer formation region side of the substrate adjacent to the gate electrode, and using a resist film formed on the substrate as a mask, a low-concentration reverse conductivity type impurity is directly formed under the groove. To form a low-concentration reverse-conductivity type layer directly under the groove, and after the insulating film is formed on the entire surface of the substrate, the entire surface is etched to fill the groove and cover the gate electrode. A step of forming a wall spacer; and a step of implanting a high-concentration impurity of the opposite conductivity type by using the element isolation film and the sidewall spacer as a mask so as to be adjacent to the sidewall spacer. A step of forming a source / drain diffusion layer of reverse conductivity type, and a step of forming the source / drain diffusion layer of high concentration through a contact hole formed in the interlayer insulation film after forming an interlayer insulating film on the entire surface of the substrate. And a step of forming a metal electrode in contact with the drain diffusion layer.