JPH09283716A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-withstanding voltage isolation, without increasing the process cost by connecting through conductive lines regions having conductivities of relatively low impurity concn. and regions formed between principal planes of a semiconductor substrate through an insulation film. SOLUTION: N-type diffused regions 12a, 12b form resurf structures surrounded with n-type diffused regions 2a which are partly slit into divisions. The semiconductor device comprises nch resurf MOSFET regions and resurf isolated island regions. Al electrodes 10 are formed adjacent to n-type and p-type diffused regions 5, 6 and have the same potential as that of resurf isolated islands. A gate electrode 9 is positively biased to flow a current in the p-type diffused region 6 to cause a potential difference between the electrode 10 and Al interconnection 8. This provides a level shift function to a high withstanding voltage region, reduces the area and suppresses the process cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device having a high breakdown voltage isolation region.

[0002]

2. Description of the Related Art As a high breakdown voltage semiconductor device having a high breakdown voltage isolation region, one using a RESURF structure has been conventionally known (for example, see USP 4292642). FIG.
FIG. 1 shows a sectional view of the structure of a semiconductor device having a level shift function using a conventional high breakdown voltage RESURF structure. As shown in this figure, this semiconductor device is composed of an n ch-resurf MOSFET on the left side of the figure and a resurf isolation island region on the right side of the figure and reaches the p-substrate 1, n-epitaxial layer 2 and p-substrate 1. The p diffusion region 3, the n + buried diffusion region 4, the n diffusion region 5, the p diffusion region 6, the oxide film 7, the aluminum wiring 8, the polysilicon gate 9, the aluminum electrode 10, and the polysilicon 11 which are formed as described above are provided. There is. The aluminum electrode 10 is formed in contact with the n diffusion region 5 and the p diffusion region 6 and has the same potential as the potential of the RESURF isolation island. The polysilicon 11 has the same potential as the p diffusion region 3 and functions as a field plate. The n diffusion region 5 and the n + buried diffusion region 4 are surrounded by the p diffusion region 3 to form a RESURF structure.

In the semiconductor device configured as described above, n ch M
The OSFET is turned on, and a current flowing in the p diffusion region 6 causes a potential difference between the electrode 10 and the aluminum wiring 8. By outputting this potential difference, the logic signal applied to the gate 9 can be level-shifted to the high potential side.

A problem with the structure of such a conventional high breakdown voltage semiconductor device is that since the high-potential aluminum wiring 8 crosses over the p diffusion region 3 which is the substrate potential, the n-epitaxial layer 2 and the p diffusion region 3 are formed. That is, the extension of the depletion layer between and is inhibited, and the breakdown voltage is lowered. To solve this problem, as shown in FIG. 12, the field plate 11 is formed of polysilicon or the like on the above-mentioned pn junction to secure the extension of the depletion layer, and further the field plates are formed in a floating manner. The surface electric field is stabilized by capacitive coupling (see, for example, USP5455439), but the field plate 11 is increased as the breakdown voltage is increased.
In order to secure the insulation strength of the oxide film itself between the aluminum wiring 8 and the aluminum wiring 8, there is a problem that the oxide film thickness needs to be considerably increased and the process cost increases.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and does not cause an increase in process cost, and the required area is small, and high withstand voltage isolation is realized. A high withstand voltage semiconductor device is provided.

[0006]

A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type (preferably p-type),
A second conductivity type (preferably n-type) first region formed on the main surface of the semiconductor substrate and having a relatively low impurity concentration, and a main surface of the semiconductor substrate 1 in contact with the first region. The second conductivity type (preferably n
Second type and a second conductivity type (preferably n type) having a relatively high impurity concentration and formed at a predetermined interval between the second region of the second type) and the second region on the main surface of the semiconductor substrate. Of the third conductivity type and a second conductivity type (preferably, having a relatively low impurity concentration) formed at a predetermined interval between the third region and the first region in contact with the third region on the main surface of the semiconductor substrate. , N− type) fourth region, and a conductive path 8 formed between the second region and the third region with an insulating layer interposed between the fourth region and the main region of the semiconductor substrate. It is a feature.

A semiconductor device according to another invention of the present invention is a semiconductor substrate of a first conductivity type (preferably p-type),
A plurality of first conductivity type (preferably n-type) first regions formed on the main surface of the semiconductor substrate and having a relatively low impurity concentration, and a plurality of first regions on the main surface of the semiconductor substrate. Between a plurality of second conductive type (preferably n-type) second regions each having a relatively high impurity concentration and being in contact with each other, and the plurality of second regions on the main surface of the semiconductor substrate. Third regions of the second conductivity type (preferably n-type) that are formed at predetermined intervals and have a relatively high impurity concentration, and a plurality of regions that are in contact with the third regions on the main surface of the semiconductor substrate. Of the fourth region of the second conductivity type (preferably n-type) which is formed at a predetermined distance from the first region and has a relatively low impurity concentration, and the main surface of the semiconductor substrate. A plurality of conductive members formed between the plurality of second regions and a plurality of third regions respectively with an insulating layer in between. It is characterized in that a 8.

A semiconductor device according to another invention of the present invention is a semiconductor substrate of a first conductivity type (preferably p-type),
A plurality of first conductivity type (preferably n-type) first regions formed on the main surface of the semiconductor substrate and having a relatively low impurity concentration, and a plurality of the first regions on the main surface of the semiconductor substrate 1. Between a plurality of second regions of the second conductivity type (preferably n-type) formed in contact with the regions and having a relatively high impurity concentration, and between the plurality of second regions on the main surface of the semiconductor substrate. A third region of a second conductivity type (preferably n-type), which has a sandwiched portion and is formed at a predetermined interval from the plurality of second regions and has a relatively high impurity concentration. A main surface of the semiconductor substrate has a portion that is in contact with the third region and is sandwiched between the plurality of first regions, and is formed at a predetermined distance from the plurality of first regions. Between the fourth region of the second conductivity type (preferably n-type) having a relatively low impurity concentration and the main surface of the semiconductor substrate, there is no insulation. It is characterized in that a plurality of conductive paths that connect, respectively, respectively between said plurality of second regions formed through the layer and said third region.

A semiconductor device according to another invention of the present invention is the semiconductor device according to each of the above-mentioned inventions, wherein an outer periphery of a region including the second region and the third region includes the first region and the fourth region. It is characterized in that it is formed so as to be surrounded by a region.

A semiconductor device according to another invention of the present invention is a semiconductor substrate of a first conductivity type (preferably p-type),
An annular first region of the second conductivity type (preferably n-type) formed on the main surface of the semiconductor substrate and having a relatively low impurity concentration, and an inner side of the first region on the main surface of the semiconductor substrate. A predetermined distance between a second region of a second conductivity type (preferably n type) having a relatively high impurity concentration formed in contact with the second region and the inside of the second region on the main surface of the semiconductor substrate. An insulating layer is sandwiched between a second conductive type (preferably n type) annular third region having a relatively high impurity concentration and having a relatively high impurity concentration, and an insulating layer interposed between the third region and the main surface of the semiconductor substrate. It is characterized by comprising a conductive path formed between the second region and the third region.

A semiconductor device according to another invention of the present invention is the semiconductor device according to each of the above-mentioned inventions, which is formed between the second region and the third region and the semiconductor substrate.
It is characterized in that the depletion layer of the pn junction extends and contacts each other before the n junction reaches a critical electric field.

A semiconductor device according to another invention of the present invention is the semiconductor device according to each of the above-mentioned inventions, which is formed between the second region and the third region and the semiconductor substrate.
It is characterized in that it is formed such that the density of the lines of electric force at the peripheral corners of the n-junction is equal to or less than the density of the lines of electric force at the plane of the pn junction.

According to the semiconductor device of another invention of the present invention, in the above inventions, the width of the main surface of the semiconductor substrate between the second region and the third region is the diffusion depth of the second region. It is characterized in that it is formed to be 1.14 times or less of the height.

A semiconductor device according to another invention of the present invention is the semiconductor device according to each of the above inventions, wherein a punch-through voltage between the second region and the third region is formed in the third region. It is characterized in that it is formed to have a voltage higher than the power supply voltage.

A semiconductor device according to another invention of the present invention is the semiconductor device according to each of the above-mentioned inventions, wherein the second region and the third region are formed in the insulating layer between the main surface of the semiconductor substrate and the conductive path. It is characterized in that a field plate extending upward is provided.

Further, in the semiconductor device of another invention of the present invention, in each of the above-mentioned inventions, the withstand voltage by the insulating film between the field plate and the third region and the third region is in the third region. The thickness of the insulating film and the impurity concentration of the third region are adjusted so as to be higher than the power supply voltage of the control circuit to be formed.

The semiconductor device of another invention of the present invention is the semiconductor device according to each of the above-mentioned inventions, wherein the interfacial electric field of the insulating film between the field plate and the third region does not reach a critical electric field. The feature is that the impurity concentration of the region is adjusted.

In the semiconductor device of another invention of the present invention, in the above-mentioned inventions, the breakdown voltage by the insulating film layer and the third region is larger than the power supply voltage of the control circuit formed in the third region. The impurity concentration of the insulating layer and the third region is adjusted so that

Further, a semiconductor device according to another invention of the present invention is characterized in that, in each of the above-mentioned inventions, an impurity concentration of the third region is adjusted so that an interface electric field of the insulating layer does not reach a critical electric field. To do.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 is a plan view showing a semiconductor region of a semiconductor device having a level shift structure according to a first embodiment of the present invention. 2 is a cross section A in the plan view of FIG.
It is sectional drawing which shows the structure in -A.

First, as shown in the plan view of FIG. 1, the semiconductor device of the present invention has a RESURF structure in which n diffusion regions 12a, 12b are surrounded by n-diffusion regions 2a, 2b. However, it is divided into parts with slits. Further, as shown in the sectional view of FIG. 2, this semiconductor device has an nch RESURF MOSF in the left half of the figure.
It is composed of an ET region and a RESURF isolation island region in the right half of the figure, and includes a p-silicon substrate 1 (semiconductor substrate), an n-diffusion region 2a (first region), an n-diffusion region 5, a p-diffusion region 6 and an oxide film. 7 (insulating layer), aluminum wiring (conductive path) 8, polysilicon gate 9, aluminum electrode 10, n diffusion region 12a (second region), n diffusion region 12b (third region). The n-diffusion region 2b (fourth region) in FIG.
Although not shown in FIG. 3, it is formed around the n diffusion region 12b in the same shape as the n − diffusion region 2a. The aluminum electrode 10 is formed in contact with the n diffusion region 5 and the p diffusion region 6 and has the same potential as the potential of the RESURF isolation island.

In the semiconductor device having the above structure,
By biasing the gate electrode 9 +, nch MOSF
The ET is turned on, and a current flowing in the p diffusion region 6 causes a potential difference between the electrode 10 and the aluminum wiring 8. By using this potential difference as an output, the signal applied to the gate 9 can be level-shifted to the high potential side.

The structure of the present invention is different from the conventional structure in that there is no RESURF structure between the drain of the nch RESURF MOSFET (n-diffusion region 2a in FIG. 2) and the RESURF isolation island region 12b, and the p width is narrow. -The substrate region 1 is a slit-shaped region 1a which is exposed on the surface.

FIG. 3 shows equipotential lines when the n diffusion region 12b has a high potential in this structure. N as shown in FIG.
Since the p-substrate 1a sandwiched between the diffusion regions 12a and 12b is depleted, the surface potential of the p-substrate 1a does not significantly differ from that of the n diffusion regions 12a and 12b. Therefore, the potential difference between the aluminum wiring 8 and the surface of the underlying silicon substrate 1 is small, and electric field concentration, which is a problem in the conventional example, does not occur.

The signal at the time of level shift is output as a potential difference between the electrode 10 and the aluminum wiring 8.
It is the same as the potential difference between the n diffusion regions 12a and 12b (between the n diffusion region 12a as the drain of the nch MOSFET and the RESURF isolation island region 12b). Therefore, n diffusion region 12a
The punch-through voltage between and 12b must be greater than the output voltage. Generally speaking, the output voltage is detected by a low-breakdown-voltage control circuit or the like built in the RESURF isolation island region, so that the output voltage is designed to be equal to or lower than the power supply voltage of the control circuit.

From the above, the surface exposed region 1a of the p-substrate 1 is depleted to the extent that the RESURF breakdown voltage is not lowered, and the punch-through voltage between the n diffusion regions 12a and 12b becomes equal to or higher than the control circuit power supply voltage. It is necessary to have a proper concentration and distance.

This will be examined analytically. FIG. 4 is a diagram schematically showing the corner portions of the n diffusion regions 12a and 12b in a simplified manner for this analysis. As shown in FIG. 4, the pattern corner radius of the n diffusion region 12a is R,
The diffusion depth and the lateral diffusion length of the n diffusion regions 12a and 12b are r.

First, the necessary condition for not affecting the RESURF breakdown voltage is that the pn junction electric field does not reach the critical electric field when the depletion layers extending from the n diffusion regions 12a and 12b on both sides are in contact with each other at the center. This condition for the electric field of the pn junction at the corner is expressed in the form of Equation 1. However, the actual
It is assumed that the depletion layers extend from the n diffusion regions 12a and 12b on the side of the inside corner 12a and on the side of the outside 12b, but are substantially the same. Ecr> E1 = L ・ q ・ Np / (ε ・ ε ') × ((L ・ L / 3 + r ・ L + R ・ L / 2) / ((R + r) ・ r) +1)・ ・ ・ Equation 1 where Ecr: critical electric field (about 2.5E5 [V / cm]) E1: pn junction electric field when the depletion layer contacts at the center q: electron charge Np: p-near the surface of the substrate 1 Impurity concentration at ε: Dielectric constant in vacuum ε ': Dielectric constant of silicon.

In the case of R >> r, it is approximated by the following equation. Ecr> E1 = L * q * Np / ([epsilon] * [epsilon] ') * (L / (2 * r) +1) ... Equation 2 Therefore, the radius of the pattern corner (R ), The diffusion depth (r) of the n diffusion regions 12a and 12b and the impurity concentration (Np) near the surface of the p-substrate 1 are adjusted.

Next, in the case of the structure of FIG. 4, the breakdown voltage generally decreases with respect to the one-dimensional breakdown voltage between the p-substrate 1 and the n diffusion regions 12a and 12b. This is the n diffusion region 12a, 12
This is because the line of electric force per unit area of the pn junction corner part of the peripheral part of b is larger than the line of electric force of the plane part of the pn junction, and the electric field at the pn junction part rises. n diffusion region 12
Assuming that the pattern corner radius R of a is sufficiently larger than the diffusion depth and the lateral diffusion length r of the n diffusion region 12, the electric field at the corner of the pn junction is approximately (area of the pn junction viewed from the surface) / (pn junction). It is considered to be proportional to the actual area). Here, the actual area of the pn junction is the sum of the junction areas of the pn junction corners of the n diffusion regions 12a and 12b, and the area of the pn junction viewed from the surface is n.
The sum of the area where the pn junctions at the corners of the diffusion regions 12a and 12b are projected on the plane and the area between them (the width 2L) on the surface of the p-substrate 1a are meant.

Therefore, this value is set to 1 or less, that is, pn
The electric field at the junction corner may be designed to be equal to or less than the electric field at the plane portion of the pn junction. This condition is expressed by Equation 3 below. 1 ≧ ((r + L) ・ (r + L) + 2R ・ (r + L)) / (2 ・ r ・ (π ・ R / 2 + r)) ・ ・ ・ Equation 3 If R >> r, then 1 ≧ 2 · (r + L) / (π · r) ・ ・ ・ Equation 4 Therefore 2L ≦ (π−2) · r ・ ・ ・ Equation 5 and the surface of the p-substrate 1 Width on top (slit p-substrate
It can be seen that the width of 1a (2L) should be less than or equal to (π-2) of the diffusion depth (r) of the n diffusion regions 12a and 12b.

FIG. 5 shows the result of confirming this effect by two-dimensional simulation with R >> r. As can be seen from this figure, when the width 2L on the surface of the p-substrate 1 becomes larger than about (π-2) of the diffusion depth (r) of the n diffusion region 12, the breakdown voltage of the pn junction corner portion becomes one-dimensional. It will be less than 80% of the breakdown voltage. It is also understood that when L is sufficiently large (2L = ∞), the breakdown voltage drops to 43% of the one-dimensional breakdown voltage.

Next, the punch-through voltage V between the n diffusion regions 12a and 12b when the depletion layer extends by 2 L is the power supply voltage Vc of the control circuit in the RESURF isolation island region from the above discussion.
Needs to be larger. When this is approximated by a one-dimensional staircase connection, it is expressed by the following equation. Vc <V = 2L·L · q · Np / (ε · ε ′) (1 + Np / Nn) ··· Equation 6 where q: electron charge Nn: n near the pn junction of the diffusion regions 12a and 12b Impurity concentration Np: p-impurity concentration near the surface of the substrate 1 ε: vacuum permittivity ε ′: relative permittivity of silicon.

Therefore, in order to satisfy the expression 6, the width of the p-substrate 1a portion (2L), the impurity concentration (Np) near the surface of the p-substrate 1a, and the pn junction of the n diffusion regions 12a and 12b are close to each other. Adjust the impurity concentration (Nn) of.

FIG. 5 also shows the results of punch-through voltage simulation. p-width on the surface of substrate 1 (2L
Is (π−) of the diffusion depth (r) of the n diffusion regions 12a and 12b.
At 2) times, the punch-through voltage has risen to 50V, which is sufficiently larger than the general control circuit power supply voltage. Therefore, from this value as well, the width 2L of the p-substrate 1a in the gap is less than (π-2) times the n diffusion depth (r), that is,
It can be seen that the design should be 1.14 times or less the n diffusion depth.

According to the structure of the semiconductor device of this embodiment as described above, the level shift can be realized by forming the n-diffusion region 2a as the level shift element in only one of the RESURF isolation island regions 12b. Therefore, the device area can be significantly reduced. Further, since it is not necessary to change the process, there is no increase in process cost.

Embodiment 2 FIG. 6 is a plan view showing an arrangement state of semiconductor regions of a semiconductor device according to the second embodiment of the present invention. The structure of the cross section AA in FIG. 6 is the same as that in FIG. In the semiconductor device according to the second embodiment, as shown in the plan view of FIG. 6, two n-diffusion regions 2a (first regions) are separated from each other on the p-silicon substrate 1 (semiconductor substrate) at predetermined intervals. Two n diffusion regions (second regions) 12a are formed in contact with each other and are opposed to each other at a predetermined interval. In addition, these two n diffusion regions (second region) 1
N diffusion region (third region) 12 at a predetermined interval from 2a
b is formed. Then, an n-diffusion region (fourth region) 2b is formed on the periphery of the n-diffusion region 12b, and the n-diffusion region 2a (first region) is opposed to the n-diffusion region 2a (first region) at a predetermined interval. In the figure, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding portions.

The structure of the second embodiment is one in which a plurality of small areas adjacent to each other at the same position are divided from the n RESURF separating island and are spaced from each other. And these two n
Diffusion region (second region) 12a and n diffusion region (third region)
The region including 12b has an n-diffusion region 2a on the outer periphery thereof.
It is surrounded by a region including the (first region) and the n− diffusion region (fourth region) 2b.

As described above, in the second embodiment, nch
It has two RESURF MOSFETs, generally more than one. In this way, a plurality of level shift elements can be connected to one RESURF isolation island region. Except for this point, the operation and function of the high voltage isolation of this semiconductor device are the same as those of the first embodiment shown in FIGS. 1 and 2, and detailed description thereof will be omitted. Further, even in such a configuration, since it is sufficient to provide the RESURF MOSFET only on one side of the RESURF isolation island region, it is possible to suppress an increase in the element area.

Embodiment 3 FIG. 7 is a plan view showing the arrangement of the semiconductor regions of the semiconductor device according to the third embodiment of the present invention. The structure of the cross section AA shown in FIG. 7 is the same as that of FIG. As shown in the plan view of FIG. 7, the semiconductor device of the third embodiment has p
-N-diffusion region 2a on the silicon substrate 1 (semiconductor substrate)
Two (first regions) are formed separately, and two n diffusion regions (second regions) 12a are formed in contact with each other. An n diffusion region (third region) 12b is formed at a predetermined interval from the two n diffusion regions (second region) 12a, and extends between the two n diffusion regions (second region) 12a. . Then, an n-diffusion region (fourth region) 2b is formed around the n-diffusion region 12b, and the n-diffusion region 2a is formed.
It faces the (first region) at a predetermined interval. Furthermore, the n− diffusion region (fourth region) 2b is an n diffusion region (third region) 1 between two n diffusion regions (second region) 12a.
2b, and between the two n-diffusion regions 2a (first region), these two n-diffusion regions 2a (first region).
And are arranged at a predetermined interval.

The semiconductor device of the third embodiment is the same as the nch RESURF in the device shown in the first embodiment of FIGS.
It can be considered that a plurality of MOSFETs are formed at different positions on one RESURF isolation island.

As described above, the third embodiment incorporates a plurality of n ch RESURF MOSFETs. The difference from the third embodiment is that an n-diffusion region 2a formed in contact with the n diffusion region 12a of the RESURF isolation island is formed between the two n ch RESURF MOSFETs. By doing so, a plurality of level shift elements can be connected to one RESURF isolation island region. Also, the RESURF MOSFET can be provided only on one side of the RESURF isolation island region,
An increase in element area can be suppressed. Furthermore, two n
It is possible to prevent the parasitic operation due to the parasitic element L-npn (lateral transistor structure) between ch RESURF MOSFETs.

In the example of FIG. 7, nch RESURF MOSF
Two sets of level shift functions by ET are provided, but a plurality of sets can be provided as needed.

Fourth Embodiment FIG. 8 is a plan view showing an arrangement of semiconductor regions of a semiconductor device having a level shift structure according to a fourth embodiment of the present invention. The structure of the cross section AA in FIG. 9 of the semiconductor device of the fourth embodiment is similar to that of FIG.

In the semiconductor device according to the fourth embodiment, as shown in the plan view of FIG. 9, an n-diffusion region 2a (first region) is annularly formed on a p-silicon substrate 1 (semiconductor substrate), In contact with this inner side, n diffusion region (second region) 12a
Is formed in a ring shape. Further, inside this, an island-shaped n diffusion region 12b is provided with a p- substrate 1a having a predetermined width interposed therebetween.

Thus, unlike the first embodiment, the device of the fourth embodiment has a structure in which the separation between the n diffusion regions 12a and 12b is formed in an annular shape, and the portion of the n diffusion region 2a is not divided. It is that. Apart from this,
Since the operation and function of the device of the fourth embodiment are the same as those shown in FIG. 1, detailed description thereof will be omitted. In the structure of the first embodiment shown in FIGS. 1 and 2, the n-diffusion region 2 is used.
May be reduced due to the separation of
In this structure, there is no fear that the breakdown voltage will decrease due to the division of the n − diffusion region 2.

Embodiment 5 9 is a diagram showing a sectional structure of a semiconductor device having a level shift structure according to a fifth embodiment of the present invention. The planar structure of the semiconductor region of the semiconductor device of the fifth embodiment is similar to that of FIG. FIG. 9 shows a sectional view at the same position as the section AA in FIG. Embodiment 5
9, the p-silicon substrate 1 (semiconductor substrate), the n-diffusion region 2a (first region), the n-diffusion region 5, the p-diffusion region 6, the oxide film 7 ( Insulating layer), aluminum wiring 8 (conductive path), polysilicon gate 9, aluminum electrode 10 formed in contact with n diffusion region 5 and p diffusion region 6 and having the same potential as the island potential, n diffusion region 12
a (second region) and n diffusion region 12a (third region) are provided. Although the n-diffusion region 2b (fourth region) of FIG. 1 does not appear in FIG. 9, it has the same shape as the n-diffusion region 2a.
It is formed around the n diffusion region 12b. Since these are the same as those in FIG. 1, description thereof will be omitted.

Further, in the fifth embodiment, in addition to the structure of the first embodiment, polysilicon 13 having the same potential as that of the n diffusion region 12a on the nch RESURF MOSFET side is arranged in the oxide film 7 and below it. Oxide film portion (this is the oxide film 7a
It is formed so as to cover the exposed portion 1a on the surface of the p-substrate 1 with (an insulating film) interposed therebetween.
And this polysilicon 13 has n diffusion regions 12a, 1
Covering the pn junction formed between 2b and the p-substrate 1;
Further, it extends over the portions of the n diffusion regions 12a and 12b. When formed in this way, during the level shift operation,
Between the n diffusion regions 12a and 12b, that is, the n diffusion region 12a of the nch MOS drain and the n diffusion region 12 of the RESURF isolation island.
Punch-through with b can be prevented by the field plate effect of the polysilicon layer 13. However, in the n diffusion region 12b on the RESURF isolation island region side, if the thickness of the oxide film 7a under the polysilicon 13 is too thin, electric field concentration may occur on the Si surface under the polysilicon 13 and conversely the withstand voltage may decrease. is there.

Therefore, it is necessary to satisfy the following conditions. First, FIG. 10 is an enlarged view showing a structure in which the polysilicon 13 and the n diffusion region 12b on the RESURF isolation island region side face each other with the oxide film 7a in between. At the same time, the electric field distribution is also shown. The thickness of the oxide film 7a under the polysilicon 13 is t, and the thickness of the depletion layer extending into the n diffusion region 12b is d. The breakdown voltage of the silicon oxide film 7a and the n diffusion region 12b must be higher than the power supply voltage Vc of the control circuit. From this, the following equation 7 is obtained. Vc <q ・ Nn ・ d / (ε ・ ε ') ・ (ε' ・ t / εox + d / 2) ・ ・ ・ Equation 7

Since the electric field at the interface of the silicon oxide film 7a must be below the critical voltage Ecr ',
The following expression 8 is obtained. Ecr ′> q ・ Nn ・ d / (ε ・ ε ') ·············································· In these equations, Ecr': critical electric field (about 5E5 [V / C
m]) q: charge amount of electrons Nn: impurity concentration of n diffusion region 12b ε: dielectric constant of vacuum ε ′: relative dielectric constant of silicon εox: relative dielectric constant of oxide film d: depletion immediately below the end of polysilicon 13 Layer width t: oxide film thickness just below the end of the polysilicon 13.

In most cases, the field plate 13 is actually formed to extend up to the large impurity concentration (Nn) of the n region 12, so the depletion layer d can be considered to be considerably small. Therefore, it is generally desirable that the value of the first term on the right side of the equation 7 be larger than the control voltage Vc. That is, Vc <q ・ Nn ・ d / (ε ・ ε ') ・ (ε ′ ・ t / εox) Therefore, Vc <q ・ Nn ・ d ・ t / ε ・ εox Equation 9 The oxide film thickness (t) immediately below the end of the polysilicon 13 and the impurity concentration (Nn) of the n diffusion region 12b are adjusted so as to satisfy these equations 7-9.

Further, FIG. 11 shows the state of the lines of electric force (FIG. 11A) when the polysilicon 13 is formed so as to cover the p-substrate 1a as shown in FIG.
It is the figure compared with the case where there is no (FIG.11 (b)). As shown in FIG. 11, the presence of the polysilicon 13 on the surface region of the p-substrate 1a causes some lines of electric force to terminate in the polysilicon 13, and the electric field at the corner of the pn junction is relaxed. . This allows p-substrate 1
The breakdown voltage between the n-type diffusion region 12 and the n-diffusion region 12 is less likely to decrease.

FIG. 5 also shows the breakdown voltage simulation results when the field plate 13 is present. It is 85% for one dimension and 6% for no field plate.
Withstand voltage improvement is obtained. According to this structure, in addition to the effect of the first embodiment, the breakdown voltage and punch through voltage can be further increased.

The apparatus shown in FIG. 9 corresponds to the apparatus shown in FIG.
Although the field plates 13 are provided in the devices of 2 and 2, the field plate can be similarly applied to the devices of FIGS. 6 to 8 of the second to fourth embodiments.

In addition, the breakdown voltage of the polysilicon 13 provided in the oxide film 7 and the oxide film 7a and the n diffusion region 12b below the polysilicon 13 have been considered above. This same consideration can be applied to the breakdown voltage of the aluminum wiring 8, the oxide film 7 thereunder, and the n diffusion region 12b in the devices of FIGS. 1 to 8 in the first to fourth embodiments. That is, also in these cases, the oxide film thickness (t) immediately below the end of the aluminum wiring 8 and the n diffusion region 12 are satisfied so that the conditions of the expressions 7 to 9 are satisfied.
The impurity concentration (Nn) of b is adjusted.

As described above, according to the present invention, a semiconductor device having a high breakdown voltage isolation region between a low breakdown voltage region and a high breakdown voltage region and having a level shift function to the high breakdown voltage region is provided. , Which has a small area and does not increase the process cost.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor region of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a partial cross-sectional structural view for explaining the operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a partial cross-sectional perspective view for explaining the operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing simulation results for explaining the operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor region of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor region of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor region of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional structural view of a part of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is an enlarged partial cross-sectional view for explaining the operation of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 11 is an electric force diagram for explaining the operation of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 12 is a sectional view showing a structural example of a conventional semiconductor device.

[Explanation of symbols]

1 semiconductor substrate (p-substrate), 2a first region (n-diffusion region), 2b fourth region (n-diffusion region), 7 insulating layer (oxide film), 7a insulating film (oxide film), 8 conductive paths (Aluminum wiring), 12a second region (n diffusion region), 12b
Third region (n diffusion region), 13 field plate (polysilicon)

Claims (14)

[Claims] 1. A semiconductor substrate of a first conductivity type, a second region of a second conductivity type formed on a main surface of the semiconductor substrate and having a relatively low impurity concentration, a main region of the semiconductor substrate on the first region. A second region of the second conductivity type formed in contact with each other and having a relatively high impurity concentration, and formed on the main surface of the semiconductor substrate at a predetermined interval between the second region and a relatively high impurity concentration. A second region of the second conductivity type, which is formed on the main surface of the semiconductor substrate in contact with the third region and at a predetermined distance from the first region and has a relatively low impurity concentration. A semiconductor device comprising a fourth region and a conductive path formed between the fourth region and the main surface of the semiconductor substrate with an insulating layer interposed between the second region and the third region. 2. A semiconductor substrate of a first conductivity type, a plurality of first regions of a second conductivity type formed on the main surface of the semiconductor substrate and having a relatively low impurity concentration, and a plurality of the plurality of regions on the main surface of the semiconductor substrate. A plurality of second regions of the second conductivity type formed in contact with the first regions and having a relatively high impurity concentration, and a plurality of second regions on the main surface of the semiconductor substrate are provided with predetermined intervals. A third region of the second conductivity type having a relatively high impurity concentration, formed on the main surface of the semiconductor substrate in contact with the third region and at a predetermined distance from the plurality of first regions. A fourth region of the second conductivity type having a relatively low impurity concentration and an insulating layer between the fourth region and the main surface of the semiconductor substrate, and between the plurality of second regions and the third region. A semiconductor device characterized by comprising a plurality of conductive paths. 3. A semiconductor substrate of a first conductivity type, a plurality of first regions of a second conductivity type formed on a main surface of the semiconductor substrate and having a relatively low impurity concentration, and a plurality of the plurality of regions on the main surface of the semiconductor substrate. A plurality of second regions of the second conductivity type which are formed in contact with the first regions and have a relatively high impurity concentration; and a portion sandwiched between the plurality of second regions on the main surface of the semiconductor substrate. And a third region of the second conductivity type, which is formed at a predetermined distance from the plurality of second regions and has a relatively high impurity concentration, and which is in contact with the third region on the main surface of the semiconductor substrate. A second region of the second conductivity type, which has a portion sandwiched between the first region and is formed at a predetermined interval between the plurality of first regions and has a relatively low impurity concentration, And a plurality of second regions formed via an insulating layer between the main surface of the semiconductor substrate and the A semiconductor device comprising a plurality of conductive paths which respectively extend from the third region to the third region. 4. The area including the second area and the third area is formed so as to be surrounded by the area including the first area and the fourth area. 4. The semiconductor device according to any one of 3 above. 5. A semiconductor substrate 1 of a first conductivity type, an annular first region of a second conductivity type formed on a main surface of the semiconductor substrate and having a relatively low impurity concentration, and a first region on the main surface of the semiconductor substrate. A second region of the second conductivity type annular shape having a relatively high impurity concentration formed in contact with the inside of one region, and formed on the main surface of the semiconductor substrate with a predetermined space between the second region and the inside of the second region. Is formed between the second region and the third region by sandwiching an insulating layer between the third region of the second conductivity type having a relatively high impurity concentration and the main surface of the semiconductor substrate. A semiconductor device comprising a conductive path. 6. A depletion layer of the pn junction extends and contacts each other before the pn junction formed between the second region and the third region and the semiconductor substrate reaches a critical electric field. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 7. The density of the lines of electric force at the peripheral corners of a pn junction formed between the second region and the third region and the semiconductor substrate is equal to that of the lines of electric force at the plane of the pn junction. 7. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to have a density or less. 8. The width of the main surface of the semiconductor substrate between the second region and the third region is 1.1 of the diffusion depth of the second region.
8. The semiconductor device according to claim 1, wherein the semiconductor device is formed to have a size of 4 times or less. 9. The punch-through voltage between the second region and the third region is set to be higher than the power supply voltage of the control circuit formed in the third region. 9. The semiconductor device according to any one of items 8 to 8. 10. The field plate extending to above the second region and the third region is provided in the insulating layer between the main surface of the semiconductor substrate and the conductive path. The semiconductor device according to any one of 1 to 9. 11. The insulating film between the field plate and the third region and the third region so that the withstand voltage of the third region is higher than the power supply voltage of the control circuit formed in the third region. The semiconductor device according to claim 10, wherein the thickness and the impurity concentration of the third region are adjusted. 12. The impurity concentration of the third region is adjusted so that an interfacial electric field of an insulating film between the field plate and the third region does not reach a critical electric field. Semiconductor device. 13. The impurity concentration of the insulating layer and the third region is adjusted so that the breakdown voltage of the insulating film layer and the third region is higher than the power supply voltage of a control circuit formed in the third region. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 14. The semiconductor device according to claim 1, wherein an impurity concentration of the third region is adjusted so that an interfacial electric field of the insulating layer does not reach a critical electric field.