JPH09283732A - Image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high sensitivity MOS type image sensor whose photo transistor amplification factor is increased by lowering the applied voltage to the photo transistor by separating the applied voltage from the driving voltage of a logical circuit part and thinning the base layer of the photo transistor. SOLUTION: This image sensor is provided by forming a sensor part, which is composed of a photo transistor 2 arranged in array or matrix and a switching element, and a logical circuit part (PMOS3, NMOS4), which processes the signal received by a discretionary photo transistor of the sensor part, on a semiconductor substrate 1. The photo transistor 2 is formed in a first well 5, which is provided on the semiconductor substrate 1, and a voltage lower than a voltage that operates the logical circuit part can be applied to the photo transistor 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inexpensive MOS type image sensor of image sensors for recognizing an image. More specifically, it has improved sensitivity and can be used as a reduction type image sensor.
MOS that can be used for ICs, infrared sensor ICs, etc.
Type image sensor.

[0002]

2. Description of the Related Art Conventionally, as an image sensor for recognizing an image, a signal transferred by a charge transfer unit is transferred to a signal processing unit by a signal received by each of light receiving sensors such as photodiodes arranged in a matrix. CCD sensors for image processing, light receiving sensors and switching elements such as MOS transistors are provided in a matrix.
For example, a MOS type sensor in which data of each pixel selected by a logic circuit unit such as a shift register is sequentially read through a switching element is considered.

The MOS type sensor is low in cost and is often used in the contact type image sensor.
The sensitivity is lower than that of the CD type sensor, and the reduction type image sensor including fine pixels has drawbacks such as a low reading speed and is not used.

In the MOS type sensor, a light receiving sensor such as a phototransistor is made of a bipolar semiconductor, and a switching element and an element for a logic circuit of a signal processing section are MOSICs formed on the same semiconductor substrate. Therefore, the bipolar phototransistor is also manufactured by the MOSIC manufacturing process, and the semiconductor substrate is used as the collector region, and the diffusion regions of the base and the emitter are sequentially formed in the semiconductor substrate. Therefore, as the voltage for operating the phototransistor, the voltage applied to the semiconductor substrate for operating the MOSFET is applied as it is.

In order to operate the MOSFET, it is necessary to apply a voltage of about 5V, and in some cases about 3 to 8V, and the phototransistor must be able to withstand the voltage higher than that. It is known that the collector-emitter breakdown voltage of a transistor generally increases as the thickness of the base layer (thickness between the emitter region and the collector region) increases. Therefore, the base region of the phototransistor is a MOSF so that the breakdown voltage of the phototransistor can withstand the voltage applied to the MOSFET.
It is formed thickly by a diffusion process different from the source / drain regions etc. forming ET.

On the other hand, however, it is generally known that the amplification factor of a transistor increases as the thickness of the base layer (the thickness of the portion sandwiched between the emitter region and the collector region) decreases. For this reason, the conventional MOS image sensor has a drawback in that even if a phototransistor is used in the sensor portion, a sufficient amplification factor cannot be obtained due to the withstand voltage and the sensitivity is low.

[0007]

As described above, the conventional M
In the OS type sensor, even if a phototransistor is used in the sensor portion, the amplification factor of the phototransistor is low and sufficient sensitivity cannot be secured. As a result, there is a problem that it cannot be used in a reduction type image sensor.

The present invention has been made in order to solve such a problem, and the applied voltage to the phototransistor is separated from the drive voltage of the logic circuit section to be low and the base layer of the phototransistor is made thin. An object of the present invention is to provide a highly sensitive MOS image sensor in which the amplification factor of the phototransistor is increased.

[0009]

SUMMARY OF THE INVENTION An image sensor according to the present invention comprises a sensor section comprising phototransistors and switching elements arranged in an array or a matrix, and a logic for processing a signal received by the phototransistor of the sensor section. A circuit unit is an image sensor formed on a semiconductor substrate, wherein the phototransistor is formed in a well provided on the semiconductor substrate, and a voltage lower than a voltage for operating the logic circuit unit is applied to the phototransistor. Is configured to be possible.

The collector region of the phototransistor and the semiconductor substrate on which the logic circuit portion is formed are formed of the same conductivity type, and the wells on which the phototransistor is formed are formed of different conductivity types. It is preferable that the phototransistor and the collector region of the phototransistor are electrically isolated from each other through pn junctions formed between the phototransistor and the phototransistor. By doing so, MO
This is because the logic circuit section of the SFET and the bipolar phototransistor can be easily electrically independent, and the amplification factor of the phototransistor can be increased by lowering the voltage applied to the phototransistor.

A voltage dividing circuit by a resistor is formed in the semiconductor substrate or on the surface thereof via an insulating film, and the voltage dividing circuit obtains a voltage obtained by stepping down the voltage applied to the logic circuit section. It is preferable because a low voltage that can be applied to the phototransistor can be easily formed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a MOS type image sensor of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an example of a semiconductor structure of a part of a phototransistor and a MOSFET portion for a logic circuit portion of the image sensor of the present invention, and FIG. 2 is a block diagram of a main portion of the image sensor of the present invention. is there.

In FIG. 1, reference numeral 1 is an n-type semiconductor substrate, 2 is a phototransistor portion composed of bipolar transistors, and 3 and 4 are PMOSFETs (hereinafter,
PMOS and NMOSFET (hereinafter NMO)
The logic circuit section is composed of S). The phototransistor 2 part is the first p-well 5 formed on the semiconductor substrate 1.
It comprises an n ⁺ type collector region 21, a p ⁺ type base region 22, and an n ⁺ type emitter region 23 provided therein, and electrodes 24 and 25 are provided in the collector region 21 and the emitter region 23, respectively. Has been. The first p-well 5 is provided with an electrode 5b via a high-concentration region 5a provided on a part of its surface and is connected to the ground. By connecting the first p-well 5 to the ground, a diode having a pn junction is formed between the first p-well 5 and the semiconductor substrate 1, and the first p-well 5 and the collector region 21 are formed. Since a diode having a pn junction is also formed between and, and the anode side thereof is grounded, the semiconductor substrate 1 and the collector region 21 are diode-separated. As a result, the semiconductor substrate 1 and the phototransistor 2 are electrically separated. When the semiconductor substrate 1 is p-type, the first well is n-type and is not connected to the ground but held at a constant potential. As a result, the pn junctions formed between the n-type well and the p-type collector region and the semiconductor substrate respectively perform diode isolation, and the collector region and the semiconductor substrate are electrically isolated.

The PMOS 3 is a gate electrode provided via the source / drain regions 31 and 32 formed of p ⁺ type regions directly formed on the front surface side of the semiconductor substrate 1 and the oxide film 1a on the surface of the semiconductor substrate 1 between them. 33, and the NMOS 4 is the second p provided on the semiconductor substrate 1.
N ⁺ type source / drain regions 41 and 42 are formed in the well 6.
And the gate electrode 43 provided via the oxide film 1a on the surface of the semiconductor substrate 1 between them. This P
As shown in FIG. 2, the MOS 3 and the NMOS 4 form a logic circuit unit such as the shift register 8 and the chip selector 11.

The semiconductor structure of the MOS type image sensor of the present invention has a structure as shown in FIG. 1, and is characterized in that the phototransistor 2 portion is provided in the first p-well 5. As a result, the applied voltage to the phototransistor 2 can be reduced, and the thickness of the base layer of the phototransistor 2 portion (emitter region 23 and collector region 2) can be reduced.
The thickness h of the area sandwiched between 1 and w _b is reduced, and the amplification factor h
_fe can be increased. That is, the collector 21 of the phototransistor 2 has a low voltage V divided by the electrode 24 from the power supply voltage Vdd for operating the logic circuit section.
lo is connected. Therefore, the MOSFET of the logic circuit section
The voltage that drives 3, 4 is the sensor itself (the MOS used
The voltage Vlo lower than the rated voltage Vdd of the sensor is applied to the collector electrode 25 in the phototransistor 2 part in which the thickness w _b of the base layer is thinned while being the rated voltage Vdd of the FET), and is high without causing breakdown voltage breakdown. The amplification factor h _fe can be obtained. As a result, the MOS image sensor has a built-in phototransistor with a large amplification factor h _fe while using the rated voltage of the sensor as the power supply voltage.

With the structure shown in FIG. 1, the number of diffusion steps for forming the collector region 21 in the first p-well 5 is increased by one, but the p-layer of the base region 22 is a PMOS.
3 is formed at the same time as the source / drain regions 31 and 32, and the emitter region 23 is formed at the same time as the source / drain regions 41 and 42 of the NMOS 4. Therefore, in steps other than the diffusion step for forming the collector region 21, the MOSFETs 3 and 4 in the logic circuit section and the bipolar phototransistor 2 section can be simultaneously formed only by changing the patterning of the mask at the time of diffusion. This is because the diffusion of the base region has been the same as before in the MOSFETs 3 and 4
Since it could not be formed at the same time as the source / drain regions, the number of steps is the same as the conventional one, and the thickness of the base layer of the phototransistor 2 part can be reduced.

The low voltage Vlo applied to the collector 21 of the phototransistor 2 is, for example, as shown in FIG. 2, a voltage obtained by dropping the power supply voltage Vdd by the voltage dividing circuit 9 composed of resistors R ₁ and R _2. Is, for example, MOS
A type voltage follower amplifier 10 is used to convert the impedance from a high impedance to a low impedance to easily obtain a current. This resistance R
₁ and R ₂ are, for example, a polysilicon film formed on an oxide film on the surface of the semiconductor substrate 1 or the semiconductor substrate 1
The resistance of the semiconductor layer is used.

In FIG. 2, 7 is each phototransistor 2
A switching element that selectively extracts the received signal of
(Not shown in FIG. 2) is a MOSFET, the drain of which is connected to the emitter of the phototransistor 2 and the gate of which is connected to the shift register 8. The shift register 8 is composed of flip-flop circuits connected to each other. The shift register 8 selects a pixel corresponding to the data by the input clock signal CLK and data signal DSI, turns on the switching element 7 of the pixel, and turns on the switching element 7 of the pixel. The charge accumulated in the phototransistor 2 corresponding to the received signal is output through the analog switch 12 (SO). In this way, the received signal of each pixel is sequentially read out and signal-processed according to the signal from the logic circuit section. Reference numeral 11 denotes a chip selector, DS, which turns on the analog switch 12 if the chip has data and turns off the analog switch 12 if there is no data.
O is the output of the data signal. Cascade connection is performed using the normal output DSO.

In the above example, the p-type first well 5 is formed in the n-type semiconductor substrate 1 and the phototransistor 2 is formed in the p-type well 5. However, as described above, the p-type semiconductor is formed. An n-well may be formed on the substrate and a phototransistor may be formed in the n-well.

Further, although the linear image sensor is used in the above example, a sensor IC for CD, an infrared sensor IC,
The MOS image sensor of the present invention can be used for other various sensors.

[0022]

According to the present invention, since the phototransistor section is formed in the well, the phototransistor can be electrically isolated from the semiconductor substrate, and the phototransistor section is restricted by the withstand voltage against the drive voltage of the logic circuit section. Therefore, the depth of the base region can be controlled to be thin. Therefore, the amplification factor of the phototransistor can be increased, and the sensitivity of the MOS image sensor can be improved.

As a result, the MOS type image sensor can be used as the reduction type image sensor.
It greatly contributes to the cost reduction of electronic devices using image sensors.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory view of a chip of an image sensor of the present invention.

FIG. 2 is a block diagram of a main part of the image sensor of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 phototransistor 5 first p-well 7 switching element 8 shift register 9 voltage divider circuit

Claims (3)

[Claims] 1. An image in which a sensor portion including phototransistors and switching elements arranged in an array or a matrix and a logic circuit portion for sequentially reading signals received by the phototransistors of the sensor portion are formed on a semiconductor substrate. An image sensor, wherein the phototransistor is formed in a well provided in the semiconductor substrate, and a voltage lower than a voltage for operating the logic circuit unit can be applied to the phototransistor. 2. A collector region of the phototransistor and a semiconductor substrate on which the logic circuit section is formed are formed of the same conductivity type, and a well in which the phototransistor is formed is formed of different conductivity types. The image sensor according to claim 1, wherein the semiconductor substrate and the collector region of the phototransistor are electrically isolated by pn junctions formed between the well and the well. 3. A voltage dividing circuit by a resistor is formed in the semiconductor substrate or on the surface thereof via an insulating film, and a voltage obtained by reducing the voltage applied to the logic circuit section by the voltage dividing circuit is the photo voltage. The image sensor according to claim 1, which can be applied to a transistor.