JPH09284231A - Optical signal demodulator - Google Patents

Abstract

(57) Abstract: To realize an optical signal demodulating device that can accurately demodulate the pulse width of a transmitted code signal and is unlikely to cause malfunction. A photodiode 1 receives an optical code signal modulated with a pulse having a predetermined frequency. The received signal is discriminated by the bandpass filter 4 for only predetermined frequency components, and then converted into a pulse-shaped signal v _o6 by the integrating circuit 5 and the comparator 6. The output change detection circuit 7 detects the rising _edge of the pulse signal v _{o6 and sends it} to the clock generation unit 8. On the basis of this, the clock generation unit 8 uses the clock signal v _o synchronized with the pulse signal v _{o6.
produces o8} . Digital counting circuit 9, the clock signal v _o8 operates as a clock signal, counting the number of pulse signals v _o6 synchronized to the signal v _o8. Digital counting circuit 9
Is the pulse signal v when the number of pulses exceeds a predetermined number.
_Demodulate the code signal based on _o6 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical signal demodulating device which is provided for an optical communication device such as an optical remote controller and receives and demodulates an optical code signal modulated by a pulse of a specific frequency. .

[0002]

2. Description of the Related Art For example, an optical communication device using light such as infrared rays as a medium is easier to limit the communication range compared to a communication system using radio waves, and it is difficult to cause interference. More widely used. in recent years,
It is also used as a communication device for computers and other devices, and further development is expected.

In the above-mentioned conventional optical communication apparatus, for example, an optical signal transmitting apparatus (not shown) transmits a code signal as shown in FIG. 13 (a) to a specific frequency as shown in FIG. 13 (b). It is modulated by a pulse and transmitted as a pulse modulation code signal. In the optical signal demodulating device shown in FIG. 12, the photodiode 101 converts the pulse modulation code signal into a photocurrent signal. In addition, the preamplifier unit 10
2 performs current-voltage conversion of the optical signal ( _vo102 shown in (c) of FIG. 13), and then the AC amplifier unit 103 _{causes the} v
_Amplify the AC component of _o102 (v shown in (d) of FIG. 13)
_o103 ).

Further, the bandpass filter 104 discriminates the frequency component designated by the current supplied from the constant current circuit 110 from the output signal v _o103 of the AC amplifier 103, and the integrating circuit 105 the bandpass filter 104.
Output signal v _o104 is integrated (see (e) in FIG. 13).
The comparator 106, the output signal v _{O 105} compares the output signal v _{o1 04} is larger period of the output signal v _{O 104} and the integrating circuit 105 of bandpass filter 104, the output signal v _{O 106}
To a high level and the output signal v _{o1 06} to a low level for a small period (see (f) in FIG. 13).

Further, after the comparator 106,
A demodulation integration circuit 107 including a resistor 107b and a capacitor 107c connected in series is provided via a diode 107a connected in the forward direction. Also,
At the connection point of the resistor 107b and the capacitor 107c,
A discharging constant current source 107d that absorbs a predetermined current is connected.

[0006] Thus, the capacitor 107c is between the output voltage v _{o1 06} of the comparator 106 is high, the resistor 107 b, is charged with a time constant C · R,
Constant current source 1 for discharge while the output voltage v _o106 is low level
_07d discharges with a time constant C × Δv _o107 / I. In the equation of each time constant, C is the capacitor 1
07c, R is the resistance value of the resistor 107b, Δv _{o107
Indicate} the voltage changes of the voltage v _o107 across the capacitor 107c due to discharge. As a result, the voltage v _o107 across the capacitor 107c rises during the period when the output voltage v _o106 of the comparator 106 is at the high level and falls during the period when it is at the low level, as shown in (g) of FIG.

Further, the demodulation comparator 108 compares the reference voltage v _c1 generated by dividing the power supply voltage V _cc by the resistors 108a and 108b with the voltage v _o107 across the capacitor 107c and compares the voltage v _o107 across the voltage _. , The high level signal is output. As a result, the optical signal demodulating device demodulates the code signal having the pulse width T _out in response to the code signal having the pulse width T _in shown in (a) of FIG. 13, as shown in (h) of FIG. .

[0008]

However, in the above-described conventional optical signal demodulating device, the demodulating integration circuit 107 shown in FIG. 12 does not faithfully respond to the output signal v _{o106 of the} comparator 106. Therefore, the demodulation comparator 1
In the output of 08, that is, in the demodulated signal of the optical signal demodulation device, the pulse width T _out does not match the desired pulse width T _in , which causes a problem that pulse width distortion occurs.

Further, for example, in a remote controller using infrared rays, a fluorescent lamp lit at a commercial power source frequency can be cited as a main noise source, but a resistor 107b and a capacitor forming the demodulation integrating circuit 107 are used. 107
If the value of c is small and varies, the optical signal demodulator cannot distinguish between the optical code signal and the optical noise, and there is a risk of malfunction. In particular, when the resistor 107b and the capacitor 107c are formed in an integrated circuit, since the respective values have large variations, malfunction easily occurs, and solving the problem is an important issue.

The present invention has been made in view of the above problems, and an object thereof is to realize an optical signal demodulating device which can accurately demodulate the pulse width of a transmitted code signal and is less likely to malfunction. is there.

[0011]

In order to solve the above-mentioned problems, an optical signal demodulating device according to a first aspect of the present invention includes a light-receiving element for receiving an optical code signal modulated by a pulse of a specific frequency, and the above-mentioned light-receiving device. An optical signal demodulating device having a discriminating means for discriminating the specific frequency from the detection signal of the element and a converting means for converting the discriminating signal of the discriminating means into a pulse signal is characterized in that the following means are taken. .

That is, clock signal generating means for generating a clock signal, synchronization control means for synchronizing the clock signal generated by the clock signal generating means with the pulse signal, and operating based on the clock signal, the clock signal And counting means for counting the number of pulses of the pulse signal synchronized with, and for outputting a code signal having a pulse width corresponding to the number of pulses when the counted number of pulses exceeds a predetermined lower limit value.

In the above structure, for example, the light receiving element including a photodiode receives the optical code signal. The discriminating means discriminates the specific frequency from the detection signal of the light receiving element. As a result, the component of the optical code signal modulated by the pulse of the specific frequency is extracted. Further, the conversion means shapes the output signal of the discrimination means and converts it into a pulsed signal.

The synchronization control means identifies the phase of the pulse signal based on, for example, a change in output, and the clock signal generation means synchronizes the generated clock signal with the pulse signal based on the instruction of the synchronization control means. Thereby, the clock signal generating means generates a clock signal synchronized with the pulse signal.

For example, the counting means including a shift register circuit operates based on the clock signal, and counts the number of pulses synchronized with the clock signal from the pulse signal. Further, when the counted number of pulses exceeds a predetermined lower limit value, the counting means determines the pulse signal as an optical code signal and outputs a code signal having a pulse width corresponding to the number of pulses.

In the above structure, the counting means counts the number of pulses of the pulse signal synchronized with the clock signal. Therefore, when the light receiving element receives noise and a pulse signal that is not synchronized with the clock signal is generated, or when the number of received pulses is less than the above lower limit value, the counting means does not output the code signal. As a result, in the optical signal demodulation device, it is possible to improve the noise / signal separation characteristics.

Further, the counting means determines the pulse width of the code signal to be output based on the counted number of pulses. Therefore, as in the case of envelope detection using a conventional integrating circuit, the code signal does not fluctuate due to the fluctuations in the resistance and capacitance forming the integrating circuit. It can always be constant for numbers. As a result, the pulse width of the demodulated signal becomes the same as the pulse width before modulation, and the waveform distortion during demodulation can be reduced.

According to a second aspect of the present invention, in the optical signal demodulating device according to the first aspect of the invention, the clock signal generating means includes an oscillator that generates a basic clock of the clock signal. The oscillator is characterized by being provided with a set-reset flip-flop circuit that resets the output in response to an instruction from the synchronization control means.

In the above structure, the oscillator oscillates at a predetermined frequency to generate the basic clock of the clock signal. When instructed by the synchronization control means, the set-reset flip-flop circuit provided in the oscillator resets the output of the oscillator. The set / reset flip-flop circuit can be realized by, for example, a simple circuit using two NAND circuits. Therefore, the clock signal generating means can be configured without using a large-scale circuit. As a result, the cost for manufacturing the optical signal demodulation device can be suppressed.

Further, in the optical signal demodulating device according to the invention of claim 3, in the configuration of the invention according to claim 2, the clock signal generating means divides the output of the oscillator and the synchronization control means of the synchronizing control means. From the frequency divider that is reset according to the instruction, the output of the oscillator and the output of the frequency divider,
And an output unit for generating a clock signal.

In the above structure, the frequency divider divides the basic clock generated by the oscillator, and the output section generates a clock signal from the output of the frequency divider and the basic clock. Further, the frequency divider, according to the instruction of the synchronization control means,
Will be reset.

By the way, when the frequency divider simply divides the output of the oscillator, even if the pulse signal and the basic clock are synchronized, the phase difference between the pulse signal and the clock signal is There is a possibility that they may be different from each other depending on the state of the frequency divider at the time of input. However, since the frequency divider resets the output according to the instruction of the synchronization control means, the phase difference between the pulse signal and the clock signal can be maintained even when the frequency divider is used.

Further, the frequency divider and the output section can be realized by a simple circuit such as a D-type flip-flop or a NAND circuit. Therefore, the cost for manufacturing the optical signal demodulation device can be suppressed.

On the other hand, in the optical signal demodulating device according to the invention of claim 4, in the configuration of the invention of claim 1, 2 or 3, the oscillation frequency of the clock signal generating means and the frequency discriminated by the discriminating means. It is characterized by having an external resistor that determines both.

Therefore, by using the external resistor, both frequencies can be determined with higher accuracy, as compared with the case where it is determined by the resistor provided in the integrated circuit. Further, even if the resistance value varies slightly, the error is the same, so that the ratio of both frequencies can be made constant. Thereby, the pulse width distortion at the time of demodulation of the optical signal demodulation device can be further reduced. In addition, since the external resistor is shared by the discriminating means and the clock signal generating means, the number of parts can be reduced as compared with the case where they are individually provided.

Further, in the optical signal demodulating device according to the invention of claim 5, in the structure of the invention according to claim 1, 2, 3 or 4, the lower limit value of the counting means is set to 5 or more. It is characterized by that.

In the above structure, the fluorescent lamp, which is the main noise source of the optical signal demodulation device, usually produces less than 5 times of noise, but the counting means receives code even if less than 5 times of noise is input. No signal is output. Therefore, it is possible to realize an optical signal demodulating device that does not respond to the noise light emitted by the fluorescent lamp.

Further, in the optical signal demodulating device according to the invention of claim 6, in the configuration of claim 5, the counting means comprises a D-type flip-flop having a number of stages according to a lower limit value which is operated by the clock signal. A shift register circuit and an output logic circuit that outputs a code signal based on the output of the shift register circuit are provided.

In the above configuration, the shift register circuit delays the input pulse signal by the lower limit value. The output gate generates a code signal from the output of the D flip-flop of each stage when the number of pulses exceeds the lower limit value. The shift register circuit and the output logic circuit can be realized by a D-type flip-flop and a basic logic circuit such as a NAND circuit, for example. As a result, it is possible to realize an optical signal demodulating device with high accuracy and little variation with a simple configuration.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
It is as follows when it demonstrates based on FIG.
The optical signal demodulating device according to the present embodiment is provided, for example, in a remote control device or the like, and is used by an optical signal transmitting device to demodulate an optical code signal pulse-modulated at a specific frequency.

As shown in FIG. 1, the optical signal demodulating device includes a photodiode (light receiving element) 1 for converting an optical signal from an optical signal transmitting device (not shown) into an electric signal, and a preamplifier for amplifying the electric signal. Amplifier unit 2 and AC amplifier unit 3
And a bandpass filter (discrimination means) 4 for discriminating a specific frequency component from the output signal v _o3 of the AC amplifier unit 3,
It is provided with an integrating circuit 5 and a comparator (conversion means) 6 for converting the output signal v _o4 of the band pass filter 4 into a pulsed signal v _o6 .

Further, the optical signal demodulator according to the present embodiment is connected to the comparator 6 via the capacitor C1 and an output change detection circuit (synchronization control means) 7 for detecting a change in the output signal v _o6. , Oscillator 81, frequency divider 8
2, and a NAND circuit (output unit) 83,
According to the instruction of the output change detection circuit 7, the pulse signal v
clock generator for generating a clock signal synchronized with _o6 and (clock signal generation means) 8, in the pulse signal v _o6, clock signal v of the clock generator 8 has generated
_The number of pulses synchronized with _o8 is counted, and when the number of pulses exceeds a predetermined number, a code signal v having a pulse width corresponding to the number of pulses
and a digital counting circuit (counting means) 9 for outputting _o . In addition, the optical signal demodulation device supplies a constant current I ₁₀ to each circuit 4 and 81 in order to determine the center frequency of the bandpass filter 4 and the oscillation frequency of the oscillator 81.
A constant current circuit 10 for respectively supplying

The preamplifier section 2 includes a preamplifier 2a in which the cathode of the photodiode 1 is connected to the input side,
Feedback resistor 2b for connecting the input and output of the preamplifier 2a
And As a result, the photodiode 1
External light is received and changes in the amount of received light are converted into changes in the output current.
The output photocurrent can be converted from current to voltage. The anode of the photodiode 1 is grounded.

Further, the AC amplifier section 3 includes an operational amplifier 3a, a resistor 3b provided between the input and output of the operational amplifier 3a, and a resistor 3c having one end connected to the input of the operational amplifier 3a. Further, a capacitor 3d is provided between the other end of the resistor 3c and the preamplifier unit 2, and the preamplifier unit 2 and the operational amplifier 3a are connected to each other.
C-bonded. As a result, the AC amplifier unit 3 can amplify the AC component of the output signal v _o2 of the preamplifier unit 2 with a predetermined amplification factor. When the values of the resistors 3b and 3c are R _3b and R _3c , respectively, the amplification factor of the AC amplifier unit 3 is R _3b / R _3c .

The bandpass filter 4 provided at the latter stage of the AC amplifier section 3 is an active filter composed of, for example, an operational amplifier. The center frequency of the bandpass filter 4 is determined based on the current value supplied from the constant current circuit 10. Thus, A
A specific frequency corresponding to the frequency of the optical code signal can be discriminated from the signal v _o3 input from the C amplifier unit 3.

The integrator circuit 5 includes a transconductance amplifier (current output type differential amplifier) 5a having an output terminal and an inverting input terminal connected to each other, and a potential of the non-inverting input terminal, that is, a bandpass filter. A current value I _5a corresponding to the output voltage v _{o4 of} 4 can be output. The output terminal of the transconductance amplifier 5a is grounded via the capacitor 5b. Further, the output terminal, a constant current source 5c is connected for supplying a current I _5c constant value. Thus, the capacitor 5b is charged by I _5a -I _5c, it is discharged by I _5c. Therefore, the integration circuit 5, the integrated value of the output signal v _o4, can be output as a potential difference v _o5 capacitor 5b. The current value I _5c of the constant current source 5c is set to I _5a −I _5c > I _5c , that is, I _5c <I _5a / 2.

Further, the comparator 6 is realized by a operational amplifier compares the output signal v _o4 of the band-pass filter 4, the output signal v _o5 of the integration circuit 5, v _o4
Can be output as a binary level signal.
As a result, the output signal v _o4 can be converted into a pulsed signal v _o6 .

Further, the output change detection circuit 7 according to the present embodiment receives the pulse signal v _o6 via the capacitor C1 and detects the output change of the signal v _o6 such as rising, and the clock generation unit 8 described later. Can be sent as a reset signal. As a result, the phase difference between the clock signal v _o8 output by the clock generator 8 and the signal v _o6 can be adjusted.

The oscillator 81 provided in the clock generator 8 can oscillate at a predetermined frequency based on the constant current I ₁₀ supplied from the constant current circuit 10. Also, the frequency divider 82
Is a synchronous frequency divider composed of a D-type flip-flop, and can divide the output of the oscillator 81 by two. Further, the NAND circuit 83 is provided with the oscillator 8
The clock signal v _o8 can be generated by negating the logical product of 1 and the output of the frequency divider 82. The oscillator 81 and the frequency divider 82 are reset by the reset signal from the output change detection circuit 7. Thus, the clock generating unit 8 has a predetermined frequency, and generates a clock signal v _o8 no output signal v _o6 and phase difference of the comparator 6 can be output to the digital counting circuit 9.

Here, a concrete configuration example of the oscillator 81 provided in the output change detection circuit 7 and the clock generation section 8 will be described with reference to FIGS. 2 and 3 as follows.

That is, as shown in FIG. 2, the oscillator 81 according to the present embodiment repeats charging / discharging with a predetermined time constant to determine the oscillation frequency of the oscillator 81.
1a and a constant current source 81b serving as a current source of the oscillator 81.
When the constant voltage source 81c to produce a reference voltage v ₂ and v ₃ which is the upper limit or lower limit of the voltage across v ₁ of the capacitor 81a, and the reference voltage v ₂ or v _3, and the voltage across v ₁ The first and second comparators 81d and 81e for respectively comparing Further, the oscillator 81 is composed of NAND circuits 81f and 81g which are interleaved with each other, and is set or reset by both comparators 81d and 81e.
-FF circuit) 81h and the RS-FF circuit 81
A charging / discharging control circuit 81i for controlling charging / discharging of the capacitor 81a according to the output of h is provided.

The constant current source 81b includes a current mirror circuit composed of PNP type transistors Q ₁₁ to Q ₁₅ whose bases are connected to each other. Transistor Q ₁₁
The collector and the base are connected to each other, and a predetermined constant current I ₁₀ is supplied from the constant current circuit 10 shown in FIG. The collector of the transistor Q ₁₂ is grounded via the capacitor 81a, and the collectors of the transistors Q ₁₃ to Q ₁₅ are respectively connected to the first
It is connected to the comparator 81d, the second comparator 81e, and the charge / discharge control circuit 81i. On the other hand, the power supply voltage V _cc is applied to the emitters of the transistors Q ₁₁ to Q ₁₅ . As a result, the constant current source 81b supplies the constant current I to each of the circuits 81a, 81d, 81e and 81i.
Can supply ₁₀ .

The constant voltage source 81c has an NPN transistor Q ₁₆ whose base and collector are connected to each other. The collector of the transistor Q _16, further provided with power V _cc is applied, the emitter is grounded through a resistor R ₁₁ · R ₁₂ · R ₁₃ connected in series. Therefore, the current flowing through the resistors R ₁₁ , R _12, and R ₁₃ has a constant value, that is, (V _cc −V _BE ) / (R ₁₁ + R
₁₂ + R ₁₃ ). Note that V _BE in the above equation is the base-emitter voltage of the NPN transistor Q ₁₆ . Since the transistors shown in FIGS. 2 to 3 are formed on an integrated circuit, hereinafter, the base-emitter voltage of each NPN transistor is not particularly distinguished and is represented by V _BE .

As a result, the constant voltage source 81c calculates the potential v _{1 at} the connection point between the resistors R ₁₁ and R ₁₂ and the potential v ₂ at the connection point between the resistors R ₁₂ and R ₁₃ by the following equation (1). And as shown in (2), v ₂ = (V _cc −V _BE ) × (R ₁₂ + R ₁₃ ) / (R ₁₁ + R ₁₂ + R ₁₃ ) ... (1) v ₃ = (V _cc −v _BE ) × R ₁₃ / (R ₁₁ + R ₁₂ + R ₁₃ ) ... (2) It can be maintained at a constant value.

[0045] Furthermore, the first comparator 81d, the voltage v ₁ or v ₂ to be compared, the transistors Q ₂₁ and Q ₂₂ are applied to the respective bases, and a current mirror circuit, two transistors Q ₂₁ · An NPN transistor Q that absorbs the same amount of current as the current output from the collector of the transistor Q ₂₁ from the collector of Q ₂₂
And _{23 ·} Q _24, a base connected to the collector of the transistor Q _22, the transistor Q than the transistor Q _21
22 is provided with a transistor Q ₂₅ which conducts when a large amount of current flows.

The base of the transistor Q ₂₁ is grounded through the capacitor 81a, and the transistor Q ₂₂
The base of is connected to the connection point of the resistors R ₁₁ and R ₁₂ of the constant voltage source 81c. As a result, both transistors Q
The base of ₂₁ · Q ₂₂ is the capacitor 81 to be compared.
The both-end voltage v _{1 of} a and the upper limit voltage v ₂ of the capacitor 81a generated by the constant voltage source 81c are applied.

The emitters of the transistors Q ₂₁ and Q ₂₂ are the transistors Q ₁₃ provided in the constant current source 81b.
Connected to the collector. On the other hand, both transistors Q
The collectors of ₂₁ and Q ₂₂ are connected to the collectors of the transistors Q ₂₃ or Q ₂₄ , respectively. The base and collector of the transistor Q ₂₃ are connected to each other, and the emitters of both transistors Q ₂₃ and Q ₂₄ are grounded.

The base of the transistor Q ₂₅ is the collector of the transistor Q ₂₂ and the transistor Q _22.
It is connected to the intersection of ₂₄ collectors, and the collector is connected to the set terminal of the RS-FF circuit 81h, that is, one input of the NAND circuit 81f. The emitter of the transistor Q ₂₅ is grounded.

Thus, the voltage v ₁ across the capacitor 81a is compared with the upper limit voltage v ₂ generated by the constant voltage source 81c, and when the upper limit voltage v ₂ is larger, the transistor Q ₂₅ is turned on. As a result, the RS-FF circuit 81h can be set by inputting a low level signal to the NAND circuit 81f.

On the other hand, the second comparator 81e has the same structure as the first comparator 81d as described above, to the transistors Q ₂₁ in response to Q _25, to the transistors Q ₃₁ and a Q _35. However, the second comparator 81
In e, the base of the transistor Q ₃₁ is the constant voltage source 8
It is connected to the connection point between the resistors R ₁₂ and R ₁₃ provided in 1c, and the base of the transistor Q ₃₂ is connected to the ungrounded end 81j of the capacitor 81a. The collector of the transistor Q ₃₅ is RS-FF.
The reset terminal of the circuit 81h, that is, the NAND circuit 8
Connected to one of the 1g inputs. The other connections are the same as those of the first comparator 81d.

As a result, the second comparator 81e is
The voltage v ₁ across the capacitor 81a and the constant voltage source 8
The lower limit voltage v ₃ generated in 1c is compared, and v ₁ <v
_In the case of ₃ , the transistor Q ₃₅ can be turned on, a low-level signal can be applied to the NAND circuit 81g, and the RS-FF circuit 81h can be reset.

Further, in the RS-FF circuit 81h, the NAND circuits 81f and 81g are interleaved with each other and become the output NA of the RS-FF circuit 81h.
The output of the ND circuit 81f is connected to one input of the NAND circuit 81g, and the output of the NAND circuit 81g is NAN.
It is connected to one of the inputs of the D circuit 81f. Therefore, the other input of the NAND circuit 81f becomes the set terminal of the RS-FF circuit 81h, and the other input of the NAND circuit 81g becomes the reset terminal. Further, the set terminal and the reset terminal are connected to the first or second comparator 81d / 81e as described above.

The charge / discharge control circuit 81i has NPN transistors Q ₄₁ to Q ₄₃ whose bases are connected to each other.
And an NP which conducts according to the output of the NAND circuit 81g and controls the operation / stop of operation of the current mirror circuit.
And an N-type transistor Q ₄₄ . In the transistor Q ₄₁ , the collector and the base connected to each other are the transistor Q ₁₅ provided in the constant current source 81 b.
Connected to the collector. Also, the transistor Q ₄₂
And in Q ₄₃ , both collectors are capacitor 8
It is connected to the end 81j of 1a. The transistors Q ₄₁ to Q ₄₃ form a current mirror circuit. Further, in the transistor Q _44, the collector, to the connection point between the collectors of the transistors Q ₁₅ of the transistor Q _41, the base is the NA
Each of them is connected to the output of the ND circuit 81g. The emitters of the transistors Q ₄₁ to Q ₄₄ are
Each is grounded.

[0054] Thus, the inverted output of the RS-FF circuit 81h, that is, when the output of the NAND circuit 81g is low, the transistor Q ₄₄ is turned off, a current mirror circuit consisting to the transistors Q ₄₁ Q ₄₃ is operated. As a result, the amount of current flowing from the collectors of the transistors Q ₄₂ and Q ₄₃ to the transistor Q ₄₁ , that is,
The same current as the current value I ₁₀ supplied from the constant current source 81b is absorbed. Therefore, the amount of current I _81i absorbed by the charge / discharge control circuit 81i from the capacitor 81a is 2 × I _10.
Becomes

By the way, the constant current I ₁₀ is constantly supplied to the capacitor 81a from the constant current source 81b. Therefore, while the charge / discharge control circuit 81i is absorbing the current, the constant current I ₁₀ − is supplied from the capacitor 81a.
I _81i , that is, I _10, is discharged, and the charge / discharge control circuit 8
While 1i is not absorbing the current, the constant current I ₁₀ is charged in the capacitor 81a. As a result, the charge / discharge control circuit 81i can control whether to charge the capacitor 81a according to the output of the NAND circuit 81g.

On the other hand, as shown in FIG. 3, the output change detection circuit 7 is connected to the comparison unit 71 for detecting the output change of the comparator 6 shown in FIG. 1 and the end 81j of the capacitor 81a provided in the oscillator 81. A transistor Q ₅₁ which is connected and conducts at the time of resetting to lower the potential of the end 81j;
A constant voltage source 72 for applying a constant voltage to the base of the transistor Q ₅₁ , and an output control circuit 73 for controlling conduction / interruption of the transistor Q ₅₁ according to the output of the comparison unit 71 are provided. The output of the comparison unit 71 is the frequency divider 82.
NPN transistor Q connected to the reset terminal of
Connected to the base of ₆₂ . As a result, when the comparator 71 detects a change in the output voltage v _o6 of the comparator 6, the transistor Q ₆₂ is turned on and the frequency divider 82 is turned on.
Can be reset. Further, the transistor Q ₅₁ becomes conductive according to an instruction from the output control circuit 73. As a result, the voltage v ₁ across the capacitor 81a can be lowered and the oscillator 81 can be reset.

The comparator 71 has a reference voltage v ₅₁ generated by dividing the power supply voltage V _cc by resistors R ₅₁ and R ₅₂ connected in series and an output voltage v ₅₁ of the comparator 6.
A change detection comparator 71a for comparing with _o6 is provided. The inverting input terminal of the change detection comparator 71a is
It is connected to the connection point between the resistors R ₅₁ and R ₅₂ , and the non-inverting input terminal is connected to the comparator 6 via the capacitor C1. The connection point between the non-inverting input terminal and the capacitor C1 is connected to the power supply voltage V _cc via the bias resistor R ₅₃ and is also grounded via the bias resistor R ₅₄ . The resistance value of each of the resistors R ₅₁ to R ₅₄ is R ₅₄ / (R ₅₃ + R ₅₄ ) <R ₅₂ / (R ₅₁ + R ₅₂ ).
Is set to Furthermore, the change detection comparator 71
The a is connected to the transistor Q ₆₂ connected to the frequency divider 82 and the output control circuit 73 via the resistor R ₅₅ . As a result, the comparing section 71 outputs a high level signal to the transistor Q ₆₂ and the output control circuit 73 when the output voltage v _o6 rises, and otherwise outputs a low level signal. You can

Further, the constant voltage source 72 is connected to the power source voltage V _cc in the same manner as the constant voltage source 81c shown in FIG.
A PN transistor Q ₆₁ has a resistor R connected in series.
It is configured to be grounded via ₆₁ and R ₆₂ . As a result, the constant voltage source 72 can maintain the potential of the connection point of the resistors R ₆₁ and R ₆₂ , that is, the potential of the base of the transistor Q _{51 at} a constant potential v _o72 . The reference voltage v
_o72 is V _o72 = R ₆₂ · (V _cc −V _BE ) / (R ₆₁ + R ₆₂ ), where V _BE is the base-emitter voltage of the transistor Q ₆₁ , as shown in the following formula (3). (3)

The reference voltage v _o72 is the same as the transistor Q _51.
Is conducted, its emitter potential v _o73 , that is,
The voltage v ₁ across the capacitor 81a is set to be lower than the lower limit voltage v ₃ of the capacitor 81a generated by the constant voltage source 81c shown in FIG. Therefore, when the base-emitter voltage of the transistor Q ₅₁ is V _BE , the reference voltage v _o72 is set to v _o72 −V _BE <v ₃ (4) as in the following expression (4). .

The output control circuit 73 includes NPN type transistors Q ₇₁ and Q ₇₂ whose bases are connected to each other. The base and collector of the transistor Q ₇₁ are
They are connected to each other, and the comparison unit 71 is connected to the base.
Output voltage v _o71 is applied. Also, the transistor Q
The collector of ₇₂ is connected to the emitter of the transistor Q ₅₁ . The emitters of both transistors Q ₇₁ and ₇₂ are grounded. Accordingly, when the output voltage v _o71 of the comparison unit 71 is at the high level, the output control circuit 73
Can conduct to bias the transistor Q ₅₁ .

As a result, when the output voltage v _{o6 of the} comparator 6 shown in FIG. 1 rises, the output change detection circuit 7 has the end 8 of the capacitor 81a provided in the oscillator 81.
The oscillator 81 can be reset by lowering the potential of 1j to v _o73 .

Further, as shown in FIG. 4, the digital counting circuit 9 according to the present embodiment has a shift register section (shift register circuit) 91 composed of D-type flip-flops 91a to 91e connected in series, and a shift register. Part 9
An output gate circuit (output logic circuit) 92 for demodulating a code signal based on the output of 1 and the shift register unit 9
1 and an initial reset circuit 93 for initializing 1.

In the shift register section 91, in the D-type flip-flop 91a at the first stage, the pulse signal v _o6 output from the comparator 6 is applied to the D input, and in the D-type flip-flops 91b to 91e at the subsequent _stages , The Q output of the previous stage is applied to the D input. The clock inputs of the D-type flip-flops 91a to 91e are low active, and the clock inputs (C
The clock signal v _o8 generated by the clock generator 8 is applied to K).

As a result, the shift register section 91 shifts the stored data to 1 at each falling edge of the clock signal v _o8.
The pulse signal v _o6 can be stored in the first stage by shifting to the _next stage and storing it. In addition, each stage of the shift register unit 91 holds data until the next fall, and outputs the data from the Q output.

The output gate circuit 92 outputs the Q outputs of the D-type flip-flops 91a to 91e and all NAs.
It is provided with a 5-input NAND circuit 92a for taking ND, a 5-input OR circuit 92b for calculating the OR of all Q outputs, and a set / reset flip-flop (hereinafter, referred to as RS-FF) 92c. The RS-FF92c is
It is configured by crossing two NAND circuits 92d and 92e, and the output v _o92a of the 5-input NAND circuit 92a.
_{Is a} set input, and the output of the 5-input OR circuit 92b is v _o92b
Is used as the reset input. The set and reset inputs are both low active.

As a result, the output v of the output gate circuit 92 is
_o level, during the period the output v _92b is at a high level of 5-input OR circuit 92b, when the output v _{o9 2a} five-input NAND circuit 92a is changed to a low level, a high level. Further, the output gate circuit 92, v _O92a is high level, v _O92b the duration of the high level to maintain the level of the output v _o. When v _o92b goes low, the output gate circuit 92 sets its output v _o low.

The initial reset circuit 93 is also provided.
Are connected to the reset inputs (R) of the D flip-flops 91a to 91e. This allows, for example,
When the power is turned on, the initial reset circuit 93 can clear the data currently stored in the shift register unit 91. As a result, the output of the shift register unit 91 and the output v _o of the digital counting circuit 9 calculated based on the output are
It becomes the same as the non-reception state of the code signal.

Further, the constant current circuit 10 according to the present embodiment.
Includes an external resistor R1 and a current mirror circuit composed of NPN transistors Q1 to Q3, and supplies a constant current determined by the external resistor R1 to the bandpass filter 4 and the oscillator 81. it can. The bases of the transistors Q1 to Q3 are connected to each other, and the emitters thereof are grounded. The collector of the transistor Q1 is connected to the base. The external resistor R1 is connected to the collector.
The power supply voltage V _cc is applied via. The collector of the transistor Q2 is connected to the bandpass filter 4, and the collector of the transistor Q3 is connected to the oscillator 81. As a result, a current mirror circuit is formed, and the constant current circuit 10 includes the bandpass filter 4 and the oscillator 8
1, a constant current I ₁₀ can be supplied. Above constant current I
_10, as shown in the following equation (5) is determined by _{I 10 = (V cc -V BE} ) / R1 ··· (5) external resistor R1. In the above equation, V _BE is the base-emitter voltage of the transistor Q1.

The operation of each unit when the optical signal demodulating device receives the optical code signal in the above configuration will be described with reference to FIGS. 5 to 7.

That is, the optical signal transmitter (not shown)
As shown in FIG. 5A, the code signal at the high level during the period T _in is modulated by the pulse having the predetermined frequency. Further, as shown in FIG. 5B, the optical signal transmission device transmits the modulated signal as an optical code signal using, for example, infrared rays.

In the optical signal demodulating device shown in FIG. 1, the preamplifier section 2 uses the photodiode 1 to convert the optical code signal into an electric signal, and outputs it as shown in FIG. 5 (c). Output as a change in voltage v _o2 . Furthermore, FIG.
(D), the AC amplifier unit 3 amplifies the AC component of the output signal v _o2 .

The bandpass filter 4 includes the AC amplifier section 3
From the output signal v _o3 of, the component of a specific frequency is discriminated.
As a result, the bandpass filter 4 outputs a substantially sine-shaped signal v _o4 as indicated by the solid line in FIG. The pass band of the band pass filter 4 is the constant current circuit 1
It is determined by the amount of current I ₁₀ supplied from 0 to the bandpass filter 4.

The integrating circuit 5 integrates the output signal v _o4 . In the integrating circuit 5, if the output current of the transconductance amplifier 5a is I _5a and the current supplied by the constant current source 5c is I _5c , the capacitor 5b is charged by I _5a.
-I _5c , discharge is performed by I _5c . Therefore,
The time constant for discharging is (C _5b × Δv _o5 ) / I _5c , and the time constant for charging is (C _5b × Δv _o5 ) / (I _5a
-I _5C ). Further, the current value of the constant current source 5c is I
_{Since 5a−} I _5c <I _5c is set, the discharge time constant becomes larger than the charge time constant. Therefore, FIG.
In (e), the output voltage v _o5 of the integrating circuit 5 rises each time the pulse modulation code signal is received, as indicated by the broken line. As a result, the noise margin in the comparator 6 in the subsequent stage can be increased.

The comparator 6 includes the bandpass filter 4
And the output voltage v _o4, by comparing the output voltage v _o5 of the integration circuit 5, as shown in (f) of FIG. 5, if v _o5 is large, when a high level, v _o5 is small, low It outputs a pulsed signal v _o6 that becomes a level. The pulsed signal v
_o6 is transmitted to the output change detection circuit 7 and the digital counting circuit 9.

The output change detection circuit 7 detects the rising _edge of the pulsed signal v _o6 and supplies it as a synchronization signal to the oscillator 81 and the frequency divider 82 provided in the clock generation section 8 at each rising time point. .

On the other hand, in the oscillator 81, as shown in FIG. 6C, while the synchronizing signal is not input (t4
Up to the period), and oscillates in a predetermined cycle. Further, the frequency divider 82 frequency- _divides the output signal v ₀₈₁ of the oscillator 81, as shown in FIG. The internal operation of the oscillator 81 according to this embodiment will be described in detail later with reference to FIGS. 2 and 3.

At time t4, the output change detection circuit 7
When a synchronization signal is input from the oscillator 81 to the oscillator 81, the oscillator 81
Is reset. As a result, the output signal v _o81
Of the pulse signal v _o6 coincides with the _subsequent rising edge of the pulse signal v _o6 .

The frequency divider 82 is also reset. As a result, the output signal v _{o8 2} of the frequency divider 82 is inverted every time the output signal v _o81 falls, with the high level at the rising of the first pulse signal v _{o6.
Divide o81} by two.

Further, the NAND circuit 83, as shown in FIG. 6 (e), outputs both output signals v ₀₈₁ and v 0.
_Takes the _negation of the logical product of _o82 . Accordingly, NAND circuit 83 sends a pulse waveform v _o8 synchronized with the output variation of the pulse signal v _o6 to digital counting circuit 9.

The digital counting circuit 9 operates using the pulse signal v _o6 shown in FIG. _7A as an input and the clock signal v _o8 shown in FIG. _7B as a clock signal. In the digital counting circuit 9, the D-type flip-flops 91a to 91e provided in the shift register unit 91 _hold the input signal at the falling edge of the clock signal v _o8 until the next falling edge of the clock signal v _o8 , It is outputting. The D-type flip-flop 91a at the first stage receives v _o6 as an input signal, and the D-type flip-flop 91a at the next stage and thereafter.
b to 91e are D-type flip-flops 91a in the preceding stage
9 to 91d Q output is input.

Therefore, as shown in FIG. 7C,
The D-type flip-flop 91a is at the high level _{while the} pulsed signal v _o6 is at the high level at each falling edge of the clock signal v _o8 . Consequently, the signal v _O91a a pulse width corresponding to the number of pulses of the pulsed signal v _o6 synchronized with the clock signal v _o8 is obtained. Furthermore, to no D-type flip-flop 91b 91e, as shown in to (d) no in FIG 7 (g), the signal v _O91a, and outputs a free signal v _O91b delayed by one clock to _v o91e.

[0082] Furthermore, 5-input NAND circuit 92a, as shown in (h) of FIG 7, to the free signals _v o91a v
_Taking the _negation of the logical product of _o91e , the 5-input OR circuit 92b
As shown in (i) of FIG. 7, the _signals v _o91a through v _o91a
Take the logical sum of _o91e . The RS-FF _92c sets the output signal v _o92a of the 5-input NAND circuit 92a to a set signal, 5
The output signal v _o92b of the input OR circuit 92b operates as a reset signal, and as shown in (j) of FIG.
The output signal v _{o of out} is output.

The output signal v _o has a pulse waveform obtained by delaying the code signal shown in FIG. 5A by five pulse-modulated code signals shown in FIG. 5B. The width T _out is the same as the pulse width T _{in of the} code signal.

Next, regarding the operation inside the oscillator 81,
The following is a description with reference to FIG. 2 based on FIG. 6.

That is, the voltage v across the capacitor 81a
₁ and the upper limit voltage v ₂ generated by the constant voltage source 81c
When the magnitude relationship with the lower limit voltage v ₃ is v ₁ <v ₃ , the transistor Q ₃₅ becomes conductive in the second comparator 81e of the oscillator 81 shown in FIG. As a result, the output voltage v _{o81e of} the comparator 81e, that is, RS-
The reset input of the FF circuit 81h becomes low level.

In this case, v ₁ <v ₂ is always established. Accordingly, in a first comparator 81d, the transistor Q ₂₅ is cut off, the output voltage v _O81d of the comparator 81d, i.e., the set input of RS-FF circuit 81h is at the high level.

As a result, the RS-FF circuit 81h is reset, and the output voltage _vo81 becomes low level.
Further, the NA serving as the inverting output terminal of the RS-FF circuit 81h
The ND circuit 81g outputs a high level output voltage v _o81g .

[0088] Thus, in the charge and discharge control circuit 81i, and conducts the transistors Q _44, current mirror circuit consisting to the transistors Q ₄₁ Q ₄₃ does not operate. As a result, the current I absorbed by the charge / discharge control circuit 81i
_o81i becomes 0, and the capacitor 81a is the constant current source 81
It is charged by the current I ₁₀ supplied from the transistor Q _{12 of} b.

When the voltage v ₁ across the capacitor 81a rises due to charging and v _{3 ≤v 1} <v ₂ , the second comparator 81e shuts off the transistor Q ₃₅ and the output voltage v _o81e becomes high. It becomes a level. Also,
Since v ₁ <v ₂ , the output voltage v _o81d of the first comparator 81d becomes high level. Therefore, RS-FF
The reset input of the circuit 81h becomes high level and the set input becomes high level. In this state, the RS-FF circuit 81h remains in the previous state due to the characteristics of the flip-flop. As a result, the output voltage v of the oscillator 81
_o81 is kept at low level and capacitor 81a
Is continuously charged (the period from t1 to t2 in FIG. 6).

When v ₂ ≦ v ₁ is obtained by charging, the first
The transistor Q _{25 of the} comparator 81d becomes conductive. In addition, the transistor Q ₃₅ of the second comparator 81e remains cut off. As a result, the set input becomes low level, the reset input becomes high level, and RS-
The FF circuit 81h is set. As a result, the oscillator 81
_Sends out a high level signal v _o81 .

On the other hand, the output voltage v _o81g of the NAND circuit 81g of the RS-FF circuit 81h changes to the low level. Accordingly, the charge and discharge control circuit 81i, cut off the transistor Q _44, current mirror circuit consisting to the transistors Q ₄₁ Q ₄₃ is operated. As a result, the current I _{o81i absorbed} by the charge / discharge control circuit 81i becomes 2 × I ₁₀ . As a result, the capacitor 81a becomes the constant current source 81
Discharge is started at the difference between the input current I ₁₀ from b and the constant current I _o81i , that is, the constant current I ₁₀ (t2 in FIG. 6).
Point of time).

When the voltage v ₁ across the capacitor 81a returns to v ₃ ≤v ₁ <v _{2 due} to discharge, the RS-FF circuit 81h maintains the previous state, as described above. As a result, the output voltage _vo81 of the oscillator 81 is maintained at the high level, and the capacitor 81a continues discharging (the period from t2 to t3 in FIG. 6).

When the voltage v ₁ across the capacitor 81a decreases and v ₁ <v ₃ again, the RS-FF circuit 81h
Is reset as described above (at time t3 shown in FIG. 6), and charging is started.

Therefore, as shown in FIG.
When the synchronization signal from the output change detection circuit 7 is not input (until t4), the oscillator 81 repeats charging / discharging of the capacitor 81a to continue oscillation, and the voltage v ₁ across the capacitor 81a is maintained. As shown in FIG. 6B, the voltage fluctuates periodically between the upper limit voltage v ₂ and the lower limit voltage v ₃ .

Both comparators 81d and 81e shown in FIG.
Is the voltage v ₁ across the capacitor 81a and the upper limit voltage v ₂
Alternatively, the lower limit voltage v ₃ is compared, and the both-end voltage v ₁ is v ₂
Is reached, the first comparator 81d causes the RS-FF
To circuit 81h, and it sends a set signal, when the v ₁ reaches v _3, second comparator 81e is, RS-FF circuit 8
Send a reset signal to 1h.

As a result, the output voltage v _o81 of the RS-FF circuit 81h, that is, the oscillator 81, is the upper limit voltage v ₁ with the voltage v ₁ across the capacitor 81a as shown in (c) of FIG.
Each time it reaches _2, it goes high, and every time it reaches the lower limit voltage v _3, it goes low.

On the other hand, when the pulse signal v _o6 rises, the output change detection circuit 7 shown in FIG. 3 makes the transistor Q ₅₁ conductive at each rising time. As a result, the voltage v ₁ across the capacitor 81a provided in the oscillator 81 is
_Falls to v _o73 and the oscillator 81 is reset. The reset voltage v _o73 is set so that v _o73 ≦ v ₃ .

When the oscillator 81 is reset, the voltage v ₁ across the capacitor 81a is v ₁ <v ₃ <v ₂ . Therefore, both comparators 81d.8 shown in FIG.
As described above, 1e outputs the high-level set signal and the low-level reset signal to the RS-FF circuit 81h.
And the capacitor 81a starts charging (FIG. 6).
(At time t4).

Thereafter, as in the case where the oscillator 81 is not set, the capacitor 81a is not charged until the voltage v _{1 at} both ends reaches the upper limit voltage v ₂ (the period from t4 to t5 in FIG. 6). Then, the oscillator 81 outputs the low level signal v _o81 . It becomes the point of t5, reaches the upper limit voltage v _2, the capacitor 81a, a discharge is started. Then, while the voltage v ₁ across both ends falls to the lower limit voltage v ₃ (the period from t5 to t6 in FIG. 5), the capacitor 81a is continuously discharged, and the oscillator 81 outputs the high-level signal v _o81 . . As a result, the oscillator 8
1 is (c) of FIG. 6 after the pulse signal v _o6 is input.
As shown in, the falling oscillator output v _o81 is generated every time the pulse signal v _o6 rises.

The capacitor 81a is charged with a current value I ₁₀ during the charging period, and is discharged with I _{81 i} -I ₁₀ , that is, I ₁₀ during the discharging period. Therefore, the charging period T1 and the discharging period T2 shown in FIG. 6 are expressed by the following equations (6) and (7): T1 = C _81a × (v ₂ −v _o73 ) / I ₁₀ (6) T2 = C _81a × (v ₂ −v ₃ ) / I ₁₀ (7) In the above equation, C _81a is the capacity of the capacitor 81a.

[0102] Furthermore, for simplicity of explanation, the reference voltage v _O72 constant voltage source 72 shown in FIG. 3 is generated, _v o72 -
When V _BE = v ₃ is set and v _o73 = v ₃ , each period T1 and T2 and the oscillation period T are expressed by the following equation (8).
And as shown in (9), T1 = T2 = C _81a × (v ₂ −v ₃ ) / I ₁₀ (8) T = 2 × C _81a × (v ₂ −v ₃ ) / I ₁₀ ·・ It becomes (9).

Here, in the above formulas (1) and (2), if R ₁₁ = R ₁₂ = R ₁₃ , then v ₂ = (2/3) × (V _cc -V _BE ) (10) ) v become _{3 = (1/3) × (V} cc -V BE) ··· (11).

Further, from the above equations (8) to (11) and equation (5), the periods T1 and T2 and the oscillation period T are as follows: T1 = T2 = C _81a × R1 / 3 ( 12) T = (2/3) × C _81a × R1 (13) In the above equations (12) and (13),
The fact that the V _BE term in equations (5), (10), and (11) could be eliminated is due to the insertion of transistor Q ₁₆ .

As described above, the optical signal demodulator according to this embodiment uses the bandpass filter 4 for discriminating a specific frequency from the received signal of the photodiode 1 and the output signal v _o4 of the bandpass filter 4 as a pulse signal. The integrating circuit 5 and the comparator 6 for converting into Further, in the optical signal demodulating device, the clock signal v _o8 is generated and the clock signal v _o8 is instructed to synchronize the clock signal v _o8 with the pulse signal v _o6 output from the comparator 6. an output change detecting circuit 7 for, from the pulse signal v _o6, counted the number of pulses in synchronism with the clock signal v _o8, when it exceeds a predetermined number, provided a digital counting circuit 9 for outputting a demodulated signal v _o is ing.

In the above configuration, the digital counting circuit 9 outputs the code signal v _o having a pulse width corresponding to the number of pulses when receiving a fixed number of pulses synchronized with the clock signal v _o8 . _Further , when a pulse which is not synchronized with the clock signal v _o8 is received or when the number of pulses is less than a predetermined number, the digital counting circuit 9 does not output the demodulated signal v _o . As a result, in the optical signal demodulation device, it is possible to improve the separation characteristic between the signal and the noise.

Further, the pulse width of the demodulated signal v _o is determined by the number of pulses synchronized with the clock signal v _o8 . Therefore, as in the case of envelope detection using a conventional integrating circuit, variation in the code signal due to variation in resistance and capacitance forming the integrating circuit does not occur, and the pulse width of the demodulated code signal is set to the above pulse width. It can always be constant for numbers. As a result, the pulse width of the demodulated signal becomes the same as that of the code signal before being modulated by the optical signal transmitter (not shown), and the waveform distortion at the time of demodulation can be reduced.

Further, the clock generating section 8 is provided with an oscillator 81 for generating a basic pulse of the clock signal v _o8 , and as shown in FIG. 2, the oscillator 81 has an RS for setting or resetting the output. A -FF circuit 81h is provided. Further, the output change detection circuit 7 is provided with a pulse signal v _o6 such as a rising _edge of the pulse signal v _o6.
Is detected, and the RS-FF circuit 81h is reset. The RS-FF circuit 81h is
Since it can be realized by the two NAND circuits 81f and 81g, it can be realized by a simple circuit without using a large-scale circuit. Therefore, the cost for manufacturing the optical signal demodulation device can be suppressed.

Further, the clock generator 8 comprises a frequency divider 82 for dividing the output of the oscillator 81 and a NAND circuit 83 for negating the logical product of the outputs of the oscillator 81 and the frequency divider 82. The frequency divider 82, like the oscillator 81, responds to an instruction from the output change detection circuit 7
It is reset when the output of the pulse signal v _o6 changes.

By the way, the frequency divider 82 according to the present embodiment.
4 is composed of a D-type flip-flop circuit as shown in FIG. 4, and inverts the output signal v _o82 at each falling edge. Therefore, if the D-type flip-flop stores 1 at the first falling time, as shown in FIG. 6 (f), the output signal v _{o82 of the} frequency divider 82.
Is a waveform obtained by inverting the desired waveform shown in FIG. As a result, as shown in (g) of FIG. 6, the clock signal v _o8 generated by the NAND circuit 83 becomes a signal whose phase is shifted by a half cycle from the desired signal.

However, in the output change detection circuit 7 according to this embodiment, the frequency divider 82 is reset every time the oscillator 81 is reset.
Is also resetting. As a result, the frequency divider 82 operates as shown in FIG.
(D) of the output signal v _o6 of the comparator 6
_Can reliably output the waveform v _o82 that goes high every time the _pulse rises. As a result, the clock generation unit 8
The circuit 83 outputs the output signal v _{081 of the} oscillator 81 shown in FIG. _6C and the output signal v ₀ of the frequency divider 82 shown in FIG. _6D .
_By taking the negation of the logical product with _o82 , as shown in (e) of FIG. 6, the pulse signal v shown in (a) of FIG.
_A clock signal v _o8 that falls at the center of _o6 can be generated.

Further, in the present embodiment, the frequency divider 82 is realized by a simple circuit such as a D-type flip-flop. Therefore, the cost for manufacturing the optical signal demodulation device can be suppressed.

In addition to the above configuration, in the present embodiment, FIG.
, The bandpass filter 4 and the oscillator 81
A constant current circuit 10 for supplying the same current is provided. The constant current circuit 10 supplies the bandpass filter 4 and the oscillator 81 with a constant current I ₁₀ adjusted by an external resistor R1 having a higher precision than a resistor generated in the integrated circuit.

As a result, the center frequency of the bandpass filter 4 and the oscillation frequency of the oscillator 81 can be accurately determined. Further, even if the resistance value varies slightly, the error is the same, so that the ratio of both frequencies can be made constant. Thereby, the pulse width distortion at the time of demodulation of the optical signal demodulation device can be further reduced.

Since the resistors for determining both frequencies are shared, the number of parts can be reduced as compared with the case where they are individually provided.

In the digital counting circuit 9 according to this embodiment, five stages of D-type flip-flops 91a to 91 are used.
Although the shift register unit 91 is formed of e,
The number of stages of the D-type flip-flops, that is, the number of clocks until the digital counting circuit 9 outputs the demodulated signal v _o is
It is not limited to this. For example, the number of stages may be one or two, or six or seven. By using at least one D-type flip-flop, the above effect can be obtained.

However, the number of D-type flip-flops is
It is desired to be set to 5 or more as in the present embodiment. When an optical signal demodulator is provided in an optical remote controller using infrared rays or the like, a fluorescent lamp is a major noise source. As shown in FIG. 8, when the light of a fluorescent lamp that generates impulse noise is received, the output signal v _o4 of the bandpass filter 4 and the output signal v of the integrating circuit 5 shown in FIG.
The _o5, changes as shown in FIG. 9, the period is larger output signal v _o4 than the output signal v _o5 will appear consecutively up to 4 times. As a result, the output voltage v _o6 of the comparator 6 shown in FIG. 1 changes from low level to high level four times due to the noise.

Further, as shown in FIG. 10, when the fluorescent lamp which is turned on at the normal commercial power source frequency is received, the output current I _{5a of the} transconductance amplifier 5a and the output current I _{5a of the} transconductance amplifier 5a in the integrating circuit 5 shown in FIG. 1 are received. , The current value I of the constant current source 5c
By adjusting the ratio with _5c , as shown in FIG. 11, the period when the output signal v _{o4 is} larger than the output signal v _o5 , that is, the number of pulses output from the comparator 6,
It can be set to less than 5.

In any case, the number of pulses generated by the comparator 6 due to the noise from the fluorescent lamp is
Less than 5 times. Therefore, as shown in FIG. 4, the shift register unit 9 is composed of five or more stages of D-type flip-flops.
It is possible to realize an optical signal demodulation device that does not malfunction with respect to fluorescent lamp noise by forming 1 and generating the output signal v _o only when five or more pulses come.

Further, the digital counting circuit 9 according to the present embodiment is provided with the D-type flip-flops 91a to 91e, but it is not limited to this. For example, a counter or the like may be used to count the number of pulses, and a timer or the like may output the demodulated signal v _o having a pulse width corresponding to the number of pulses. Alternatively, the same operation may be performed by the computer executing a predetermined program. In the pulse signal v _o6 , the digital counting circuit 9
With the _{configuration} in which the number of pulses synchronized with the clock signal v _o8 is counted and demodulated to the code signal v _o having the pulse width corresponding to the number of pulses, the same effect as this embodiment can be obtained.

However, as in this embodiment, the demodulated signal v _o is generated according to the outputs of the shift register section 91 composed of the D-type flip-flops 91a to 91e and the D-type flip-flops 91a to 91e. When the output gate circuit 92 is provided, the digital counting circuit 9 can be realized by, for example, a D-type flip-flop and a basic logic gate such as a NAND circuit. As a result, it is possible to realize an optical signal demodulating device with high accuracy and little variation with a simple configuration.

[0121]

As described above, the optical signal demodulating device according to the first aspect of the present invention includes the clock signal generating means for generating the clock signal, and the clock signal generated by the clock signal generating means for detecting the light receiving element. When the number of pulses of the pulse signal synchronized with the clock signal and counting the number of pulses of the pulse signal synchronized with the clock signal exceeds the predetermined lower limit value. , Counting means for outputting a code signal having a pulse width corresponding to the number of pulses.

In the above configuration, the counting means outputs the code signal when the number of pulses is less than the lower limit value or when the light receiving element receives noise and a pulse signal which is not synchronized with the clock signal is generated. do not do. As a result, in the optical signal demodulation device, it is possible to improve the separation characteristic between noise and signal. Further, the counting means determines the pulse width of the code signal to be output based on the counted number of pulses. As a result, it is possible to reduce the waveform distortion during demodulation.

An optical signal demodulating device according to the invention of claim 2 is
As described above, in the configuration of the invention according to claim 1, the clock signal generation means includes an oscillator that generates a basic clock of the clock signal, and the oscillator includes:
A set-reset flip-flop circuit that resets the output in response to an instruction from the synchronization control means is provided.

Therefore, the clock signal generating means can be constructed without using a large-scale circuit. As a result, it is possible to reduce the cost for manufacturing the optical signal demodulation device.

An optical signal demodulating device according to the invention of claim 3 is
As described above, in the configuration of the present invention as set forth in claim 2, the clock signal generating means divides the output of the oscillator, and the frequency divider is reset in response to an instruction from the synchronization control means. It is configured to include an output unit that generates a clock signal from the output of the oscillator and the output of the frequency divider.

Therefore, even when the frequency divider is used as the clock signal generating means, the phase difference between the pulse signal and the clock signal can be maintained. Further, the frequency divider and the output section can be realized by a simple circuit such as a D-type flip-flop or a NAND circuit. As a result, it is possible to reduce the cost for manufacturing the optical signal demodulation device.

The optical signal demodulating device according to the invention of claim 4 is
As described above, in the configuration of the invention according to claim 1, 2 or 3, the external resistor for determining both the oscillation frequency of the clock signal generating means and the frequency discriminated by the discriminating means is provided. It is a composition.

Therefore, both frequencies can be determined with higher accuracy than in the case where it is determined by the resistance provided in the integrated circuit. As a result, it is possible to further reduce the pulse width distortion at the time of demodulation of the optical signal demodulator. In addition, since the external resistor is shared by the discriminating means and the clock signal generating means, it is possible to reduce the number of parts as compared with the case where they are individually provided.

The optical signal demodulating device according to the invention of claim 5 is
As described above, in the configuration of the invention according to claim 1, 2, 3, or 4, the lower limit value of the counting means is set to 5 or more.

In the above arrangement, the counting means does not output the code signal even if noise less than 5 times is input. Therefore, it is possible to realize an optical signal demodulating device that does not respond to the noise light emitted by the fluorescent lamp.

An optical signal demodulating device according to the invention of claim 6 is
As described above, in the structure of claim 5, the counting means is based on the shift register circuit including the D-type flip-flops having the number of stages corresponding to the lower limit value operated by the clock signal, and the output of the shift register circuit. And an output logic circuit that outputs a code signal.

In the above structure, the shift register circuit and the output logic circuit can be realized by a basic logic circuit such as a D-type flip-flop and a NAND circuit. As a result, there is an effect that an optical signal demodulating device with high accuracy and less variation can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention and is a circuit diagram showing a main configuration of an optical signal demodulating device.

FIG. 2 is a circuit diagram showing a main configuration of an oscillator in the optical signal demodulating device.

FIG. 3 is a circuit diagram showing a main configuration of an output change detection circuit in the optical signal demodulation device.

FIG. 4 is a circuit diagram showing a main part of a digital counting circuit in the optical signal demodulating device.

FIG. 5 is a timing chart showing an operation of each unit when an input signal of the output change detection circuit is generated in the optical signal demodulation device.

FIG. 6 is a timing chart showing operations of the output change detection circuit and the oscillation circuit.

FIG. 7 is a timing chart showing the operation of each unit during demodulation in the digital counting circuit.

FIG. 8 shows an example of noise input to the optical signal demodulation device, and is a waveform diagram showing an impulsive fluorescent lamp noise waveform.

9 is a waveform diagram showing waveforms of various parts of the optical signal demodulation device when the fluorescent lamp noise waveform shown in FIG. 8 is input.

FIG. 10 is a waveform chart showing an example of noise input to the optical signal demodulation device and showing a fluorescent lamp noise waveform using a commercial power supply.

11 is a waveform diagram showing waveforms of various parts of the optical signal demodulating device when the fluorescent lamp noise waveform shown in FIG. 10 is input.

FIG. 12 shows a conventional example and is a circuit diagram showing a main part of an optical signal demodulating device.

FIG. 13 is a timing chart showing the operation of each unit during demodulation in the conventional optical signal demodulation device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 photodiode (light receiving element) 4 band pass filter (discrimination means) 6 comparator (conversion means) 7 output change detection circuit (synchronization control means) 8 clock generation unit (clock signal generation means) 9 digital counting circuit (counting means) 81 Oscillator 81h Set-reset flip-flop 82 Frequency divider 83 NAND circuit (output section) 91 Shift register section (shift register circuit) 91a D-type flip-flop 92 Output gate circuit (output logic circuit) R1 External resistor

Claims (6)

[Claims] 1. A light receiving element for receiving an optical code signal modulated by a pulse of a specific frequency, a discrimination means for discriminating the specific frequency from a detection signal of the light receiving element, and a discrimination signal of the discrimination means as a pulse signal. An optical signal demodulating device having a converting means for converting into a clock signal, a clock signal generating means for generating a clock signal, a synchronization control means for synchronizing the clock signal generated by the clock signal generating means with the pulse signal, and the clock signal Counting means for counting the number of pulses of the pulse signal synchronized with the clock signal and outputting a code signal having a pulse width according to the number of pulses when the counted number of pulses exceeds a predetermined lower limit value. And an optical signal demodulating device. 2. The clock signal generating means comprises an oscillator for generating a basic clock of the clock signal,
2. The optical signal demodulating device according to claim 1, wherein the oscillator is provided with a set-reset flip-flop circuit that resets an output in response to an instruction from the synchronization control means. 3. The clock signal generation means divides the output of the oscillator and is reset in response to an instruction from the synchronization control means, the output of the oscillator and the output of the divider. The optical signal demodulating device according to claim 2, further comprising: an output unit that generates a clock signal. 4. An external resistor for determining both the oscillation frequency of the clock signal generating means and the frequency discriminated by the discriminating means.
2. The optical signal demodulating device according to 2 or 3. 5. The lower limit value of the counting means is set to 5 or more, 1, 2, 3, or 4.
The optical signal demodulating device described. 6. The counting means outputs a code signal based on the output of the shift register circuit, which comprises a D-type flip-flop having a number of stages corresponding to a lower limit value operated by the clock signal, and the output of the shift register circuit. An optical signal demodulator according to claim 5, further comprising an output logic circuit.