JPH09294093A - Equalization circuit for intra-station line termination board - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To realize a simple and miniaturized equalization circuit for an intra-station line termination board. A received signal from which noise is removed is AGC
It is normalized by (automatic gain control circuit) 31. The adder 32 changes the level of the output signal of the AGC 31 according to the feedback signal. The phase determination means 40 samples the output signal of the adder 32 by using the plurality of signals φ1 to φ8 whose phases are shifted by dividing the fixed oscillation frequency, and determines the rising edge of the output signal of the adder 32. Set the corresponding timing. The sampling means 60 samples the output signal of the adder 32 in synchronization with the set timing to generate reproduction data. On the other hand, BT equalizer 51 and D
The / A converter 52 synchronizes with the set timing,
A feedback signal corresponding to the sign of the reproduction data at that time is generated and given to the adder 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intra-station line which is provided at a reception point in a station and which generates reproduced data from a reception signal obtained by ping-pong transmission with a subscriber line terminating device (hereinafter referred to as DSU) or the like. The present invention relates to an equalizer circuit of a terminal board.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Sadayoshi Shimada, Ryoichi Komiya, Fumio Mano, Seiichi Yamano,
And Kiyomi Umozaki, "Multimedia Network Series Digital Access Method", published by Ohmsha, P84-85, P
100-103 FIG. 2 is a block diagram showing a main part of a conventional intra-station line termination board. The DSU 1 and the intra-station line termination board 10 are connected by a two-wire metallic cable 20. A plurality of bridge taps (BT) are provided in the middle of the two-wire metallic cable 20. The intra-station line termination board 10 is provided at the receiving point in the station, and includes a line automatic equalization circuit 11 and
The timing extraction circuit 12 and the identification reproduction circuit 13 are provided. The line automatic equalization circuit 11 is connected to the metallic cable 20, and the output side of the line automatic equalization circuit 11 is
It is connected to the timing extraction circuit 12 and the identification reproduction circuit 13. In the intra-station line termination board 10, the automatic line equalization circuit 11, the timing extraction circuit 12, and the identification reproduction circuit 13 perform shaping of waveform distortion of the received signal, timing extraction, and identification reproduction of data. Then, by using a circuit (not shown), the frame is synchronized and then multiplexed to form an interface with the exchange.

FIG. 3 is a block diagram showing the configuration of the timing extraction circuit shown in FIG. This timing extraction circuit 12
Is a digital phase-locked loop (hereinafter D
A PLL) is adopted and a pattern detection circuit 12 ₁ for detecting a pattern with respect to an output signal of the automatic line equalization circuit 11 is provided. The phase comparator 12 ₂ is connected to the output side of the pattern detection circuit 12 ₁ . The phase comparator 12 ₂ detects a phase shift between the fed back signal and the output signal of the pattern detection circuit 12 ₂ ,
Phase-advance signal generation circuit (advance phase) 12 using the result as a set signal
₃ or the delay signal generator circuit (slow phase) 12 ₄ . Lead signal generation circuit 12 ₃ and lag signal generation circuit 1
The 2 ₄ has a function of outputting each phase advance signal and the delayed phase signal at a timing of the set signal. The timing extraction circuit 12 is provided with a main oscillator 12 ₅ . The main oscillator 12 ₅ oscillates at a fixed oscillation frequency of, for example, 15.36 MHz, outputs two phases of 0 phase and π phase, and the two phases are one input terminal of each AND circuit 12 ₆ and 12 _7. This is the connection input to. Further, the phase advance signal generation circuit 12 ₃ is reset by the 0-phase output signal, and the delay phase signal generation circuit 12 ₄ is reset by the π-phase output signal. Each AND circuit 12 ₆ ,
The other input terminal of 12 ₇ has a phase advance signal generation circuit 12 ₃
A connection slow signal is inputted from the phase advance signal or delayed phase signal generating circuit 12 _4.

An OR circuit 12 ₈ is connected to the output side of each AND circuit 12 ₆ and 12 ₇ , and a frequency divider 12 ₉ is connected to the output side of the OR circuit 12 ₈ . Divider 12
_9, the output signal of the OR circuit 12 ₈ has the function of peripheral 48 minutes. The output signal of the frequency divider 12 ₉ is given to the phase comparator 12 ₂ as the feedback signal and also fed back to the pattern detection circuit 12 ₁ . The DPLL of the timing extraction circuit 12 has a free-running oscillation frequency of 320 KHz, but if a phase shift occurs between the pattern detected by the pattern detection circuit 12 ₁ and the output signal of the frequency divider 12 ₉ , phase comparison is performed. The detector 12 ₂ detects the deviation and gives a set signal to the advanced signal generation circuit 12 ₃ or the delayed signal generation circuit 12 ₄ . The advanced signal generation circuit 12 that has been set
₃ or the delayed phase signal generating circuit 12 _4, the phase advance signal or delayed phase signal is output. AND circuits 12 ₆ and 12 ₇
The OR circuit 12 ₈ changes the frequency of 15.36 MHz in cooperation with the advanced signal generation circuit 12 ₃ and the delayed signal generation circuit 12 _4, and supplies the frequency to the frequency divider 12 ₉ . That is, AN
The D circuits 12 ₆ and 12 ₇ and the OR circuit 12 ₈ delete the waveform when the comparison result by the phase comparator 12 ₂ indicates advance, and increase the waveform when the comparison result indicates delay. In this way, the timing extraction is performed, and the reproduction data is generated based on the timing extraction.

[0005]

However, the conventional intra-station line termination board has the following problems. In the intra-station line termination board of FIG. 2, for example, the line automatic equalization circuit is made to perform frequency domain equalization and time domain equalization in order to equalize line loss of 50 dB and bridge taps.
Also, in consideration of the influence of heterogeneous core wire connection and jitter in the metallic cable 20, the DPLL as shown in FIG.
Timing extraction circuit. With these, highly accurate equalization and reproduction can be performed, but when the line loss is small and the jitter is small, it can be said that the performance is excessive. Also,
Since the main oscillator 12 ₅ having a high oscillation frequency is used, L
There is a problem that it is difficult to realize SI and the circuit becomes complicated.

[0006]

In order to solve the above-mentioned problems, the present invention provides an intra-station line which is provided at a reception point in the station and which generates reproduced data of a reception signal obtained by ping-pong transmission with a subscriber side. The equalizer circuit of the terminal board is configured to include the following amplifying means, level changing means, oscillator, phase determining means, sampling means and equalizing means. The amplifying means amplifies and normalizes the level of the received signal from the subscriber, and the level changing means changes the level of the output signal of the amplifying means based on the feedback signal.
The oscillator has a function of oscillating at a fixed frequency. The phase determination means uses a plurality of phase detection signals whose fixed frequencies are frequency-divided and whose phases are shifted from each other, samples the output signal of the level changing means, and raises the output signal of the level changing means a plurality of times. It has a function of making a judgment and setting a timing corresponding to the judgment result. The sampling means has a function of sampling the output signal of the level changing means in synchronization with the set timing and generating the digital reproduction data corresponding thereto. The equalizing means is configured to generate a feedback signal according to the code of the reproduction data at that time in synchronization with the set timing.

According to the present invention, since the equalization circuit of the intra-station line terminal board is configured as described above, the received signal is amplified by the amplifying means and the amplification result is given to the level changing circuit. The output signal of the level changing means is sampled by the sampling means, and reproduced data corresponding to the received signal is generated. Here, the sampling timing in the sampling means is obtained by the phase determination means. The phase determination means uses a plurality of phase detection signals whose phases are shifted from each other by dividing the fixed oscillation frequency of the oscillator, determines the rise of the output signal of the level changing means a plurality of times, and sets the timing. This makes it possible to obtain proper timing that is resistant to the jitter of the received signal. On the other hand, the equalizer generates a feedback signal according to the code of the reproduced data in synchronization with the timing set by the phase determiner. The feedback signal is given to the level changing means, and the level of the output signal of the amplifying means is changed.
As a result, the influence of interference between the data in the received signal is removed. Therefore, the sampling means can generate the reproduction data in which the influence of the interference component is removed. Therefore, the above problem can be solved.

[0008]

1 is a block diagram showing a configuration of an equalizer circuit of an intra-station line terminating board showing an embodiment of the present invention. The equalization circuit of the intra-station line termination board is for generating reproduction data in ping-pong transmission with a DSU or the like,
The pre-filter 30 which receives a received signal from a DSU or the like and removes a component in the 640 kHz band is provided. An automatic gain control circuit (hereinafter referred to as AGC) 31 that is an amplification unit is connected to the pre-filter 30, and an adder 32 that is a level changing unit is connected to the output side of the AGC 31. The adder 32 is configured to change the level of the output signal of the AGC 31 based on the feedback signal. The equalizer circuit of FIG. 1 includes an oscillator 3 having a fixed oscillation frequency f of 2.56 MHz.
5, a phase determination means 40, an equalization means 50, and a sampling means 60 for outputting reproduction data are provided. The phase determination means 40 and the sampling means 60 are connected to the output side of the adder 32. Phase determination means 40
And the equalizing means 50 on the output side of the sampling means 60.
Is connected. The output signal of the phase determination means 40 is also connected to the sampling means 60.
The equalizing means 50 is configured to output a feedback signal to the adder 32. The phase determination means 40 has a plurality of signals φ1 to φ obtained by dividing the fixed oscillation frequency f of the oscillator 35.
8 is the input configuration.

The phase determining means 40 includes a timing selecting section 4
0A and the rising detection part B are provided. The rising detection section B samples the output signal of the adder 32 by using the eight phase detection signals φ1 to φ8 whose phases are shifted from each other by dividing the fixed oscillation frequency f, and outputs the rising edge of the output signal of the AGC 31. Has a function of sequentially determining. The timing selection unit 40A has a function of setting the timing by selecting the phase detection signals φ1 to φ8 from the determination result of the rising edge detection unit B. Equalizer 50
Is for generating a feedback signal according to the polarity of the reproduction data at that time in synchronization with the timing set by the timing selection unit 40A, and inputs the reproduction data and the timing output by the timing selection unit 40A. The BT equalizer 51 is provided. The output side of the BT equalizer 51 is connected to the digital / analog converter (D / A) 52, and the output side of the digital / analog converter 52 is connected to the adder 32.

FIG. 4 is a circuit diagram showing the phase determining means, the sampling means and their peripherals in FIG. Two drivers 41, 42 and O are provided on the input side of the phase determination means 40.
And an R circuit 43. These drivers 41,
42 and the OR circuit 43 are for setting the polarity of the output signal via the adder 32 of the AGC 31.
It constitutes a part of C31 or the adder 32. The output sides of the drivers 41 and 42 are connected to the input terminals of the 2-input OR circuit 43, respectively. The output side of the OR circuit 43 is input to the rising edge detection section 40B. On the other hand, a fixed frequency f of the oscillator 35 and a 320 KHz signal obtained by dividing the frequency by 8 are input to the phase shifter 45, and the phase shifter 45 shifts the phase of the divided signal to output a phase detection signal. This is a configuration for generating φ1 to φ8. Phase detection signals φ1 to φ8 are detected by the rising edge detection unit 40B.
And the timing selection unit 40A.

[0011] rise detection unit 40B is provided with eight determination circuits 46 _1, 46 ₂ ... 46 _8. Each of the determination circuits 46 _{1 to} 46 ₈ is composed of, for example, an AND circuit,
While inputting the phase detection signals φ1 to φ8 respectively,
An input signal via the OR circuit 43 is commonly input.
Then, each of the determination circuits 46 _{1 to} 46 ₈ is configured to perform the level determination of the input signal via the OR circuit 43. The output side of each of the determination circuits 46 _{1 to} 46 ₈ is connected to the timing selection unit 40.
It is connected to the phase determination unit 47 in A. Phase determination unit 4
The output side of 7 is connected to the selector 48. The selector 48 is configured to select and output the phase detection signals φ1 to φ8. On the other hand, the sampling means 60 is composed of, for example, a delay flip-flop 61. The data terminal D of the flip-flop 61 is a connection to which an input signal is applied via the OR circuit 43, and the clock terminal C
The output side of the selector 48 is connected to. The reproduction data is output from the output terminal Q of the flip-flop 61.

Next, the operation of the equalizer circuit of the intra-station line termination board of FIG. 1 will be described. A reception signal from the DSU via a metallic cable or the like is input to the pre-filter 30.
The pre-filter 30 removes the noise component in the 640 kHz band in the received signal. AGC31 is a pre-filter 3
At 0, the received signal from which the noise component is removed is amplified to the normalized level (1Vp-p). The output signal of AGC31 is
The level is changed via the adder 32. On the other hand, the phase shifter 45 generates eight phase detection signals φ1 to φ8 from the fixed oscillation frequency f of the oscillator 35 and the signal obtained by dividing the frequency by eight. The phase detection signals φ1 to φ8 are applied in parallel to the determination circuits 46 _{1 to} 46 ₈ , respectively. Each decision circuit 46 ₁ to 46 ₈ is a synchronized sampling phase detection signal Fai1～fai8, determines the level of the output signal of the adder 32. That is, the sampling and the determination are performed at timings different in time. Each determination circuit 46 ₁ to 4
The determination result of 6 ₈ is sequentially sent to the phase determination unit 47 as a signal indicating the rising timing of the output signal of the adder 32.

FIG. 5 is a diagram for explaining the operation of the phase determining section 47 in FIG. The data shown in FIG.
2 is an output signal. Now, the output signal of the adder 32 is
When input as the data shown by the solid line, the signals φ2 to
Each determination circuit 46 that performs sampling determination in synchronization with φ5
_{2-46 5} output level becomes "1", the other output level is "0". The phase determination unit 47 includes each determination circuit 46.
Based on the differential of the output signal of _{1-46 8} obtains a rising differential results 1 of FIG. 5, estimates the timing of rises of the received signal. After the initial estimation is completed, the estimation is continuously performed in the following frequency division cycle. That is, the estimation is performed N times (for example, 3 times) in total. When there is jitter in the received signal at the time of performing the second estimation and the data indicated by the broken line is input from the adder 32, the determination circuits 46 _{3 to} 46 ₆ of the determination circuits 46 _{3 to} 46 ₆ that perform the determination with the signals φ3 to φ6 are performed. The output level becomes "1" and the other output levels become "0". In this case, the phase determination unit 47 estimates the rising timing of the received signal from the rising differential result 2 in FIG. However, the phase determination unit 47 makes a total of N estimations and takes the majority of the N estimation results. The final selected phase is determined based on the result of the majority decision, and the change point of the output signal of the adder 32 is determined. For example, when the majority result is the differential result 1 in FIG. 5, the phase determination unit 47 determines the phase of φ4 at a position shifted by two phases as the selected phase in order to obtain stable reproduction data, and the selection result To the selector 48. Selector 48
Selects the signal φ4 and supplies it to the flip-flop 61 and the BT equalizer 51. That is, the rising differential result 2 is canceled. From the above, the flip-flop 61 and the BT
The timing for the equalizer 51 will be set.

The flip-flop 61 takes in the output signal of the adder 32 in synchronization with the signal φ4 and sequentially outputs digital reproduction data. On the other hand, the BT equalizer 51 outputs the signal φ4.
The reproduced data output from the flip-flop 61 is fetched in synchronism with, and is applied to the digital / analog converter 52.
If the cable connecting the DSU and the intra-station line termination board is long or if there is reflection due to a bridge tap, interference will occur between the data in the received signal. This interference matches the sign of the immediately preceding data. Therefore, the digital / analog converter 52 generates analog data having a polarity opposite to that of the reproduced data that has been taken in. That is, the data corresponding to the amount of reverse interference is given to the adder 32. By changing the level by the adder 32, the influence of the interference amount becomes close to zero, and malfunction is prevented. As described above, in the present embodiment, the AGC 31 and the adder 3
2. Since the phase deciding means 40, the equalizing means 50, the sampling means 60, etc. are used to configure the equalizing circuit of the intra-station line termination board, even the oscillator 31 having a low natural oscillation frequency f is sufficiently practical. An equalization circuit can be realized. Therefore, unlike the configuration using the conventional DPLL, the circuit can be simplified and the size can be reduced. In addition, the oscillator 31
Since it can be incorporated into I, the cost of the entire intra-station line termination board can be reduced. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, the oscillator 31
The natural oscillation frequency f of is not limited to 2.56 MHz, and may be realized at another natural oscillation frequency. In this case, if the number of frequency divisions and the number of phase detection signals are also changed, optimum reproduction data can be obtained by the same operation as in the above embodiment.

[0015]

As described in detail above, according to the present invention, the amplification means for amplifying and normalizing the level of the received signal, the level changing means, and the oscillator oscillating at a fixed frequency are further provided. , A phase determination unit that sequentially determines the rising edge of the output signal of the level changing unit by using a plurality of phase detection signals that are out of phase, and the feedback signal is generated in synchronization with the phase determination unit. Equalizing means and sampling means for outputting reproduced data are provided. Therefore, even with an oscillator having a low natural oscillation frequency, a sufficiently practical equalizer circuit for an intra-station line termination board can be realized, and unlike the configuration using the conventional DPLL, the circuit can be simplified and downsized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an equalization circuit of an intra-station line termination board showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a conventional intra-station line termination board.

3 is a configuration block diagram showing a timing extraction circuit in FIG.

FIG. 4 is a circuit diagram showing a phase determination unit, a sampling unit and their peripherals in FIG.

5 is a diagram illustrating an operation of a phase determination unit 47 in FIG.

[Explanation of symbols]

 31 AGC (amplifying means) 32 adder (level converting means) 35 oscillator 40 phase determining means 40A timing selecting section 40B rising edge detecting section 50 equalizing means 51 BT converter 52 D / A converter 60 sampling means φ1 to φ8 phase detecting Signal

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Seiichi Yamano 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. An equalization circuit of an intra-station line termination board, which is provided at a reception point in a station and generates reproduction data of a reception signal obtained by ping-pong transmission with a subscriber, Amplification means for amplifying and normalizing the level; level changing means for changing the level of the output signal of the amplification means based on a feedback signal; oscillator for oscillating at a fixed frequency; Using a plurality of phase detection signals that are out of phase, the output signal of the level changing means is sampled to determine the rising edge of the output signal of the level changing means a plurality of times, and the timing corresponding to the determination result is set. Judging means and sampling means for sampling the output signal of the level changing means in synchronization with the set timing to generate the digital reproduction data. An equalizing circuit for generating the feedback signal according to the code of the reproduction data at that time in synchronization with the set timing. .