JPH09311327A - Liquid crystal display - Google Patents
Liquid crystal displayInfo
- Publication number
- JPH09311327A JPH09311327A JP12553496A JP12553496A JPH09311327A JP H09311327 A JPH09311327 A JP H09311327A JP 12553496 A JP12553496 A JP 12553496A JP 12553496 A JP12553496 A JP 12553496A JP H09311327 A JPH09311327 A JP H09311327A
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- Prior art keywords
- substrate
- liquid crystal
- electrode
- crystal display
- display device
- Prior art date
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は液晶表示装置に係
り、特にアレイ基板上に形成された着色層に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a colored layer formed on an array substrate.
【0002】[0002]
【従来の技術】液晶表示装置は薄膜トランジスタ等のス
イッチング素子や画素電極等を含むアレイ基板と、共通
電極等を含む対向基板とに液晶が挟持されてなってい
る。従来、着色層は対向基板に形成されていたが、基板
の貼り合わせ精度のためのマージンによる開口率の低下
を防ぐため、アレイ基板上に着色層を形成する技術が開
発されている。2. Description of the Related Art In a liquid crystal display device, liquid crystal is sandwiched between an array substrate including switching elements such as thin film transistors and pixel electrodes and a counter substrate including common electrodes and the like. Conventionally, the colored layer has been formed on the counter substrate, but a technique for forming the colored layer on the array substrate has been developed in order to prevent a decrease in the aperture ratio due to a margin for the bonding accuracy of the substrates.
【0003】また、さらに高い開口率を得るために走査
線及び信号線等の配線と画素電極との層間に絶縁性の着
色層を形成し、配線と画素電極とを立体的に分離し、配
線に画素電極を重ねることで配線が遮光膜を兼ねる構造
が開発されている。Further, in order to obtain a higher aperture ratio, an insulating colored layer is formed between the wiring of the scanning line and the signal line and the pixel electrode, and the wiring and the pixel electrode are three-dimensionally separated, and the wiring is wired. A structure has been developed in which the wiring doubles as a light-shielding film by stacking the pixel electrode on.
【0004】図7に着色層の形成されたアレイ基板の平
面図を示す。図8は図7ののA−A’線による断面図で
ある。図8(A)は隣り合う画素領域の着色層が重なら
ずに形成されている。この場合、信号線上に着色層が形
成されない部分ができる。信号線は通常Al等の反射率
の高い金属が用いられることが多く、信号線を遮光膜と
して利用する場合にはコントラストの低下を招く原因に
なっていた。FIG. 7 shows a plan view of an array substrate on which a colored layer is formed. FIG. 8 is a sectional view taken along the line AA ′ of FIG. In FIG. 8A, the coloring layers in the adjacent pixel regions are formed without overlapping. In this case, there is a portion where the colored layer is not formed on the signal line. In general, a metal having a high reflectance such as Al is used for the signal line, which causes a reduction in contrast when the signal line is used as a light shielding film.
【0005】また、図8(B)は隣り合う画素領域の着
色層が重なって形成されている。この場合、信号線上は
全て着色層が覆っているので信号線の反射によるコント
ラストの低下は問題にならない。しかしながら、重ね合
わせ部で段差が生じ、配向処理を施す際に段差の後ろ側
が影になり、配向処理が行われず表示不良の原因となっ
ていた。Further, in FIG. 8B, the colored layers in the adjacent pixel regions are formed to overlap each other. In this case, since the signal line is entirely covered with the colored layer, the reduction in contrast due to the reflection of the signal line does not pose a problem. However, a step is generated in the overlapping portion, and when the alignment process is performed, the back side of the step is shaded, and the alignment process is not performed, which causes display failure.
【0006】[0006]
【発明が解決しようとする課題】本発明は上記問題点に
鑑みなされたもので、着色層の重なりにより発生する配
向処理の不良が表示に影響しない液晶表示装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device in which a defective alignment treatment caused by overlapping of colored layers does not affect the display.
【0007】[0007]
【課題を解決するための手段】本発明は、第1の基板
と、前記第1の基板上に形成された遮光部と、所定の画
素領域に対応して形成された着色層と、前記基板上に形
成された第1の電極と、前記第1の基板上に形成された
第1の配向膜と、を有する第1の電極基板と、第2の基
板と、前記第2の基板上に形成された第2の電極と、前
記第2の基板上に形成された第2の配向膜と、を有する
第2の電極基板と、前記第1の電極基板と前記第2の電
極基板とに挟持された液晶と、を有する液晶表示装置に
おいて、隣り合う画素領域で色の異なる着色層どうしは
前記遮光部上に対応する領域で幅を持って重なり合い、
重なり幅の中心が遮光部幅の中心より配向開始方向に近
い画素領域側にずれていることを特徴とする液晶表示装
置である。According to the present invention, there is provided a first substrate, a light-shielding portion formed on the first substrate, a colored layer formed corresponding to a predetermined pixel region, and the substrate. A first electrode substrate having a first electrode formed thereon and a first alignment film formed on the first substrate; a second substrate; and a second substrate on the second substrate. A second electrode substrate having the formed second electrode and a second alignment film formed on the second substrate; and the first electrode substrate and the second electrode substrate. In the liquid crystal display device having a sandwiched liquid crystal, colored layers having different colors in adjacent pixel regions are overlapped with a width in a corresponding region on the light shielding portion,
The liquid crystal display device is characterized in that the center of the overlapping width is displaced from the center of the width of the light shielding portion toward the pixel region closer to the alignment start direction.
【0008】[0008]
【発明の実施の形態】以下に本発明の実施の形態を図面
を用いて詳細に説明する。 (実施例1)図1は本実施例の液晶表示装置を示す平面
図である。図2(A)は図1におけるA−A’での断面
図、図2(B)は図1におけるB−B’での断面図であ
る。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (Embodiment 1) FIG. 1 is a plan view showing a liquid crystal display device of this embodiment. 2A is a sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a sectional view taken along the line BB ′ in FIG.
【0009】液晶表示装置の構成は、アレイ基板101
と対向基板102とに液晶130が挟持されてなる。ア
レイ基板101の構成は、基板10上に走査線20が形
成され、さらに走査線20と平行に補助容量線22が形
成されている。この上に基板全面にゲート絶縁膜50を
介して、走査線20と直交するように信号線23が形成
されている。そして、走査線20と信号線23との交点
部に薄膜トランジスタ(TFT:Thin Film
Transistor)が形成されている。この薄膜ト
ランジスタの構成は、走査線20から分岐されたゲート
電極21、ゲート電極21上のゲート絶縁膜50、さら
に半導体層30、エッチングストッパ層51が積層さ
れ、オーミックコンタクト層31、及びドレイン電極2
4、ソース電極25が積層されている。The structure of the liquid crystal display device is the array substrate 101.
The liquid crystal 130 is sandwiched between the counter substrate 102 and the counter substrate 102. In the configuration of the array substrate 101, the scanning line 20 is formed on the substrate 10, and the auxiliary capacitance line 22 is further formed in parallel with the scanning line 20. A signal line 23 is formed on the entire surface of the substrate via the gate insulating film 50 so as to be orthogonal to the scanning line 20. Then, a thin film transistor (TFT: Thin Film) is provided at the intersection of the scanning line 20 and the signal line 23.
Transistor) is formed. This thin film transistor has a structure in which a gate electrode 21 branched from the scanning line 20, a gate insulating film 50 on the gate electrode 21, a semiconductor layer 30, and an etching stopper layer 51 are stacked, an ohmic contact layer 31, and a drain electrode 2 are stacked.
4, the source electrode 25 is laminated.
【0010】そして、このTFT上を覆うように着色層
40が形成されている。この着色層40はR(赤)、G
(緑)、B(青)の3色が信号線23に平行にストライ
プ状に形成されており、信号線23上で隣り合う画素領
域の着色層40と重なっている。A colored layer 40 is formed so as to cover the TFT. This colored layer 40 is R (red), G
The three colors (green) and B (blue) are formed in stripes in parallel with the signal lines 23 and overlap the colored layers 40 in the pixel regions adjacent to each other on the signal lines 23.
【0011】そして、この着色層40上に画素電極27
が形成されており、着色層40の開口部を通して画素電
極27とソース電極25が接続されている。また、信号
線23と同層で補助容量線22上にゲート絶縁膜50を
介して補助電極26が形成されており、この補助電極2
6と画素電極27とも開口部を通して接続されている。The pixel electrode 27 is formed on the colored layer 40.
Are formed, and the pixel electrode 27 and the source electrode 25 are connected through the opening of the colored layer 40. An auxiliary electrode 26 is formed on the auxiliary capacitance line 22 in the same layer as the signal line 23 with a gate insulating film 50 interposed therebetween.
6 and the pixel electrode 27 are also connected through the opening.
【0012】そして全面に配向膜111が形成され、ア
レイ基板101となる。また、対向基板102は基板1
1の一主面上に対向電極12と配向膜112が全面に形
成されてなる。Then, an alignment film 111 is formed on the entire surface to form the array substrate 101. The counter substrate 102 is the substrate 1
The counter electrode 12 and the alignment film 112 are formed on the entire main surface of the first electrode 1.
【0013】次に製造工程を追って順に説明する。ま
ず、アレイ基板101から説明する。ガラスからなる基
板10の一主面上に例えばタンタルをスパッタ法により
300nm成膜した後、所定形状にパターニングして走
査線20、走査線の一部であるゲート電極21、及び補
助容量線22を形成する。Next, the manufacturing steps will be sequentially described. First, the array substrate 101 will be described. For example, tantalum is deposited to a thickness of 300 nm on one main surface of the substrate 10 made of glass by a sputtering method, and then patterned into a predetermined shape to form the scanning line 20, the gate electrode 21 which is a part of the scanning line, and the auxiliary capacitance line 22. Form.
【0014】次にゲート絶縁膜50となる酸化シリコン
を350nm、半導体層30となるa−Si層を50n
m、エッチングストッパ層51となる窒化シリコンを1
50nmをそれぞれプラズマCVD法で基板全体に被覆
する。その後、窒化シリコンのみをまずパターニング
し、エッチングストッパ層51を形成する。そして、オ
ーミックコンタクト層31となるn+型a−Si層を5
0nm被膜し、a−Si層と共にパターニングして半導
体層30、及びオーミックコンタクト層31を形成す
る。そして、例えばアルミニウムをスパッタ法で500
nm被膜し、パターニングして信号線23、ドレイン電
極24、ソース電極25、補助電極26をそれぞれ形成
する。本実施例では信号線23の幅は10μm程度であ
る。Next, 350 nm of silicon oxide that becomes the gate insulating film 50 and 50 n of a-Si layer that becomes the semiconductor layer 30 are formed.
m, silicon nitride to be the etching stopper layer 51 is 1
50 nm is coated on the entire substrate by the plasma CVD method. After that, only silicon nitride is first patterned to form the etching stopper layer 51. Then, the n + -type a-Si layer to be the ohmic contact layer 31 is formed to 5
The semiconductor layer 30 and the ohmic contact layer 31 are formed by film-forming with a thickness of 0 nm and patterning together with the a-Si layer. Then, for example, aluminum is sputtered 500 times.
Then, the signal line 23, the drain electrode 24, the source electrode 25, and the auxiliary electrode 26 are formed. In this embodiment, the width of the signal line 23 is about 10 μm.
【0015】次にアクリル樹脂からなる1.5μmの着
色層40を全面に塗布しフォトエッチングにより所定の
形状に、本実施例においてはR、G、Bの順番で順次形
成する。Next, a 1.5 μm colored layer 40 made of acrylic resin is applied to the entire surface and photo-etched to form a predetermined shape in the order of R, G and B in this embodiment.
【0016】このとき、着色層40を信号線23上で重
ね合わせて形成することにより信号線23の反射を防ぐ
ことができ、コントラストの低下を防ぐ効果がある。た
だし、着色層40を重ね合わせることで段差が生じ、後
に配向処理を施したときにこの段差による影の領域がで
きてしまい配向不良を起こすことがある。従ってこの影
の領域を信号線23の線幅内に納めることで表示に悪影
響を与えないようにする。本実施例では図2(A)に示
すように、重なり合う部分が配線幅の中心よりも左側に
ずれて形成されている。この場合、左側にずれていると
いうのは、図1に示した配向方向が左上側から行われて
いるためである。ただし、本実施例は重なり部分が配線
幅の中心から完全に配向開始方向に近い側(左側)に入
っているが、重なり部分が配線幅の中心から出ていて
も、重なり幅の中心と配線幅の中心と位置を比較して、
重なり幅の中心が配向開始方向に近い側にずれていれば
よい。At this time, by overlapping the colored layer 40 on the signal line 23, the reflection of the signal line 23 can be prevented and the contrast can be prevented from lowering. However, when the colored layers 40 are overlapped with each other, a step is generated, and when the alignment process is performed later, a shadow region is formed due to the step, which may cause alignment failure. Therefore, by placing the shadow area within the line width of the signal line 23, the display is not adversely affected. In this embodiment, as shown in FIG. 2A, the overlapping portion is formed so as to be shifted to the left of the center of the wiring width. In this case, the shift to the left is because the alignment direction shown in FIG. 1 is performed from the upper left side. However, in the present embodiment, the overlapping portion is located on the side (left side) completely close to the alignment start direction from the center of the wiring width, but even if the overlapping portion is out of the center of the wiring width, Compare the center of the width and the position,
It suffices if the center of the overlapping width is displaced toward the side closer to the alignment start direction.
【0017】次に、各々の着色層40には画素電極27
とソース電極25、及び画素電極27と補助電極26を
接続するための開口部60を形成する。そして、たとえ
ばITO(Indium Tin Oxide)をスパ
ッタ法により100nm被膜し、パターニングして画素
電極27を形成する。本実施例では、画素電極27は信
号線23及び走査線20と重ね合わせることにより開口
部を配線で規定しており、配線が遮光膜を兼ねる構造と
なっている。Next, each colored layer 40 has a pixel electrode 27.
An opening 60 for connecting the source electrode 25 and the pixel electrode 27 to the auxiliary electrode 26 is formed. Then, for example, ITO (Indium Tin Oxide) is coated to a thickness of 100 nm by a sputtering method and patterned to form the pixel electrode 27. In this embodiment, the pixel electrode 27 defines the opening by wiring by overlapping with the signal line 23 and the scanning line 20, and the wiring also serves as a light shielding film.
【0018】着色層40は画素電極と信号線23、走査
線20との重なり部分に形成される寄生容量が表示に影
響を与えないように、誘電率と厚さとの関係を決めるよ
うにする。The coloring layer 40 determines the relationship between the dielectric constant and the thickness so that the parasitic capacitance formed in the overlapping portion of the pixel electrode, the signal line 23 and the scanning line 20 does not affect the display.
【0019】最後に、全面に低温キュア型のポリイミド
からなる配向膜111を形成する。そして、この配向膜
111の表面を所定方向に布等で擦ることにより配向処
理がなされる。Finally, an alignment film 111 made of low temperature cure type polyimide is formed on the entire surface. Then, the surface of the alignment film 111 is rubbed in a predetermined direction with a cloth or the like to perform the alignment treatment.
【0020】このようにして所望のアレイ基板101を
得ることができる。次に対向基板102について説明す
る。ガラスからなる基板11の一主面上に例えばITO
からなる対向電極12を形成し、さらにアレイ基板10
1と同様の配向膜112を形成する。そして、この配向
膜112をアレイ基板101の配向膜111になされた
配向方向と90度ずれるような配向方向で配向処理を施
す。こうして対向基板102が得られる。In this way, the desired array substrate 101 can be obtained. Next, the counter substrate 102 will be described. For example, ITO is formed on one main surface of the substrate 11 made of glass.
And the array substrate 10 is formed.
An alignment film 112 similar to that of No. 1 is formed. Then, the alignment film 112 is subjected to an alignment treatment in an alignment direction that is deviated from the alignment direction of the alignment film 111 of the array substrate 101 by 90 degrees. In this way, the counter substrate 102 is obtained.
【0021】そして、アレイ基板101と対向基板10
2とをそれぞれの配向膜が形成された面を対向させるよ
うに配置し、注入口を除いてシール材により貼り合わせ
る。さらにこの間隙に注入口から液晶130を注入し、
注入口を封止する。Then, the array substrate 101 and the counter substrate 10
2 and 2 are arranged so that the surfaces on which the respective alignment films are formed face each other, and are bonded together by a sealing material except for the injection port. Further, the liquid crystal 130 is injected into the gap from the injection port,
Seal the inlet.
【0022】そして、アレイ基板101、対向基板10
2のそれぞれ外側の面に偏光板121、122を被着す
る。このときアレイ基板101の偏光板121と対向基
板102の偏光板122との偏光軸が90度ずれるよう
に配置する。Then, the array substrate 101 and the counter substrate 10
Polarizing plates 121 and 122 are attached to the outer surface of each of the two. At this time, the polarization axes of the polarizing plate 121 of the array substrate 101 and the polarizing plate 122 of the counter substrate 102 are displaced by 90 degrees.
【0023】そして、アレイ基板101側にバックライ
トを配設して、液晶表示装置を得る。 (実施例2)図3は本実施例の液晶表示装置の一画素分
の平面図であり、図4は図3におけるA−A’での断面
図である。Then, a backlight is arranged on the array substrate 101 side to obtain a liquid crystal display device. (Embodiment 2) FIG. 3 is a plan view of one pixel of the liquid crystal display device of this embodiment, and FIG. 4 is a sectional view taken along the line AA 'in FIG.
【0024】本実施例の構造は実施例1のように画素電
極27が走査線20及び信号線23に重ならないパター
ンである。画素電極27と信号線23との間隔は、補助
容量線22と一体となったシールド電極22aにより遮
光する。The structure of this embodiment is a pattern in which the pixel electrodes 27 do not overlap the scanning lines 20 and the signal lines 23 as in the first embodiment. The gap between the pixel electrode 27 and the signal line 23 is shielded by the shield electrode 22a integrated with the auxiliary capacitance line 22.
【0025】また、画素電極27と走査線20との間隔
は、対向基板102上またはアレイ基板101上に設け
られたストライプ状の遮光膜41により遮光する。そし
て本実施例の場合、シールド電極22a上で隣り合う着
色層40が重なり合っている。そして、重なり部分はシ
ールド電極の幅の中心よりも配向開始方向に近い画素領
域側に形成されている。その他の構成は実施例1と変わ
らない。The distance between the pixel electrode 27 and the scanning line 20 is shielded by a stripe-shaped light shielding film 41 provided on the counter substrate 102 or the array substrate 101. In the case of the present embodiment, the adjacent colored layers 40 are overlapped on the shield electrode 22a. The overlapping portion is formed on the pixel region side closer to the alignment start direction than the center of the width of the shield electrode. Other configurations are the same as those in the first embodiment.
【0026】本実施例によれば、走査線20、信号線2
3と画素電極27とが重なっておらず寄生容量の心配が
ないので、着色層40の誘電率や厚さを考慮することな
く、適宜、所望の特性に合う材料や厚さで形成すること
ができる。 (実施例3)本実施例は隣り合う画素領域の着色層40
どうしの重なり部分に、さらに残りの一色の着色層40
を島状に設けて柱状スペーサを形成する構造である。According to this embodiment, the scanning line 20 and the signal line 2
3 and the pixel electrode 27 do not overlap with each other and there is no fear of parasitic capacitance. Therefore, the coloring layer 40 may be formed of a material and a thickness suitable for desired characteristics without considering the dielectric constant and the thickness of the coloring layer 40. it can. (Embodiment 3) In this embodiment, the coloring layers 40 in the adjacent pixel regions are used.
The remaining colored layer 40 of one color is further formed on the overlapping portion.
Is provided in an island shape to form a columnar spacer.
【0027】例えば、R、G、Bの順で着色層を形成す
る場合、Rの画素領域とGの画素領域とが隣接している
部分では、RとGとを重ねた後にBを形成する工程でこ
の部分にもBを島状に形成する。また、Gの画素領域と
Bの画素領域とが隣接している部分では、最初にRを形
成する工程でこの部分にRを島状に形成し、その後、
G、Bの順でこの部分に重ね合わせていく。また、Rの
画素領域とBの画素領域とが隣接している部分では、R
を形成した後、Gを形成する工程でこの部分にGを島状
に形成し、最後にBを重ね合わせる。For example, when the colored layers are formed in the order of R, G, and B, B is formed after R and G are overlapped in a portion where the R pixel region and the G pixel region are adjacent to each other. In the process, B is also formed in an island shape in this portion. Further, in the portion where the G pixel region and the B pixel region are adjacent to each other, R is formed into an island shape in this portion in the step of first forming R, and thereafter,
Overlap this part in the order of G and B. Further, in a portion where the R pixel region and the B pixel region are adjacent to each other, R
After forming, G is formed in an island shape in this portion in the step of forming G, and finally B is overlapped.
【0028】本実施例の場合にも、実施例1、2と同様
に3層の重なり幅の中心が、配線幅の中心よりも配向開
始方向に近い画素領域側にずれて形成されている。ま
た、上記実施例はいずれも逆スタガ型であるが、本発明
はこのほかにも、スタガ型、コプラナ型等、様々な変形
例が考えられる。Also in the case of this embodiment, as in the first and second embodiments, the center of the overlapping width of the three layers is formed so as to be shifted to the pixel region side closer to the alignment start direction than the center of the wiring width. Further, although the above-mentioned embodiments are all of the inverted stagger type, the present invention can be modified in various ways such as a stagger type and a coplanar type.
【0029】[0029]
【発明の効果】本発明によれば、隣接する画素領域の着
色層が配線上で重なり合っており、その重なり部分が配
線幅の中心より配向開始方向にずれて形成されているの
で重なりの段差による配向不良の領域が表示領域にまで
及ばないようにすることができる。According to the present invention, the colored layers in the adjacent pixel regions overlap each other on the wiring, and the overlapping portion is formed deviating from the center of the wiring width in the alignment start direction, so that there is a step difference in the overlapping. It is possible to prevent the poorly oriented region from reaching the display region.
【図1】本発明の実施例1における液晶表示装置の一画
素分を示す平面図である。FIG. 1 is a plan view showing one pixel of a liquid crystal display device according to a first embodiment of the present invention.
【図2】(A)は図1におけるA−A’での断面図であ
り、(B)は図1におけるB−B’での断面図である。2A is a sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a sectional view taken along the line BB ′ in FIG.
【図3】本発明の実施例2における液晶表示装置の一画
素分を示す平面図である。FIG. 3 is a plan view showing one pixel of a liquid crystal display device according to a second embodiment of the present invention.
【図4】図3におけるA−A’での断面図である。FIG. 4 is a cross-sectional view taken along the line A-A ′ in FIG.
【図5】本発明の実施例3における液晶表示装置の一画
素分を示す平面図である。FIG. 5 is a plan view showing one pixel of a liquid crystal display device according to a third embodiment of the present invention.
【図6】図5におけるA−A’での断面図である。6 is a cross-sectional view taken along the line A-A ′ in FIG.
【図7】従来の液晶表示装置の一画素分を示す平面図で
ある。FIG. 7 is a plan view showing one pixel of a conventional liquid crystal display device.
【図8】(A)、(B)はともに図7におけるA−A’
での断面の例である。8A and 8B are both AA ′ in FIG.
It is an example of a section in.
10、11基板 20走査線 22補助容量線 22aシールド電極 23信号線 27画素電極 40着色層 101アレイ基板 102対向基板 130液晶 10, 11 substrate 20 scanning line 22 auxiliary capacitance line 22a shield electrode 23 signal line 27 pixel electrode 40 colored layer 101 array substrate 102 counter substrate 130 liquid crystal
Claims (7)
された遮光部と、所定の画素領域に対応して形成された
着色層と、前記基板上に形成された第1の電極と、前記
第1の基板上に形成された第1の配向膜と、を有する第
1の電極基板と、 第2の基板と、前記第2の基板上に形成された第2の電
極と、前記第2の基板上に形成された第2の配向膜と、
を有する第2の電極基板と、 前記第1の電極基板と前記第2の電極基板とに挟持され
た液晶と、を有する液晶表示装置において、 隣り合う画素領域で色の異なる着色層どうしは前記遮光
部上に対応する領域で幅を持って重なり合い、重なり幅
の中心が遮光部幅の中心より配向開始方向に近い画素領
域側にずれていることを特徴とする液晶表示装置。1. A first substrate, a light-shielding portion formed on the first substrate, a colored layer formed corresponding to a predetermined pixel region, and a first substrate formed on the substrate. A first electrode substrate having an electrode and a first alignment film formed on the first substrate; a second substrate; and a second electrode formed on the second substrate. A second alignment film formed on the second substrate,
In a liquid crystal display device having a second electrode substrate having a liquid crystal sandwiched between the first electrode substrate and the second electrode substrate, the colored layers having different colors in adjacent pixel regions are A liquid crystal display device, characterized in that they overlap each other with a width in a corresponding region on a light-shielding portion, and the center of the overlapping width is displaced from the center of the width of the light-shielding portion toward the pixel region closer to the alignment start direction.
前記遮光部幅の中心より配向開始方向に近い画素領域側
に形成されていることを特徴とする請求項1記載の液晶
表示装置。2. The liquid crystal display device according to claim 1, wherein the overlapping portion of the colored layers having different colors is formed on the pixel region side closer to the alignment start direction than the center of the width of the light shielding portion.
する請求項1または2いずれか記載の液晶表示装置。3. The liquid crystal display device according to claim 1, wherein the light shielding portion is made of metal.
上に平行に形成された複数の走査線と、前記走査線と絶
縁膜を介して直交するように平行に形成された信号線
と、前記走査線と前記信号線との交点部近傍に形成され
た薄膜トランジスタと、前記薄膜トランジスタに接続さ
れた画素電極と、を有し、 前記走査線と前記信号線とが遮光部となることを特徴と
する請求項1、2または3いずれか記載の液晶表示装
置。4. The first electrode substrate has a plurality of scanning lines formed in parallel on the first substrate and a signal formed in parallel to the scanning lines via an insulating film. A line, a thin film transistor formed in the vicinity of an intersection of the scanning line and the signal line, and a pixel electrode connected to the thin film transistor, wherein the scanning line and the signal line serve as a light-shielding portion. The liquid crystal display device according to claim 1, 2, or 3.
上に平行に形成された複数の走査線と、補助容量線と、
前記補助容量線から延在するシールド電極と、前記走査
線と絶縁膜を介して直交するように平行に形成された信
号線と、前記走査線と前記信号線との交点部近傍に形成
された薄膜トランジスタと、前記薄膜トランジスタに接
続された画素電極と、を有し、前記シールド電極が前記
遮光部の一部であることを特徴とする請求項1、2また
は3いずれか記載の液晶表示装置。5. The first electrode substrate includes a plurality of scanning lines formed in parallel on the first substrate, an auxiliary capacitance line, and
A shield electrode extending from the auxiliary capacitance line, a signal line formed in parallel with the scanning line through an insulating film, and a signal line formed in the vicinity of an intersection of the scanning line and the signal line The liquid crystal display device according to claim 1, further comprising a thin film transistor and a pixel electrode connected to the thin film transistor, wherein the shield electrode is a part of the light shielding portion.
板と前記第2の電極基板との間隔を保つスペーサを兼ね
ることを特徴とする請求項1または2いずれか記載の液
晶表示装置。6. The liquid crystal display device according to claim 1, wherein the overlapping portion of the colored layers also serves as a spacer for keeping a distance between the first electrode substrate and the second electrode substrate.
た領域を持つことを特徴とする請求項6記載の液晶表示
装置。7. The liquid crystal display device according to claim 6, wherein the overlapping portion of the colored layers has a region in which three or more layers are laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12553496A JP4011645B2 (en) | 1996-05-21 | 1996-05-21 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12553496A JP4011645B2 (en) | 1996-05-21 | 1996-05-21 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09311327A true JPH09311327A (en) | 1997-12-02 |
| JP4011645B2 JP4011645B2 (en) | 2007-11-21 |
Family
ID=14912578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12553496A Expired - Fee Related JP4011645B2 (en) | 1996-05-21 | 1996-05-21 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4011645B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005249863A (en) * | 2004-03-01 | 2005-09-15 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display panel |
| KR100731025B1 (en) * | 2000-10-25 | 2007-06-22 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display panel and its manufacturing method |
| KR100806801B1 (en) * | 2000-12-29 | 2008-02-27 | 엘지.필립스 엘시디 주식회사 | Array substrate for liquid crystal display device and manufacturing method thereof |
| KR100884541B1 (en) * | 2002-12-10 | 2009-02-18 | 엘지디스플레이 주식회사 | LCD and its manufacturing method |
| JP2009134212A (en) * | 2007-12-03 | 2009-06-18 | Epson Imaging Devices Corp | Liquid crystal display device |
| KR100956342B1 (en) * | 2003-06-09 | 2010-05-06 | 삼성전자주식회사 | Thin film transistor substrate |
| JP2011002617A (en) * | 2009-06-18 | 2011-01-06 | Hitachi Displays Ltd | Liquid crystal display device |
-
1996
- 1996-05-21 JP JP12553496A patent/JP4011645B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100731025B1 (en) * | 2000-10-25 | 2007-06-22 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display panel and its manufacturing method |
| KR100806801B1 (en) * | 2000-12-29 | 2008-02-27 | 엘지.필립스 엘시디 주식회사 | Array substrate for liquid crystal display device and manufacturing method thereof |
| KR100884541B1 (en) * | 2002-12-10 | 2009-02-18 | 엘지디스플레이 주식회사 | LCD and its manufacturing method |
| KR100956342B1 (en) * | 2003-06-09 | 2010-05-06 | 삼성전자주식회사 | Thin film transistor substrate |
| JP2005249863A (en) * | 2004-03-01 | 2005-09-15 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display panel |
| JP2009134212A (en) * | 2007-12-03 | 2009-06-18 | Epson Imaging Devices Corp | Liquid crystal display device |
| JP2011002617A (en) * | 2009-06-18 | 2011-01-06 | Hitachi Displays Ltd | Liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4011645B2 (en) | 2007-11-21 |
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