JPH09312355A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor device which is easy to manufacture and replaces a BGA type semiconductor device is obtained. A plurality of leads (10) and a semiconductor chip (6)
The stage 20 on which 0 is mounted is arranged side by side at predetermined intervals. A terminal portion 12 is formed so as to project at a predetermined portion on the lower surface of the lead 10. The electrode of the semiconductor chip 60 and the terminal portion 14 on the upper surface of the lead are electrically connected by the wire 70. The top and side surfaces of the plurality of leads 10 and the stage 20
The insulating material 30 is continuously applied in layers on the upper and side surfaces of the. Then, the plurality of leads 10 and the stage 20 are coupled in series via the insulating material 30. At the same time, the semiconductor chip 60 is sealed inside the insulating material 30, and the terminal portion 12 on the lower surface of the lead is exposed between the insulating materials 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip built therein and a method of manufacturing the semiconductor device for forming the device.

[0002]

2. Description of the Related Art Conventionally, a B having a built-in semiconductor chip
There is a GA (Ball Grid Array) type semiconductor device. This semiconductor device is provided with a plurality of terminals for connecting electronic circuits arranged in a grid pattern on its lower surface.
The terminals are provided with substantially hemispherical solder bumps.

In this BGA type semiconductor device, a terminal on the lower surface of the semiconductor device is mounted on a board for mounting the semiconductor device by using solder bumps formed on the terminal (hereinafter referred to as a board).
It can be connected by soldering to the terminal portion of the electronic circuit formed on the surface. Then, the semiconductor device can be surface-mounted on the board.

[0004]

However, the above B
When manufacturing a GA type semiconductor device, a through hole is formed in a substrate for mounting a semiconductor chip, and a plurality of conductor layers are formed on the inner peripheral surface of the hole by an electroless plating method and an electrolytic plating method. It is necessary to electrically connect the circuit pattern formed on the upper surface of the substrate to the terminals formed on the lower surface of the substrate through the conductor layer, which requires a great deal of labor and time. .

The present invention has been made in view of the above problems, and provides a semiconductor device which can be easily manufactured in place of a BGA type semiconductor device, and a method of manufacturing the semiconductor device for forming the device. The purpose is to do.

[0006]

In order to achieve the above object, the first semiconductor device of the present invention is such that a plurality of leads and a stage on which a semiconductor chip is mounted are arranged side by side at predetermined intervals. A terminal portion is formed so as to project at a predetermined portion of the lower surface of the lead, the electrode of the semiconductor chip and the terminal portion of the upper surface of the lead are electrically connected, and the upper surface and the side surface of the plurality of leads and the upper surface and the side surface of the stage. An insulating material is continuously deposited on the lead, and the plurality of leads and the stage are coupled in series through the insulating material, and the semiconductor chip is enclosed inside the insulating material to form a bottom surface of the lead. It is characterized in that the terminal portion is exposed between the insulating materials.

In a second semiconductor device of the present invention, a plurality of leads are arranged side by side at predetermined intervals, a terminal portion is formed at a predetermined portion of the lower surface of the lead, and a semiconductor chip is arranged above the leads. Then, the electrodes of the chip are electrically connected to the terminals on the upper surface of the leads, and the insulating material is continuously applied to the upper surfaces and the side surfaces of the plurality of leads. The leads are connected in series, the semiconductor chip is enclosed in the insulating material, and the terminal portion of the lower surface of the lead is exposed between the insulating materials.

In the first or second semiconductor device, the terminal portion on the upper surface of the lead and the terminal portion on the lower surface of the lead are electrically connected in series via the lead.

Therefore, a through hole is formed in an insulating material corresponding to a substrate, and a conductor layer is formed a plurality of times on the inner peripheral surface of the hole by electroless plating and electrolytic plating. It is possible to eliminate the need to electrically connect the terminal portion on the upper surface of the lead and the terminal portion on the lower surface of the lead via the.

Further, between the plurality of leads, or in addition thereto, the leads and the stage can be electrically insulated by an insulating material interposed therebetween.

Also, the terminal portion projectingly formed on a predetermined portion of the lower surface of the lead, which is exposed between the insulating materials, is soldered to the terminal portion of the electronic circuit formed on the surface of the board. By connecting, the semiconductor device can be surface-mounted on the board.

In this case, the terminal portion projectingly formed on the lower surface of the lead can be used as a standoff to float the lower surface of the semiconductor device by the height of the terminal portion projectingly formed on the lower surface of the lead above the board surface. it can.

Further, since the semiconductor chip is sealed inside the insulating material, it is possible to prevent the semiconductor chip from malfunctioning due to dust and moisture adhering to the semiconductor chip.

In the first or second semiconductor device of the present invention, it is preferable that the terminal portion on the upper surface of the lead or the upper surface of the stage is plated with bonding structure.

In this semiconductor device, a wire or the like for electrically connecting the electrode of the semiconductor chip to the lead is easily and surely bonded to the terminal portion on the upper surface of the lead plated for bonding. The electrodes of the semiconductor chip can be easily and reliably flip-chip bonded. Alternatively, in addition to this, a semiconductor chip can be easily and surely bonded to the upper surface of the stage plated for bonding.

In the first or second semiconductor device of the present invention, it is preferable that a solder bump is formed on the lower surface of the stage in addition to the terminal portion formed on the lower surface of the lead. There is.

In this semiconductor device, the solder bump formed on the terminal portion on the lower surface of the lead is used to easily and surely solder the terminal portion on the lower surface of the lead to the terminal portion of the electronic circuit formed on the surface of the board. Can be attached and connected. Alternatively, in addition to this, the solder bumps formed on the lower surface of the stage can be used to easily and reliably solder the lower surface of the stage to the metallic stage joint portion formed on the board surface.

In the second semiconductor device of the present invention, it is preferable that the back surface of the semiconductor chip is exposed between the insulating materials and the heat spreader is attached to the back surface of the chip.

In this semiconductor device, the heat generated by the semiconductor chip can be efficiently dissipated to the outside of the semiconductor device through the heat spreader attached to the back surface of the chip.

The first semiconductor device manufacturing method of the present invention is
It is characterized by including the following steps. a. A predetermined portion of the upper surface of the metal plate is etched to form a contour blind groove in a predetermined pattern on the upper surface of the metal plate, and a plurality of lead forming portions and a stage forming portion separated by the contour blind groove are formed on the metal plate. Forming side by side. b. A step of bonding a semiconductor chip to the upper surface of the stage forming portion to electrically connect the electrode of the chip and the terminal portion on the upper surface of the lead forming portion. c. An insulating material is continuously deposited on the upper surfaces and side surfaces of the plurality of lead forming portions, the upper surface and side surfaces of the stage forming portion, and the inner side surface of the contour blind groove therebetween, and the insulating material is interposed therebetween. A step of connecting the plurality of lead forming portions and the stage forming portion in series and encapsulating the semiconductor chip inside the insulating material. d. By etching a predetermined portion of the lower surface of the metal plate,
Forming a contour groove on the lower surface portion of the metal plate directly below the contour blind groove,
The contour groove separates the lead forming portions and the lead forming portion from the stage forming portion to form a plurality of leads and the stage side by side at predetermined intervals. A step of exposing the insulating material in between and forming a terminal portion at a predetermined portion of the lower surface of the lead so as to project.

According to a second method of manufacturing a semiconductor device of the present invention,
It is characterized by including the following steps. a. A step of etching a predetermined portion of the upper surface of the metal plate to form a contour blind groove in a predetermined pattern on the upper surface of the metal plate, and forming a plurality of lead forming portions separated by the contour blind groove on the metal plate side by side. . b. A step of disposing a semiconductor chip above the lead forming portion and electrically connecting an electrode of the chip to a terminal portion on the upper surface of the lead forming portion. c. An insulating material is continuously applied to the upper surfaces and the side surfaces of the plurality of lead forming portions and the inner side surface of the contour blind groove between them, and the plurality of lead forming portions are formed through the insulating material. A step of encapsulating the semiconductor chip inside the insulating material while bonding them in series. d. By etching a predetermined portion of the lower surface of the metal plate,
Forming a contour groove on the lower surface portion of the metal plate directly below the contour blind groove,
The lead grooves are separated from each other by the contour groove to form a plurality of leads side by side at predetermined intervals, and the insulating material is exposed between the contour grooves to form a lower surface of the lead. A step of projecting and forming a terminal portion at a predetermined portion.

In this first or second method of manufacturing a semiconductor device, a predetermined portion of the upper and lower surfaces of a metal plate is etched to form a plurality of leads or, in addition, stages at predetermined intervals. Can be formed side by side. At the same time, the terminal portion can be formed so as to project at a predetermined portion on the lower surface of the lead.

Further, a plurality of leads and a stage formed by etching a predetermined portion of the upper and lower surfaces of the metal plate can be connected in series via an insulating material. With it
Between the plurality of leads, or in addition to that, between the lead and the stage, by the insulating material interposed between them,
Can be electrically isolated.

Further, the terminal portion on the upper surface of the lead can be electrically connected to the terminal portion formed on the lower surface of the lead through the lead. Then, a through hole is formed in the insulating material corresponding to the substrate, and a conductor layer is formed a plurality of times on the inner peripheral surface of the hole by using an electroless plating method and an electrolytic plating method. It is possible to eliminate the need to electrically connect the terminal portion on the upper surface of the lead to the terminal portion projectingly formed on the lower surface of the lead.

Further, the semiconductor chip can be sealed inside the insulating material to prevent dust and moisture from adhering to the semiconductor chip.

The method for manufacturing a first or second semiconductor device according to the present invention includes a step of plating the terminal portion on the upper surface of the lead forming portion or the upper surface of the stage forming portion with plating for bonding. It is suitable.

In the method of manufacturing the semiconductor device, the terminal portion on the upper surface of the lead plated for bonding is
A wire or the like for electrically connecting the electrode of the semiconductor chip to the lead can be easily and surely bonded, and the electrode of the semiconductor chip can be easily and surely flip-chip bonded. Alternatively, in addition to this, the semiconductor chip can be easily and surely bonded to the upper surface of the stage plated with bonding.

In the first or second method of manufacturing a semiconductor device of the present invention, it is preferable that the method includes a step of forming solder bumps on the lower surface of the stage, or in addition to the terminal portion projectingly formed on the lower surface of the lead. I am trying.

In this semiconductor device manufacturing method, the solder bumps formed on the terminal portions on the lower surface of the lead are used to easily and surely connect the terminal portion on the lower surface of the lead to the terminal portion of the electronic circuit formed on the board surface. A semiconductor device that can be connected by soldering can be formed. Alternatively, in addition to this, by using the solder bumps formed on the lower surface of the stage, it is possible to form a semiconductor device in which the lower surface of the stage can be easily and surely solder-connected to a metallic stage joint portion formed on the board surface.

The second method of manufacturing a semiconductor device of the present invention preferably includes the step of exposing the back surface of the semiconductor chip between insulating materials and applying a heat spreader to the back surface of the chip. .

In this method of manufacturing a semiconductor device, a semiconductor device capable of efficiently dissipating heat generated by a semiconductor chip to the outside of the semiconductor device through a heat spreader attached to the back surface of the chip is formed. it can.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 show a preferred embodiment of a first semiconductor device of the present invention, FIG. 1 is a sectional view thereof, and FIG.
Is a bottom view thereof. Hereinafter, the first semiconductor device will be described.

In the figure, reference numeral 10 is a strip-shaped lead, and a plurality of leads are arranged side by side.

Reference numeral 20 denotes a rectangular plate-shaped stage, which is arranged substantially at the center of the leads 10 arranged side by side.

The plurality of leads 10 and the stage 20 are arranged side by side in a plane at predetermined intervals. The plurality of leads 10 and the stage 20 are formed by using a metal plate made of copper, a copper alloy, an iron-nickel alloy, an iron-nickel-cobalt alloy, or the like.

On a predetermined portion of the lower surface of the lead 10, a terminal portion 12 for soldering connection to a terminal portion of an electronic circuit formed on the surface of the board is formed in a protruding shape. Then, as shown in FIG. 2, the terminal portions 12 projectingly formed on the lower surface of each of the leads 10 are arranged in a grid pattern in accordance with the arrangement of the terminal portions of the electronic circuit formed on the board surface. ing.

The terminal portion 14 on the upper surface of the lead is plated with silver plating 50 or the like. Similarly, the upper surface 22 of the stage is also plated 40 such as silver for bonding.

A semiconductor chip 60 is bonded to the upper surface 22 of the stage, which is plated with the bonding plating 40. Then, the semiconductor chip 6 is mounted on the stage 20.
0 is installed.

The electrodes of the semiconductor chip 60 and the terminal portions 14 on the upper surfaces of the leads, which are plated with the bonding plating 50, are electrically connected via the wires 70.

An insulating material 30 such as an epoxy resin or a polyimide resin is continuously layered on the top and side surfaces of the plurality of leads 10 and the top and side surfaces of the stage 20, which are arranged side by side at predetermined intervals. It is worn. Then, the plurality of leads 10 and the stage 20 are connected in series via the insulating material 30. Along with that, the insulating material 30
The semiconductor chip 60 and the wires 70 are enclosed inside. Then, dust and moisture are prevented from adhering to the semiconductor chip 60 and the wires 70.

Between a plurality of leads 10 and the leads 10
An insulating material 30 is interposed between the stage 20 and the stage 20, and the insulating material 30 electrically insulates between the leads 10 and between the lead 10 and the stage 20. .

The terminal portion 1 formed to project on the lower surface of the lead 10
2 is exposed between the insulating materials 30.

The stage 20 is formed to have the same height and thickness as the terminal portion 12 projectingly formed on the lower surface of the lead 10.
The stage 20 is formed in a structure such that the lower surface thereof can be connected by soldering to a metallic stage joining portion formed on the board surface.

The terminal portion 12 on the lower surface of the lead and the stage 20
Solder bumps 90 and 100 are formed on the lower surface of the.

The first semiconductor device shown in FIGS. 1 and 2 is
In the first semiconductor device configured as described above, the solder bumps 90 formed on the terminal portions 12 on the lower surface of the leads are used, and the terminal portions 12 on the lower surface of the leads are formed on the board surface. Can be soldered to the circuit terminal. Then, the first semiconductor device can be surface-mounted on the board.

At this time, the solder bumps 100 formed on the lower surface of the stage 20 can be used to solder the lower surface of the stage 20 to the metallic stage joint portion formed on the board surface. Then, the heat generated by the semiconductor chip 60 can be efficiently dissipated to the board through the stage 20.

A preferred embodiment of the first semiconductor device manufacturing method of the present invention, which is the first semiconductor device manufacturing method shown in FIGS. 1 and 2, will now be described.

3 to 9 show a preferred embodiment of the first method of manufacturing a semiconductor device according to the present invention, which is a detailed explanatory drawing of the manufacturing process. The method of manufacturing the first semiconductor device will be described below.

In the first method for manufacturing a semiconductor device shown in the figure, as shown in FIG. 3, a predetermined portion of the upper surface of the metal plate 110 made of copper, copper alloy, iron-nickel alloy, iron-nickel-cobalt alloy or the like is formed. By etching, a contour blind groove 120 having a substantially U-shaped cross section is formed in a predetermined pattern on the upper surface of the metal plate 110. Then, on the metal plate 110, the contour blind groove 1
A plurality of lead forming portions 10a separated by 20 and a stage forming portion 20a are formed side by side.

Specifically, as shown in FIG. 4, a resist layer 130 is formed in a predetermined pattern on the upper surface of the metal plate 110. Further, the resist layer 130 is formed on the lower surface of the metal plate 110 and the side surfaces thereof other than the above. Then, the metal plate 110 having the resist layer 130 formed thereon is immersed in an etching treatment bath to etch a predetermined portion of the upper surface of the metal plate 110 exposed between the resist layers 130. Then, the contour blind groove 120 is formed on the upper surface of the metal plate 110.
Are formed in a predetermined pattern. After that, the resist layer 1
30 is peeled from the surface of the metal plate 110.

Next, as shown in FIG. 5, the terminal portion 14a on the upper surface of the lead forming portion is plated with silver plating 50 or the like. Similarly, the upper surface 22a of the stage forming portion is also plated 40 such as silver plating for bonding.

Specifically, the terminal portion 1 on the upper surface of the lead forming portion
Other metal plate 1 except 4a, the upper surface 22a of the stage forming portion, and the inner side surface of the contour blind groove 120 therebetween.
The upper surface of 10 is covered with a rubber mask (not shown), and the terminal portion 14a on the upper surface of the lead forming portion, the upper surface 22a of the stage forming portion, and the inner side surface of the contour blind groove 120 between them are silver-plated or the like. The platings 40 and 50 are continuously applied.

Next, as shown in FIG. 6, the upper surface 22a of the stage forming portion plated with the bonding plating 40 is used.
Then, the semiconductor chip 60 is bonded. Then, the semiconductor chip 60 is mounted on the stage forming unit 20a.

The electrodes of the semiconductor chip 60 are the terminal portions 14 on the upper surface of the lead forming portion on which the plating 50 for bonding is applied.
a to the wire 70 using a wire bonding device or the like.
Electrically connected via.

Next, as shown in FIG. 7, the top and side surfaces of the lead forming portions 10a and the stage forming portion 2 are formed.
An insulating material 30 such as an epoxy resin or a polyimide resin is continuously applied in layers on the upper surface and the side surface of 0a and the inner side surface of the contour blind groove 120 between them by a transfer molding method, a potting method, or the like. There is. Then, the plurality of lead forming portions 10a and the stage forming portion 20a are connected in series via the insulating material 30. With it
A semiconductor chip 60 and a wire 70 are enclosed inside the insulating material 30. Then, the semiconductor chip 60 and the wire 70
Prevents dust and moisture from adhering to.

Then, as shown in FIG.
0 A predetermined portion of the lower surface is etched to form the contour blind groove 12
A contour groove 140 having a substantially U-shaped cross section is formed on the lower surface of the metal plate 110 directly below 0. The contour groove 140 allows a space between the lead forming portions 10a and between the lead forming portion 10a and the stage forming portion 20a.
Are separated. Then, the plurality of leads 10 and the stage 20 are formed side by side in a plane shape at predetermined intervals. At the same time, the insulating material 30 is exposed between the contour grooves 140, and the terminal portion 12 is formed in a protruding shape at a predetermined portion of the lower surface of the lead 10.

Specifically, as shown in FIG. 7, a resist layer 150 is formed in a predetermined pattern on the lower surface of the metal plate 110. Also, on other side surfaces of the metal plate 110,
A resist layer (not shown) is formed. Then, the metal plate 110 having the resist layer 150 formed thereon is immersed in an etching treatment bath to etch the lower surface portion of the metal plate 110 exposed between the resist layers 150. Then, the contour groove 140 is formed on the lower surface portion of the metal plate 110 directly below the contour blind groove 120. After that, as shown in FIG. 9, the resist layer 150 is peeled from the surface of the metal plate 110.

Next, the terminal portion 12 projectingly formed on the lower surface of the lead 10 and the lower surface of the stage 20 are immersed in a solder bath. Then, as shown in FIG.
Solder bumps 90 and 100 are formed on the terminal portion 12 formed to project on the lower surface of 0 and the lower surface of the stage 20.
Then, the first semiconductor device as shown in FIGS. 1 and 2 is formed.

The method of manufacturing the first semiconductor device shown in FIGS. 3 to 9 comprises the above steps.

FIG. 10 shows a preferred embodiment of the second semiconductor device of the present invention, which is a sectional view thereof in detail. The second semiconductor device will be described below.

In the second semiconductor device shown in the figure, the stage 20
Are not arranged side by side with the leads 10,
Only 0s are arranged side by side in a plane at a predetermined interval.

The terminal portion 1 is provided at a predetermined portion on the lower surface of the lead 10.
2 is formed to project in a convex shape.

A semiconductor chip 60 is provided above the leads 10.
Is arranged. The electrode of the semiconductor chip 60 is flip-chip bonded and electrically connected to the terminal portion 14 on the upper surface of the lead immediately below the electrode.

On the upper surface and the side surface of the plurality of leads 10,
The insulating material 30 is continuously applied in layers. And
A plurality of leads 10 are connected in series via an insulating material 30. At the same time, the semiconductor chip 60 is enclosed inside the insulating material 30. And the semiconductor chip 6
0 is prevented from adhering dust and moisture.

Others are the same as those of the first semiconductor device shown in FIGS. 1 and 2, and the usage example and the operation thereof are the same as those of the first semiconductor device shown in FIGS. 1 and 2. Is the same as.

Next, a method of manufacturing the second semiconductor device, which is the second method of manufacturing the semiconductor device of the present invention, will be described.

11 to 15 show a preferred embodiment of the second method of manufacturing a semiconductor device according to the present invention, and more specifically, are explanatory views of the manufacturing process thereof. The method of manufacturing the second semiconductor device will be described below.

In the second method of manufacturing a semiconductor device shown in the figure, as shown in FIG. 11, a predetermined portion of the upper surface of the metal plate 110 is etched so that the contour blind groove 120 is formed on the upper surface of the metal plate 110.
Are formed in a predetermined pattern. And the metal plate 110
Further, a plurality of lead forming portions 10a separated by the contour blind groove 120 are formed side by side.

Next, as shown in FIG. 12, a plating 50 such as silver plating for bonding is applied to the terminal portion 14a on the upper surface of the lead forming portion.

Next, as shown in FIG. 13, the semiconductor chip 60 is arranged above the lead forming portion 10a. Then, the electrode of the semiconductor chip 60 is electrically connected to the terminal portion 14a on the upper surface of the lead forming portion immediately below it by flip chip bonding.

Then, as shown in FIG. 14, the insulating material 30 is continuously layered on the upper surfaces and side surfaces of the plurality of lead forming portions 10a and the inner side surfaces of the contour blind groove 120 between them. I'm wearing it. Then, a plurality of lead forming portions 10a are connected in series via the insulating material 30. At the same time, the semiconductor chip 60 is enclosed inside the insulating material 30. And, it prevents dust and moisture from adhering to the semiconductor chip 60.

Next, as shown in FIG. 15, the metal plate 1
10 A predetermined portion of the lower surface is etched to form a contour blind groove 1
A contour groove 140 is formed in the lower surface portion of the metal plate 110 immediately below 20. The contour groove 140 separates the lead forming portions 10a from each other. Then, a plurality of leads 10 are formed by arranging them in a plane shape with a predetermined interval. At the same time, the insulating material 30 is exposed between the contour grooves 140, and the terminal portion 12 is formed in a protruding shape at a predetermined portion of the lower surface of the lead 10.

Next, the solder bumps 90 are formed on the terminal portions 12 projectingly formed on the lower surface of the leads 10. Then, the second semiconductor device as shown in FIG. 10 is formed.

The second semiconductor device manufacturing method shown in FIGS. 11 to 15 includes the above steps.

In the first or second semiconductor device and the method for manufacturing the semiconductor device, as shown in FIG. 16, the lower end of the terminal portion 12 on the lower surface of the lead is formed in a substantially inverted Y shape, or As shown in FIG. 17, the lower part of the terminal portion 12 on the lower surface of the lead may be bulged to form a substantially spherical shape to widen the peripheral area of the terminal portion 12 on the lower surface of the lead. Then, the solder bumps 90 can be accurately formed on the terminal portions 12 on the lower surface of the lead, and the terminal portions 12 on the lower surface of the lead can be accurately soldered and connected to the terminal portions of the electronic circuit formed on the surface of the board. .

Further, without forming the solder bump 90 on the terminal portion 12 on the lower surface of the lead or forming the solder bump 100 on the lower surface of the stage 20, the terminal portion of the electronic circuit formed on the board surface or the stage bonding The terminal portion 12 on the lower surface of the lead is soldered and connected to the terminal portion of the electronic circuit formed on the board surface, or the lower surface of the stage 20 is made of metal formed on the board surface by using the solder paste applied to the board portion. It may be soldered to the stage joint.

When the solder bumps 90 are formed on the terminal portions 12 on the lower surface of the leads, or the solder bumps 100 are formed on the lower surface of the stage 20, the peripheral surface of the terminal portions 12 on the lower surface of the leads and the stage 20. It is preferable that the lower surface be plated with tin or the like to improve the wettability of the solder on those surfaces. Then, solder bumps 90, 1 are formed on those surfaces.
00 should be formed easily and accurately.

In addition, the terminal portion 14 on the upper surface of the lead, the terminal portion 14a on the upper surface of the lead forming portion, or in addition thereto, on the upper surface 22 of the stage or the upper surface 22a of the stage forming portion,
The lead 10 or the lead forming portion 10a or the wire 70 is formed of a metal member having excellent bonding properties without applying the plating 40, 50 for bonding, and the wire 70 or the electrode of the semiconductor chip 60 is connected to the terminal portion on the upper surface of the lead. 14 or the base of the terminal portion 14a on the upper surface of the lead formation portion may be directly bonded, or the semiconductor chip 60 may be bonded to the upper surface 22 of the stage or the upper surface 22a of the stage formation portion using an adhesive or the like.

Further, the plurality of leads 10 or the plurality of lead forming portions 10a, or in addition to them, the stage 20 or the stage forming portion 20a may be arranged side by side with a step difference instead of being flat. Even in such a case, it is possible to provide or form a semiconductor device having an action similar to that of the above-mentioned first or second semiconductor device.

In the first or second semiconductor device manufacturing method described above, a long metal strip for forming a lead frame or the like is used for the metal plate 110, and the first or second metal strip is used. It is advisable to form a plurality of lead forming portions 10a for forming the second semiconductor device, which are separated by the contour blind groove 120, or a plurality of sets of stage forming portions 20a, in addition to the lead forming portions 10a. And using that metal strip,
It is preferable that a plurality of sets of first or second semiconductor devices can be formed at the same time without trouble.

In the second semiconductor device described above,
As shown in FIG. 18, it is preferable that the back surface of the semiconductor chip 60 is exposed between the insulating materials 30 and the heat spreader 160 made of metal or the like having a high heat dissipation property is attached to the back surface of the chip. Also in the second semiconductor device manufacturing method described above, the back surface of the semiconductor chip 60 is exposed between the insulating materials 30, and the heat spreader 160 made of metal or the like having a high heat dissipation property is attached to the back surface of the chip. It is good to include a process. It is preferable that the heat generated by the semiconductor chip 60 can be efficiently provided and formed outside the semiconductor device through the heat spreader 160.

[0082]

As described above, according to the first or second semiconductor device of the present invention and the method of manufacturing the device, the BGA
It is possible to provide a semiconductor device which is easy to manufacture instead of the semiconductor device of the type and a method of manufacturing the semiconductor device which is easy to manufacture for forming the device.

[Brief description of drawings]

FIG. 1 is a sectional view of a first semiconductor device of the present invention.

FIG. 2 is a bottom view of the first semiconductor device of the present invention.

FIG. 3 is an explanatory diagram of the manufacturing method of the first semiconductor device of the present invention.

FIG. 4 is an explanatory diagram of the first semiconductor device manufacturing method according to the present invention.

FIG. 5 is an explanatory diagram of the first semiconductor device manufacturing method according to the present invention.

FIG. 6 is an explanatory diagram of the manufacturing method of the first semiconductor device of the present invention.

FIG. 7 is an explanatory diagram of the first semiconductor device manufacturing method according to the present invention.

FIG. 8 is an explanatory diagram of the first semiconductor device manufacturing method according to the present invention.

FIG. 9 is an explanatory diagram of the first semiconductor device manufacturing method according to the present invention.

FIG. 10 is a sectional view of a second semiconductor device of the present invention.

FIG. 11 is an explanatory diagram of the manufacturing method of the second semiconductor device of the present invention.

FIG. 12 is an explanatory diagram of the manufacturing method of the second semiconductor device of the present invention.

FIG. 13 is an explanatory diagram of the manufacturing method of the second semiconductor device of the present invention.

FIG. 14 is an explanatory diagram of the manufacturing method of the second semiconductor device of the present invention.

FIG. 15 is an explanatory diagram of the manufacturing method of the second semiconductor device of the present invention.

FIG. 16 is an enlarged cross-sectional view of the terminal portion on the lower surface of the lead of the first or second semiconductor device of the present invention.

FIG. 17 is an enlarged cross-sectional view of the terminal portion on the lower surface of the lead of the first or second semiconductor device of the present invention.

FIG. 18 is a sectional view of a second semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 lead 10a lead forming part 12 terminal part on lower surface of lead 14 terminal part on upper surface of lead 14a terminal part on upper surface of lead forming part 20 stage 20a stage forming part 22 upper surface of stage 22a upper surface of stage forming part 30 insulating material 40, 50 plating 60 Semiconductor chip 70 Wire 90, 100 Solder bump 110 Metal plate 120 Contour blind groove 140 Contour groove 130, 150 Resist layer 160 Heat spreader

Claims (10)

[Claims] 1. A plurality of leads and a stage on which a semiconductor chip is mounted are arranged side by side at predetermined intervals.
A terminal portion is formed so as to project at a predetermined portion of the lower surface of the lead, the electrode of the semiconductor chip and the terminal portion of the upper surface of the lead are electrically connected, and the upper surface and the side surface of the plurality of leads and the upper surface and the side surface of the stage. An insulating material is continuously deposited on the lead, and the plurality of leads and the stage are coupled in series through the insulating material, and the semiconductor chip is enclosed inside the insulating material to form a bottom surface of the lead. A semiconductor device, wherein the terminal portion is exposed between the insulating materials. 2. A plurality of leads are arranged side by side at predetermined intervals, a terminal portion is formed to project at a predetermined portion of the lower surface of the lead, a semiconductor chip is arranged above the leads, and electrodes of the chip are arranged. The leads are electrically connected to the terminal portions on the top surfaces of the leads, and insulating materials are continuously applied to the top and side surfaces of the leads, and the leads are connected in series through the insulating material. In addition, the semiconductor chip is enclosed in the insulating material, and the terminal portion of the lower surface of the lead is exposed between the insulating materials. 3. The semiconductor device according to claim 1, wherein the terminal portion on the upper surface of the lead, or in addition to this, the upper surface of the stage is plated for bonding. 4. The semiconductor device according to claim 1, wherein a solder bump is formed on the lower surface of the stage, or in addition to the terminal portion projectingly formed on the lower surface of the lead. 5. The semiconductor device according to claim 2, wherein a back surface of the semiconductor chip is exposed between insulating materials, and a heat spreader is attached to the back surface of the chip. 6. A method of manufacturing a semiconductor device, including the following steps. a. A predetermined portion of the upper surface of the metal plate is etched to form a contour blind groove in a predetermined pattern on the upper surface of the metal plate, and a plurality of lead forming portions and a stage forming portion separated by the contour blind groove are formed on the metal plate. Forming side by side. b. A step of bonding a semiconductor chip to the upper surface of the stage forming portion to electrically connect the electrode of the chip and the terminal portion on the upper surface of the lead forming portion. c. An insulating material is continuously deposited on the upper surfaces and side surfaces of the plurality of lead forming portions, the upper surface and side surfaces of the stage forming portion, and the inner side surface of the contour blind groove therebetween, and the insulating material is interposed therebetween. A step of connecting the plurality of lead forming portions and the stage forming portion in series and encapsulating the semiconductor chip inside the insulating material. d. By etching a predetermined portion of the lower surface of the metal plate,
Forming a contour groove on the lower surface portion of the metal plate directly below the contour blind groove,
The contour groove separates the lead forming portions and the lead forming portion from the stage forming portion to form a plurality of leads and the stage side by side at predetermined intervals. A step of exposing the insulating material between and forming a terminal portion at a predetermined portion of the lower surface of the lead so as to project. 7. A method of manufacturing a semiconductor device, comprising the following steps. a. A step of etching a predetermined portion of the upper surface of the metal plate to form a contour blind groove in a predetermined pattern on the upper surface of the metal plate, and forming a plurality of lead forming portions separated by the contour blind groove on the metal plate side by side. . b. A step of disposing a semiconductor chip above the lead forming portion and electrically connecting an electrode of the chip to a terminal portion on the upper surface of the lead forming portion. c. An insulating material is continuously applied to the upper surfaces and the side surfaces of the plurality of lead forming portions and the inner side surface of the contour blind groove between them, and the plurality of lead forming portions are formed through the insulating material. A step of encapsulating the semiconductor chip inside the insulating material while bonding them in series. d. By etching a predetermined portion of the lower surface of the metal plate,
Forming a contour groove on the lower surface portion of the metal plate directly below the contour blind groove,
The lead grooves are separated from each other by the contour groove to form a plurality of leads side by side at predetermined intervals, and the insulating material is exposed between the contour grooves to form a lower surface of the lead. A step of projecting and forming a terminal portion at a predetermined portion. 8. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of plating the terminals on the upper surface of the lead forming portion or the upper surface of the stage forming portion with plating for bonding. 9. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of forming a solder bump on the lower surface of the stage, or in addition to the terminal portion protrudingly formed on the lower surface of the lead. 10. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of exposing the back surface of the semiconductor chip between insulating materials and depositing a heat spreader on the back surface of the chip.