JPH09320263A - Semiconductor storage device and its refresh control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and to suppress an unwanted noise by performing refresh operation control with a test mode and eliminating refresh operation for an unused area of a DRAM. SOLUTION: When an unused area decision signal 105 is inputted to a latch control circuit 3 at an L-level, a control signal for activating a row decoder 10, a row address buffer 8 is outputted answering to a refresh operation time. The decoder 10 and the buffer 8 are activated respectively. When the signal 105 is inputted at an H-level, from the fact that an area is the area dispensing with the refresh operation, that is, it is a memory area dispensing with information hold is decided. A row decoder control signal 104 and a row address buffer control signal 111 are outputted at the L-level together, and the decoder 10 and the buffer 8 are inactivated, and thus, the refresh operation for the memory area of an answering row address is not performed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor memory device and its refresh control method, and more particularly to a semiconductor memory device formed as a readable / writable DRAM and its refresh control method.

[0002]

2. Description of the Related Art In recent years, in response to an increasing tendency of memory capacity in semiconductor memory devices, reduction of power consumption of the memory has become an important issue. In particular, DRAM, which has a large ratio of cost to capacity, among the memories. In this case, the reduction of power consumption is an indispensable issue. Generally, in a DRAM, stored information is held in the form of electric charges in a parasitic capacitance of a gate portion of a memory element.
After a lapse of a predetermined time, the stored information is lost due to the leakage current in the parasitic capacitance. Therefore, a so-called refresh operation for amplifying and reproducing the information in the memory cell at every fixed time is required. Since this refresh operation is performed for all memory cells of the DRAM, the amount of power consumption during information retention accompanying the refresh operation is extremely large.

FIG. 7 is a block diagram showing a conventional DRAM. As shown in FIG. 7, in this conventional example, the clock generator 2, the counter 27, and the row address
The buffer 8, the column address buffer 9, the row decoder 10, the column decoder 11, and the sense amplifier 1
2, a memory cell array 13, and a data input / output buffer 14. In the conventional example, when refreshing the memory cell array 13,
The generator 2 receives the row address strobe signal 101, the column address strobe signal 102, and the write enable signal 103 from the outside, outputs the refresh request signal 106 at the active level, and inputs the refresh request signal 106 to the counter 27. Along with
The row address buffer control signal 111 is output to the row address buffer 8 at an active level. The row decoder control signal 104 is output to the row decoder 10 at an active level. In the counter 27, the refresh request signal 1
When 06 is input at the active level, the refresh row address 114 is generated and input to the corresponding row address buffer 8, and the refresh row address of the DRAM is input via the corresponding row decoder 10. By driving the designated sense amplifier 12, the memory cell array 13 of the DRAM concerned is driven.
The refresh operation is performed on all the memory cells.

Thus, during the refresh operation in the DRAM, the refresh operation is uniformly performed on all the memory cells forming the memory cell array. For this reason, when maintaining the DRAM in the information holding state, the power consumption becomes large due to the refresh operation, which becomes a major obstacle to maintaining the information holding time of the DRAM. In order to deal with this problem, as a method for reducing power consumption at the time of refresh operation, for example, Japanese Patent Laid-Open No. Sho 60
-175294, JP-A-60-175295, JP-A-60-175296, etc., target memory cells for refresh operation by detecting an unused memory bank in the DRAM. A method has been proposed in which a region is suppressed and thereby power consumption is reduced. Below, JP-A-60-17
The conventional technique described in Japanese Patent No. 5296 will be described.

FIG. 8 is a block diagram showing an example of an access device corresponding to a general DRAM, and FIG. 9 is a row address of a conventional DRAM disclosed in the above-mentioned Japanese Patent Laid-Open No. 175296/1985. It is a block diagram showing an internal configuration of a decoder for strobe signals. As shown in FIG. 8, the access device has a D-type bank configuration.
RAM 40, CPU 28, address 130 and refresh address signal 13 applied to DRAM 40
Functioning as a multiplexer 30, a refresh add-on generator 31, a refresh timer 32, and a command signal output from the CPU 28 and a refresh request signal generated by the refresh timer 32. An arbiter 33, a timing generator 35, a write enable buffer 36, a column address strobe buffer 37, a row address strobe decoder 38, a bank address signal latch 34, and a data buffer 39. It is configured with.

In FIG. 8, the address signal 130 output from the CPU 28 is divided into 8-bit address signals and input to the multiplexer 30. The output of this multiplexer 30 is the timing generator 3
The signal is controlled by the SL signal 133 supplied from the circuit 5 and is alternately input to the corresponding address terminal of the DRAM 40. In the arbiter 33, during the period other than the time period in which the refresh operation is performed, the CPU 2
The command signal output from the signal generator 8 is accepted, and the timing generator 35 outputs the write enable signal 134, the column address strobe signal 135, and the row address strobe signal 136.
The write enable signal 134 is input to the DRAM 40 via the buffer 36 and used as an enable signal at the time of write access. The column address / strobe signal 135 is input to the DRAM 40 via the buffer 37 and used as a column address / strobe signal. Also, the row address strobe signal 136
Is input to the DRAM 40 after the logic for bank selection in the DRAM 40 is taken in the decode 38 and used as a row address strobe signal.

Next, the refresh operation for the DRAM 40 will be described. When the refresh request signal is input to the decoder 38 via the arbiter 33 and the timing generator 35, the decoder 38 outputs a row address strobe signal to the DRAM 40 at an active level. At this time, the row address strobe signal is output to all the banks in the DRAM 40, so that the refresh operation is collectively performed on all the banks. Hereinafter, with reference to FIG. 9, the prior art will be described in a spread manner. The access device for the DRAM 40 has the same configuration as that shown in FIG. 8 described above.

In FIG. 9, the DRAM 40 is a bank A.
58, bank B59, bank C60 and bank D61
It is composed of four DRAMs including Bank selection signals 140, 141, 142 and 143 output from decoder 41 in response to inputs of extended address signals 138 and 139 (included in extended address signal 137 of FIG. 8) respectively correspond to corresponding NAND gates 50, 5 respectively.
One of the input terminals 1, 52 and 53 is input. The other input terminals of these NAND gates 50, 51, 52 and 53 are connected to the timing generator 35 (see FIG.
Row address strobe signal 149 sent from the NAND gates 50, 51,
The logical product outputs output from 52 and 53 are input to one input terminals of corresponding NOR gates 54, 55, 56 and 57, respectively. On the other hand, the decoder 4
1, the bank selection signals 140, 141,
142 and 143 are bank address latches 42,
It is also input to 43, 44 and 45. These bank address latches 42, 43, 44 and 45 are
Reset signals 144, 145, 146 and 1 respectively
After being reset by 47, after the reset is released, the bank selection signals 140, 141, 14
The first falling edges of 2 and 143 are latched individually, and the contents of the latch are the following reset signals 144,
It is held until 145, 146 and 147 are input. These bank address latches 42, 43, 44
And 45 outputs NAND gates 46, 47, 48
Input to one of the input terminals of
The ND gates 46, 47, 48 and 49 are logically ANDed with the refresh request signal 148 sent from the refresh timer 32 (see FIG. 8), and the outputs are NOR gates 54, 55 and 56 described above. And 57
Is input to the other input terminal of. NOR gates 54 and 5
5, 56 and 57 are ORed with the above-mentioned NAND gates 50, 51, 52 and 53, and their OR outputs are bank A58, bank B59, bank C60 and bank D6 included in the DRAM 40, respectively.
1 is input to the row address strobe pin. As a result, the bank selection control for the DRAM 40 is performed, and the refresh control for the DRAM 40 is performed through the operation of each unit.

Next, the refresh operation in the conventional example will be described. In FIG. 9, when the power is turned on, the reset signals 144, 145, 146 and 147 are reset.
Are input all at once, the bank address latches 42, 4
3, 44 and 45 are reset at the same time. After that, when the reset operation is released, all the bank address latches 42, 43, 44 and 45 are ready for the latch operation, and the bank selection signals 140, 141, 142 and 14 output from the decoder 41.
The first falling edge of 3 is individually latched. As described above, once this falling edge is latched, the contents of the latch are the following reset signals 144,
It is held as it is until 145, 146 and 147 are input.

Now, in DRAM 40, bank A5
If access is made in the order of 8, bank B59, bank C60, and bank D61, bank A5
8 before the write access to 8 is started, the extended address signals 138 and 139 corresponding to the bank A58.
8 (included in the extended address signal 137 of FIG. 8) is input to the decoder (corresponding to the decoder 38 of FIG. 8) 41 and decoded. As a result, only the bank selection signal 140 for the bank A58 is output at the "L" level.
In the bank address latch 42, the falling edge of the bank selection signal 140 is latched, and its content is
It is held until the next reset signal 144 is input.
As a result, only the output of the bank address latch 42 is output at the “L” level and input to the NAND gate 46. In the NAND gate 46, "L" is generated only when the refresh request signal 148 is input.
A level signal is output and input to the row address strobe terminal of the bank A58 via the NOR gate 54. That is, at this time, only the bank A58 can be refreshed. In this state, write to bank A58
It is retrieved whether the access is the first write access for bank A58.

If the result of this search is the first write access, first the refresh request signal 14
By inputting 8 as appropriate, 8 for bank A58
The refresh dummy cycle of the cycle is executed. In this case, the refresh dummy cycle substitutes the dummy cycle which is not intended to write / read information. When this dummy cycle ends, the entire address area of the bank A58 is written for the first time.
It becomes possible to access. After that, by appropriately adding a row address strobe signal, a column address strobe signal, a write enable signal, an address signal 130, etc., an access operation such as a write / read to the bank A58 is performed in the order of the corresponding address. Go on. Further, during the memory access period, for example, the normal refresh operation is performed every 15.6 μs, but in this case, only the bank A58 is refreshed.

Here, if it is assumed that the access to the bank A58 is completed, it is searched whether or not the memory contents of the bank A58 are held. If the holding is not necessary, the reset signal 144 is input to the bank address latch 42, which resets the bank address latch 42 and puts it in a non-refreshable state. Further, when the holding state is necessary, the bank address latch 42 is maintained in the refreshable state without being reset. Hereinafter, similarly,
The refresh operation as described above is also performed in accessing the bank B59, the bank C60, and the bank D61. For example, when the bank B59 is used, a normal refresh operation is performed for the bank B59 after a lapse of a dummy cycle at all times, but it is necessary to retain the stored contents of the bank A58 which has already been used. In some cases, the refresh operation is performed after the dummy cycle has passed, and when it is not necessary to retain the stored content, the dummy cycle and the refresh operation are not performed.

By performing the refresh operation as described above, refresh control for each bank is possible. That is, in the case of the conventional technique, only the banks for which storage contents need to be retained and the banks currently in use are dealt with in accordance with the usage states of the banks in the order of bank A, bank B, bank C, and bank D. A normal refresh operation is performed after the dummy cycle has elapsed.

[0014]

In the above-mentioned conventional semiconductor memory device and its refresh control method,
When the DRAM forming the semiconductor memory device is refreshed in order to hold the stored information in the memory cell, all the memory cells in the DRAM are refreshed. However, there is a drawback in that an excessive current flows into the DRAM during the refresh operation, which causes noise.

Further, in the case of the prior art described in the above-mentioned Japanese Patent Laid-Open No. 60-175296, the memory system is composed of a plurality of DRAM banks, and refresh control is individually performed for each of these banks. However, since the refresh control that integrates the entire system is not performed, there is a drawback that the effect of reducing the power consumption of the entire memory system is small.

[0016]

A semiconductor memory device according to a first aspect of the present invention comprises a memory cell array, a row decoder, a column decoder, a sense amplifier, a data input / output means, etc., and is a readable / writable semiconductor memory device. At the time of a cycle, it receives a predetermined row address strobe signal, column address strobe signal and write enable signal, and receives a row decoder / column decoder control signal, an unused area determination signal, a refresh request signal, a highest row address Latch control signal,
An access control means for outputting a row address / latch control signal, an address buffer control signal, etc., and an input of the row address / latch control signal in response to the occurrence of a write cycle, and latches the input row address. The first row address / latch means and the first row address / latch control signal are input to receive the first row address / latch control signal
Second row address latch means for inputting the row address latched by the row address latch means and latching the row address as the highest row address, and the first row address latch means corresponding to the generation of the write cycle. The row address latched by the latch means is compared with the highest row address latched by the second row address latch means, and the row latched by the first row address latch means is compared. Comparing means for outputting a highest judgment signal for judging whether an address is higher than the highest row address latched by the second row address latch means; and the second row address. Upon receiving the input of the highest row address output from the latch means, the refresh row address is transmitted via the refresh request signal. Thereby generating and outputting a refresh control means for outputting an unused area determination signal determines whether the region of interest of the refresh operation, in response to input of the refresh row address,
A row address buffer which is controlled by the address buffer control signal and outputs a row address to the row decoder via a predetermined clock signal, and the refresh control means includes the second row. The unused area determination that is output when the highest row address latched by the address latch means is compared with the refresh row address and the refresh row address is lower than the highest row address Via the signal, the row decoder / column decoder control signal activates the row decoder, and the address buffer control signal activates the address buffer.

The refresh control means receives the refresh request signal, counts the refresh request signal, generates a refresh row address, and outputs the refresh row address.
It may be configured to include a comparator that compares the refresh row address with the highest row address output from the second row address latch means and outputs the unused area determination signal. The access control circuit receives at least the row address / strobe signal, the column address / strobe signal, and the write enable signal and receives at least the row decoder control signal.
A clock generator that generates and outputs a refresh request signal and a row address buffer control signal,
And a latch control circuit for receiving and inputting the unused area determination signal and the highest determination signal and generating and outputting at least the highest row address / latch control signal and the row address / latch control signal. Good.

A refresh control method for a semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein a row address strobe signal, a column address A first step of setting the DRAM in a test mode by adjusting the input timing of the strobe signal and the write enable signal, and a second row address latch by executing a read access to an arbitrary address of the DRAM A second step of updating the highest row address latched by the means, and the second row address latch means corresponding to the highest row address latch updated in the second step, The arbitrary that is input at the time of the read access It is characterized by having a third step of latching the row address of the address, at least.

[0019]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment includes a clock generator 2 and a latch control circuit 3,
In response to input of a row address / strobe signal 101, a column address / strobe signal 102 and a write enable signal 103 from the outside, a row decoder control signal 104, an unused area determination signal 105, a refresh request signal 106, a top row Address / latch control signal 107, highest row address / latch / reset signal 1
08, the row address / latch control signal 109 and the row address / buffer control signal 111 are generated and output, the row address / latch 4 for latching the row address, and the row address for latching the highest row address.・ Latch 5 and row address latch 4
A comparison 6 for comparing the row address latched in the row address and the highest row address latched in the row address latch 5, the refresh control circuit 7, the row address buffer 8, and the column address buffer 9. , A row decoder 10, a column decoder 11, a sense amplifier 12, a memory cell array 13, and a data input / output buffer 14.

Among the above components, the access control circuit 1, the row address latches 4 and 5, the comparator 6, the refresh control circuit 7, and the row add buffer 8 are particularly included.
The column address buffer 9 and the column address buffer 9 form the refresh control system of the semiconductor memory device of this embodiment.
2 is a block diagram showing the internal configuration of the refresh control circuit 7 described above. The refresh row address is synchronized with the refresh control signal 106 output from the clock generator 2 included in the access control circuit 1. A counter 15 for generating and outputting 114, and a comparator 16 for comparing the refresh row address 114 with the highest row address which has been already accessed for writing and output from the row address latch 5 are configured. .

Next, the refresh operation will be described with reference to FIGS. 1 and 2. When the power is turned on, the highest row address / latch / reset signal 108 is output at the “H” level from the latch control circuit 3 and the refresh request signal 106 until the first write access is executed. Is output at "L" level. The row address / latch 5 is reset by receiving the highest row address / latch / reset signal 108, and the refresh control circuit 7 is inactive by receiving the "L" level refresh request signal 106. As a result, the refresh operation in this embodiment is stopped.

In this state, when the first write access occurs, the latch control circuit 3 outputs the row address
The latch control signal 109 is output at "H" level,
Input to row address latch 4. Row address
In the latch 4, the row address input at that time is latched and held. At that time, the row address latched by the row address latch 4 is immediately output to the row address latch 5, and the highest row address latch control signal 107 sent from the latch control circuit 3 causes the highest row address latch. The higher row address is latched by the row address latch 5. When the next write access cycle occurs, the row address latch 4 latches the row address being input at that time, and the latched row address is changed to the row address latch 4 in the same manner as above.
It is output to the latch 5 and the comparator 6. In the comparator 6, the row address latched by the row address latch 4 is compared with the highest row address latched by the row address latch 5 and held as the highest row address which has already been write-accessed. Matched. In this comparison and collation, when the row address latched by the row address latch 4 is a lower row address than the highest row address latched by the row address latch 5, the comparator 6 determines the highest row address. The upper determination signal 110 is output at the “L” level and input to the latch control circuit 3. Conversely, if the row address latched by the row address latch 4 is a higher row address than the highest row address latched by the row address latch 5,
The highest determination signal 110 is output from the comparator 6 at the “H” level and input to the latch control circuit 3. In the latch control circuit 3, when the highest determination signal 110 is input at the “H” level, the highest row address / latch control signal 107 is output at the “H” level to the row address / latch 5. Is entered.

In the subsequent write access cycle, the above-described operation is repeatedly executed, whereby the row address latch 5 continues to be in a state where the highest row address at the time of write access is always latched. To be done. Next, the highest row address 113 latched in the row address latch 5 is output to the refresh control circuit 7 and the refresh control circuit 7 concerned.
It is input to the internal comparator 16. On the other hand, the refresh request signal 106 output from the clock generator 2 included in the access control circuit 1 is input to the counter 15 in the refresh control circuit 7, and the refresh request signal 106 is "H". By inputting at the level, the refresh row address 114 is generated and output, and is output to the row address buffer 8 and the comparator 16 as described above. In the comparator 16, this refresh
When the row address 114 is compared with the highest row address 113 input from the row address buffer 5 and the refresh row address 114 is a row address lower than the highest row address 113, The unused area determination signal 105 is output from the comparator 16 at the “L” level and input to the latch control circuit 3. Conversely, the refresh row address 114
If the row address is higher than the highest row address 113, the comparator 16 outputs the unused area determination signal 105 at the “H” level, and the latch control circuit 3
Is input to

In the latch control circuit 3, when the unused area determination signal 105 is input at "L" level, the memory area of the corresponding row address needs refreshing, that is, information holding. Row decoder control signal 104 for activating row decoder 10 and row address buffer 8 in response to the refresh operation.
Address buffer control signal 1 to activate
11 is output at the "H" level and is input to the corresponding row decoder 10 and row address buffer 8 to be activated. In addition, the comparator 16
When the unused area determination signal 105 output by the above is input at the “H” level, it is determined that the area does not require the refresh operation, that is, the memory area that does not require information retention, and Row decoder control signal 10
4 and the row address buffer control signal 111 are both output at the "L" level to inactivate the row decoder 10 and the row address buffer 8, thereby refreshing the memory area of the corresponding row address. Is not done.

Next, one embodiment of the refresh control method of the second invention will be described. FIG. 3 is a configuration diagram showing a main part of a system function corresponding to the first embodiment. As shown in FIG. 3, the sysdem function corresponding to the present embodiment has a CPU 17, a memory control circuit 18, a D
RAM (A) 19, DRAM (B) 20, DRAM
(C) 21 and DRAM (D) 22. 4 is a diagram showing a memory map in the present embodiment, FIG. 5 is a timing chart in the DRAM test mode in the present embodiment, and FIG. 6 is a flowchart of a main part of a memory control procedure in the present embodiment. It is a figure. Hereinafter, this embodiment of the second invention will be described with reference to FIGS. 1, 2, 3, 4, 5, and 6.

In the memory map shown in FIG. 4,
System area (1) 23 formed as a ROM area
Is an area where the operating system resides, and the unused area 26 is an area where the memory is not mapped on the system. The system area (3) 25, which is a dynamic memory (DRAM) area,
The system area (2) 24 is an area used as a work area by an application, and is used as a work area by the operating system. Normally, when the system is started, the operating system stored in the system area (1) 23
The system is started and the system is set up. At that time, a memory check program for confirming whether or not all the dynamic memories (DRAM) mounted on the system operate normally is executed. In this memory check program, D
RAM (A) 19, DRAM (B) 20, DRAM
For all areas of (C) 21 and DRAM (D) 22, read access is executed after write access is executed, and it is determined whether or not the contents of all memory cells are normal.

Next, referring to the system functional configuration diagram of FIG. 3, the memory map of FIG. 4, the timing diagrams of FIGS. 5A, 5B and 5C and the flow chart of FIG. 6, in the test mode. The operation procedure of is spread and explained. In the memory map of FIG. 4, for convenience of explanation,
The application 1 and the application 2 are mapped in arbitrary areas. Regarding the execution of the application, it is assumed that the application 1 is executed first, and after the execution of the application 1 is completed, the application 2 is executed. First, step S1 (see FIG. 6)
When the system is started in, the system area (3)
25 and DRAM (A) 19, DRAM (B) 20, and DRA mapped in the system area (2) 24.
A memory check is performed on the M (C) 21 and the DRAM (D) 22. When this memory check is completed, DRAM (A) 19, DRAM (B) 20, DRA
Since the highest row address latched in the highest row address latch 5 (see FIG. 1) corresponding to each of the M (C) 21 and the DRAM (D) 22 has the maximum value, these DRAMs (A) 19, DRAM
(B) 20, DRAM (C) 21 and DRAM (D)
A refresh operation for 22 is performed. Here, DRAM (A) 19, DRAM (B) 20, DR
The AM (C) 21 and the DRAM (D) 22 are unused.

Next, in step S2 (see FIG. 6), when the memory check program is executed,
Since the highest row address latched by the highest row address latch 5 has the maximum value, it is necessary to update the highest row address latched by the row address latch 5. The update of the highest row address is executed by the following procedure. In FIG.
First, for the DRAM (A) 19. The CPU 17 executes the test mode of the DRAM. In addition,
In executing the test mode, it is necessary to set an arbitrary address (hereinafter referred to as TEST address) dedicated to the test mode (unused area) in the memory map of FIG. In step S3 (see FIG. 6), when the CPU 17 (see FIG. 3) accesses the TEST address, the memory control circuit 18 outputs the data as shown in FIGS. 5 (a), 5 (b) and 5 (c). The corresponding row address strobe signal 119-1, the column address strobe signal 120-1, and the write enable signal 121-1 are output, and the corresponding DRAM
(A) It is input to 19, so that at the timing of the test mode start shown in FIG.
(A) 19 is set to the test mode. Next, in step S4, the CPU 17 causes the SYS-STA
Read access to the RT address (see FIG. 4) is performed.

According to the operation procedure described above, the DRAM
(A) 19 indicates that the latch control circuit 3 shown in FIG.
The highest row address latch control signal 107 is output at the “H” level and input to the row address latch 5. In the row address latch 5, the SYS input at the read access in step S4 is input.
Since the row address (minimum value) of the -SRART address is latched, the refresh operation is not performed on all the memory cells of the DRAM (A) 19. Finally, in step S5, the CPU 17 makes a dummy
The fresh cycle is executed, and normal access can be performed. The DRAM (B) 20,
With respect to the DRAM (C) 21 and the DRAM (D) 22, the refresh operation is not performed on all the memory cells of the DRAM (A) 19 by the same operation procedure as that of the DRAM (A) 19. .

Next, the DRAM (A) 19 and the DRAM
(B) 20, DRAM (B) 21, and DRAM (D)
A case where the areas up to 22 are used as an operating system (work) area and an application area will be described. In the memory map of FIG.
When the system area 2 is being used by the operating system, in the DRAM (A) 19, the highest row address that is write-accessed is latched by the row address latch 5, so Only the area up to the address SYS-END of (A) 19 is the area where the refresh operation is performed.
Next, when the area from START (1) to END (1) is used by the application 1, the entire area of the DRAM (A) 19 is used by the operating system and the application 1. Therefore, the refresh operation is executed for all the memory cells. In the DRAM (B) 20, only the area up to the address END (1) is used, so only the refresh operation from the head address to the address END (1) is performed.

Here, when the application to be executed is switched from the application 1 to the application 2, that is, when the area to be used is switched from the area of the application 1 to the area of the application 2, the area of the application 1 is used. DRAM (A) 19 and DRAM (B)
The refresh operation for the 20 application 1 areas is not required. In this case, the DRAM (A) 19
In the above, by executing the read access to the SYS-END address after executing the test mode as already described, the S-START (1) to S-address are read.
Only the refresh operation up to the address YS-END is performed. Further, since the DRAM (B) 20 becomes an unused area, the DRAM (B) 20 is not used after the test mode is executed.
By executing the read access to the head address of (B) 20, in the DRAM (B) 20, the refresh operation is not performed for all the memory cells. Even when the execution of the application 2 is completed, the operation as described in the application 1 is performed to release the used area and suppress unnecessary refresh operation.

As described above, in the embodiment of the second invention, the refresh operation can be controlled by using the test mode of the DRAM, so that the power consumption of the corresponding DRAM is reduced. It can be reduced. For example, the usage rate of DRAM is 50%,
Assuming that the number of refresh operations within a certain period of time is 1024, the number of refresh operations can be reduced to 1/2, that is, 512 refresh operations. Therefore, as power consumption, reduce the power consumption for 512 refresh operations. You can Also, by managing the row address of the used area,
Since the refresh operation in the unused area is not performed, it is possible to reduce power consumption and suppress unnecessary noise caused by the refresh operation.

In the above description, DRAM is used as a row address latch during write access.
However, it is needless to say that the same effect can be obtained by the present invention even in the case of a late write cycle. Also, in the above description, the refresh operation of driving the memory cells corresponding to the row address has been described as the form of the refresh operation. It goes without saying that the invention is effectively applied to the driving refresh operation.

[0035]

As described above, the present invention provides a DRA
During the refresh operation of M, the refresh operation is controlled in the test mode and the DRAM
By eliminating the refresh operation for the unused area, the refresh operation can be performed only in the used area. Therefore, unnecessary power consumption can be eliminated and the power consumption can be reduced. This has the effect of suppressing unnecessary noise that occurs with the operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device of the first invention.

FIG. 2 is a block diagram showing a refresh control circuit included in one embodiment of the first invention.

FIG. 3 is a diagram showing a system functional configuration corresponding to one embodiment of a refresh control method of a second invention.

FIG. 4 is a diagram showing a memory map corresponding to one embodiment of the second invention.

FIG. 5 is a DRA corresponding to one embodiment of the second invention.
It is a timing diagram in M test mode.

FIG. 6 is a diagram showing a flowchart of a main part of a memory control procedure in the embodiment of the second invention.

FIG. 7 is a block diagram showing an internal configuration of a general DRAM.

FIG. 8 is a block diagram showing an example of a conventional general access device for a DRAM.

FIG. 9 is a block diagram showing a conventional row address strobe decoder.

[Explanation of symbols]

1 Access control circuit 2 Clock generator 3 Latch control circuit 4, 5 Row address latch 6, 16 Comparator 7 Refresh control circuit 8 Row address buffer 9 Column address buffer 10 Row decoder 11 Column decoder 12 Sense amplifier 13 Memory cell Array 14 Data input / output buffer 15, 27 Counter 17, 28 CPU 18 Memory control circuit 19 DRAM (A) 20 DRAM (B) 21 DRAM (C) 22 DRAM (D) 23 System area (1) 24 System area (2 ) 25 system area (3) 26 unused area 29 command buffer 30 multiplexer 31 refresh address generator 32 refresh timer 33 arbiter 34 latch 35 timing generator 3 , 37 buffer 38, 41 decoder 39 data buffer 40 DRAM 42 to 45 bank address latch 46 to 53 AND gate 54 to 57 OR gate 58 bank A 59 bank B 60 bank C 61 bank D 101, 119-1 to 119-4, 136, 149
Row address strobe signal 102, 120-1 to 120-4, 135 Column address strobe signal 103, 121-1 to 121-4, 134 write
Enable signal 104 Row decoder control signal 105 Unused area determination signal 106, 148 Refresh request signal 107 Highest row address / latch control signal 108 Highest row address / latch / reset signal 109 Row address / latch control signal 110 Highest determination Signal 111 Row address buffer control signal 112 Address signal 113 Highest row address 114 Refresh row address 115 Output enable signal 116 Input / output signal 117 Data / address bus 118 Control bus 123 SYS-START address 124 SYS-END address 125 START (1) address 126 END (1) address 127 START (2) address 128 END (2) address 129 TEST address 130, 131, 137, 13 Address signal 132 refresh address signal 133 SL signal 137, 138, 139 extended address signal 140-143 bank selection signal 144 to 147 the reset signal S1-S5 step

Claims (4)

[Claims] 1. A memory cell array and a row decoder,
In a readable / writable semiconductor memory device including a column decoder, a sense amplifier, a data input / output unit, etc., a predetermined row address / strobe signal, column address / strobe signal and write / write
Receiving an enable signal input, it outputs a row decoder / column decoder control signal, unused area determination signal, refresh request signal, highest row address / latch control signal, row address / latch control signal, address buffer control signal, etc. In response to the access control means and the occurrence of the write cycle, the row address
First row address latch means for receiving a latch control signal and latching the input row address; and first row address latch for receiving the highest row address latch control signal Second row address latch means for inputting the row address latched by the means and latching it as the highest row address, and latched by the first row address latch means in response to the occurrence of the write cycle. Row address,
The highest row address latched by the second row address latch means is compared, and the row address latched by the first row address latch means is compared with the second row address latch. Comparing means for outputting a highest judgment signal for judging whether or not it is higher than the highest row address latched by the means, and the highest row address outputted by the second row address latch means. A refresh control means that receives an input, generates and outputs a refresh row address via the refresh request signal, and outputs an unused area determination signal for determining whether or not the area is a target of a refresh operation. When the refresh row address is input, it is controlled by the address buffer control signal and a predetermined clock A row address buffer for outputting a row address to the row decoder via a clock signal, and in the refresh control means, the highest row latched by the second row address latch means. An address is compared with the refresh row address, and the row decoder / column decoder is output via the unused area determination signal output when the refresh row address is lower than the highest row address. A semiconductor memory device characterized in that the row decoder is activated by a control signal and the address buffer is activated by the address buffer control signal. 2. A counter for the refresh control means to input and count the refresh request signal to generate and output the refresh row address, the refresh row address and the second row address. 2. The semiconductor memory device according to claim 1, further comprising: a comparator that compares the highest row address output from the latch means and outputs the unused area determination signal. 3. The access control circuit receives at least the row address strobe signal, the column address strobe signal and the write enable signal, and at least the row decoder control signal, the refresh request signal and the row address buffer control. A clock generator that generates and outputs a signal, and receives at least the unused area determination signal and the highest-order determination signal, and generates at least the highest row-address / latch control signal and the row-address / latch control signal. The semiconductor memory device according to claim 1, comprising a latch control circuit for outputting. 4. The semiconductor memory device according to claim 1, wherein during read operation of the readable / writable DRAM, the input timing of the row address strobe signal, the column address strobe signal, and the write enable signal is adjusted. A first step of setting the DRAM in a test mode, and a second step of updating the highest row address latched by the second row address latch means by executing a read access to an arbitrary address of the DRAM. And the second row address latch corresponding to the highest row address latch updated in the second step.
It has at least a third step of latching a row address of the arbitrary address inputted at the time of the read access by the latch means, and a fourth step of executing a dummy refresh cycle by a predetermined CPU. A refresh control method for a semiconductor memory device, comprising: