JPH09325366A - Liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

(57) [Abstract] [Problem] To prevent deterioration of display quality. SOLUTION: A semiconductor thin film formed on a gate insulating film 33 and an n ⁺ type silicon layer formed on the semiconductor thin film other than a device region are removed respectively, and a channel region 34 is formed.
a is formed, a drain region 38a and a source region 38b are formed on both sides of the upper surface thereof, a pixel electrode 40 is formed at a predetermined location on the gate insulating film 33, and another predetermined location on the gate insulating film 33. To the drain line 43
Are formed. In this case, the long hole 41 is formed in the gate insulating film 33 between the pixel electrode 40 and the drain line 43.
Therefore, the unnecessary portion of the remaining semiconductor thin film and the n ⁺ type silicon layer can be removed together with the gate insulating film 33 when the elongated hole 41 is formed. Therefore, it is possible to prevent the drain line 43 and the pixel electrode 40 from being short-circuited by an unnecessary portion of the remaining semiconductor thin film or the n ⁺ type silicon layer, and prevent the display quality from being deteriorated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, an active matrix type liquid crystal display element has a structure in which liquid crystal is sealed between a display drive panel and a common electrode panel arranged thereon. Of these, the display drive panel has drain lines (signal lines) and gate lines (scan lines) formed in a grid pattern, and thin film transistors are formed in the vicinity of the intersections of the drain lines (signal lines) and the gate lines (scan lines). Pixel electrodes are formed in the portions.

15 to 21 show a manufacturing process of such a liquid crystal display device. In manufacturing this liquid crystal display element, first, as shown in FIG. 15, a gate electrode G and a gate line 2 are formed at predetermined locations on the upper surface of the glass substrate 1. Next, the gate insulating film 3 made of silicon nitride or the like is formed on the upper surface of the glass substrate 1 including the gate electrode G and the gate line 2, and then the semiconductor thin film 4 made of intrinsic amorphous silicon or the like is formed on the upper surface. Then, a channel protective film forming layer 5 made of silicon nitride or the like is formed on the upper surface thereof. Next, a first photoresist pattern 6 is formed on the upper surface of the channel protective film forming layer 5 and at a predetermined position on the gate electrode G.

Next, when the channel protection film forming layer 5 is etched using the first photoresist pattern 6 as a mask, a channel protection film 7 is formed under the first photoresist pattern 6 as shown in FIG. Then, the first photoresist pattern 6 is peeled off. Next, as shown in FIG. 17, an n ⁺ type silicon layer (ion diffusion layer) 8 made of n ⁺ type amorphous silicon mixed with phosphorus or the like is formed on the upper surface of the semiconductor thin film 4 including the channel protective film 7. .
Next, second photoresist patterns 9 are formed on the upper surface of the n ⁺ type silicon layer 8 at two predetermined positions on both sides of the upper surface of the channel protective film 7.

Next, when the n ⁺ type silicon layer 8 and the semiconductor thin film 4 are etched by using the second photoresist pattern 9 as a mask, as shown in FIG. 18, unnecessary parts of the n ⁺ type silicon layer 8 and the semiconductor thin film 4 are removed. By removing the portion, a drain region 8a and a source region 8b made of n ⁺ type silicon are formed in an island shape in the device region, and a channel region 4a made of intrinsic silicon is formed. Then, the second photoresist pattern 9 is peeled off. Next, as shown in FIG. 19, the pixel electrode 10 made of ITO is formed at a predetermined position on the upper surface of the gate insulating film 3.

Next, as shown in FIG. 20, the drain contact layer 11a and the source contact layer 11b are formed on the upper surfaces of the drain region 8a and the source region 8b, respectively, and the drain contact layer 11a and the source contact layer are formed. A drain electrode D and a source electrode S are formed on each upper surface of 11b. In this case, at the same time, the drain line 12 is formed at a predetermined position on the upper surface of the gate insulating film 3 via the drain line contact layer 11c. In this state, the drain line 12 is connected to the drain region 8a through the drain contact layer 11a and the drain electrode D, and the source region 8b is connected through the source contact layer 11b and the source electrode S to the pixel electrode 1.
0 is connected.

Next, as shown in FIG. 21, a passivation film (overcoat film) 13 is formed at a predetermined position on the upper surface. In this state, the opening 13a is formed in the passivation film 13 in the central portion of the pixel electrode 10. In this case, the reason why the opening 13c is formed in the passivation film 13 in the central portion of the pixel electrode 10 is to increase the transparency on the pixel electrode 10. Thus, the liquid crystal display device is completed.

[0008]

However, in the conventional method of manufacturing such a liquid crystal display element, the semiconductor thin film 4 is used.
Since the a, the pixel electrode 10 and the drain line 12 are all formed on the upper surface of the gate insulating film 3, that is, on the same plane, when the channel protective film forming layer 5 is poorly etched due to the presence of particles (foreign matter), If unnecessary portions of the protective film forming layer 5 and the n ⁺ type silicon layer 8 remain, or if etching defects of the n ⁺ type silicon layer 8 and the semiconductor thin film 4 occur for the same reason, the n ⁺ type silicon layer 8 and Unnecessary portions of the semiconductor thin film 4 may remain, and these unnecessary portions of the semiconductor thin film 4 and the n ⁺ type silicon layer 8 may be left over the drain line 12 on the gate insulating film 3.
Between the pixel electrode 10 and the pixel electrode 10, the drain line 1
2 and the pixel electrode 10 are short-circuited, the pixel electrode 10 does not operate normally, and the display quality deteriorates. An object of the present invention is to prevent deterioration of display quality.

[0009]

According to the first aspect of the present invention,
In a liquid crystal display element in which a pixel electrode and a signal line are formed on an insulating film, an opening is formed in at least the insulating film between the pixel electrode and the signal line. According to a second aspect of the present invention, in a liquid crystal display element in which a plurality of signal lines are arranged and formed on an insulating film, and pixel electrodes are formed between the signal lines, the pixel electrodes and positions on both sides thereof are provided. An opening is formed in the insulating film between the signal line and the signal line. According to a fourth aspect of the invention, in a liquid crystal display element in which a plurality of signal lines are arranged and formed on an insulating film, and a pixel electrode is formed between each of the signal lines,
An opening wider than the width of the signal line is formed in the insulating film between the pixel electrodes adjacent to each other in the arrangement direction of the signal line, and a part of the signal line is located in the opening. . According to a fifth aspect of the invention, a plurality of pixel electrodes are formed in an array on the insulating film, an opening is formed in the insulating film at a predetermined position along the periphery of the pixel electrode, and a signal is formed on the insulating film. A line is formed such that at least a part of the opening is located between the signal line and the pixel electrode. According to a sixth aspect of the present invention, a plurality of pixel electrodes are formed in an array on the insulating film, an opening is formed in the insulating film between the adjacent pixel electrodes, and a width of the opening is formed on the insulating film. Also forms a narrow signal line so that a part thereof is located in the opening. According to a seventh aspect of the present invention, a scan line having a connection electrode is formed on a substrate, an insulating film is formed on the entire upper surface of the scan line, a plurality of pixel electrodes are arranged on the insulating film, and the scan line is connected. A contact hole is formed in the insulating film on the electrode, an opening is formed in the insulating film at a predetermined position along the peripheral portion of the pixel electrode, and a signal line is formed on the insulating film with the signal line. It is formed so that at least a part of the opening is located between the pixel electrode and the pixel electrode. According to an eighth aspect of the present invention, a scan line having a connection electrode is formed on a substrate, an insulating film is formed on the entire upper surface of the scan line, a plurality of pixel electrodes are arranged on the insulating film, and the scan line is connected. A contact hole is formed in the insulating film on the electrode, an opening is formed in the insulating film between the adjacent pixel electrodes, and a signal line narrower than the width of the opening is formed on the insulating film. It is formed so that a part thereof is located in the opening.

According to this invention, since the opening is formed in the insulating film between at least the pixel electrode and the signal line, a semiconductor thin film or an ion diffusion layer is not required on the insulating film between the pixel electrode and the signal line. Even if such a portion remains, an unnecessary portion of the semiconductor thin film or the ion diffusion layer remaining when forming the opening can be removed together with the insulating film. Therefore, it is possible to prevent the display quality from being deteriorated without causing a short circuit between the signal line and the pixel electrode due to the unnecessary portion of the remaining semiconductor thin film or ion diffusion layer. In this case, as in the third aspect of the invention, if the opening is formed in contact with the end of the pixel electrode, the aperture ratio can be prevented from being lowered. Further, according to the invention of claim 7 or 8, since the opening is formed at the same time when the contact hole is formed in the insulating film, the number of steps can be prevented from increasing.

[0011]

1 to 8 show a manufacturing process of a liquid crystal display element according to a first embodiment of the present invention. In this case, the manufacturing process of the gate line connection electrode formed at one end of the gate line and the drain line connection electrode formed at one end of the drain line is also shown. Therefore, the structure of the liquid crystal display element and the manufacturing method thereof according to the first embodiment will be described with reference to these drawings in order, and the manufacturing method of the gate line connection electrode and the drain line connection electrode will also be described. To do.

First, as shown in FIG. 1, a glass substrate 31
A gate electrode G and a gate line (scanning line) 32 made of chromium, aluminum, or the like are formed at a predetermined location on the upper surface of the substrate with a film thickness of about 1000Å. In this state, the connection pad 32a is formed at one end of the gate line 32. Next, a gate insulating film 33 made of silicon nitride or the like is formed on the upper surface of the glass substrate 31 including the gate electrode G and the gate line 32 by plasma CVD to a film thickness of 4
Film is formed to about 000Å, then plasma CV is formed on the upper surface.
By D, a semiconductor thin film 34 made of intrinsic amorphous silicon or the like is formed to a film thickness of about 500 Å, and then a channel protective film forming layer 35 made of silicon nitride or the like is formed on the upper surface thereof to a film thickness of about 1000 Å. . Next, a first photoresist pattern 36 is formed on the upper surface of the channel protective film forming layer 35 and at a predetermined position on the gate electrode G.

Next, when the channel protective film forming layer 35 is etched using the first photoresist pattern 36 as a mask, a channel protective film 37 is formed under the first photoresist pattern 36 as shown in FIG. afterwards,
The first photoresist pattern 36 is peeled off. Next, as shown in FIG. 3, an n ⁺ type silicon layer (ion diffusion layer) 38 made of n ⁺ type amorphous silicon in which phosphorus or the like is mixed by a plasma CVD method is formed on the upper surface of the semiconductor thin film 34 including the channel protective film 37. To a film thickness of 250 Å.
Next, a second photoresist pattern 39 is formed on the upper surface of the n ⁺ type silicon layer 38 on both sides of the upper surface of the channel protection film 37 at predetermined two positions.

Next, using the second photoresist pattern 39 as a mask, the n ⁺ type silicon layer 38 and the semiconductor thin film 3 are formed.
4 is removed, unnecessary portions of the n ⁺ type silicon layer 38 and the semiconductor thin film 34 are removed, and the drain region 38a and the source region 38b made of n ⁺ type silicon are formed in the device region as islands, as shown in FIG. Region 34 which is formed in a rectangular shape and is made of intrinsic silicon
a is formed. Then, the second photoresist pattern 39 is peeled off. Next, as shown in FIG. 5, a pixel electrode 40 made of ITO is formed at a predetermined position on the upper surface of the gate insulating film 33 to a film thickness of about 500 Å.

Next, when dry etching is performed using a third photoresist pattern (not shown) as a mask, as shown in FIG. 6, the gate line 32 in the gate insulating film 33 is formed.
A contact hole 33a is formed on the connection pad 32a of the pixel electrode 40, and both ends of the pixel electrode 40 are provided at predetermined positions of the gate insulating film 33 between the gate line 32 and between the pixel electrode 40 and a drain line 43 described later. An elongated hole (opening) 41 is formed parallel to the portion. in this case,
N ⁺ -type silicon layer even if the unnecessary portion of the n ⁺ -type silicon layer 38 and the semiconductor thin film 34 is left, which remains in forming the long hole 41 by dry etching between the drain line 43 and the pixel electrode 40 38 and unnecessary portions of the semiconductor thin film 34 are removed together with the gate insulating film 33. In this case, the etching gas is sulfur hexafluoride (S) which can etch the gate insulating film 33, the channel protective film forming layer 35, the n ⁺ type silicon layer 38 and the semiconductor thin film 34.
F ₆ ) or carbon tetrafluoride (CF ₄ ) or the like is used.

Next, as shown in FIG. 7, the drain region 3
8a and the source region 38b, the drain contact layer 42a and the source contact layer 42b made of chromium or the like are formed to a film thickness of about 250 Å on each upper surface,
A source electrode S and a drain electrode D made of aluminum or the like are formed on the respective upper surfaces of the drain contact layer 42a and the source contact layer 42b so as to have a film thickness of about 4000Å. In this case, at the same time, the drain line (signal line) 43 is formed at a predetermined position on the upper surface of the gate insulating film 33 via the drain line contact layer 42c, and the drain line connection electrode 43a is formed at one end of the drain line 43. The gate line connection electrode 44 is formed on the upper surface of the connection pad 32a exposed in the contact hole 33a of the gate line 32 via the gate line contact layer 42d. In this state, the drain line 43 is connected to the drain region 38a via the drain contact layer 42a and the drain electrode D, and the source region 38b is connected to the pixel electrode 40 via the source contact layer 42b and the source electrode S. There is. Further, a gate line connection electrode 44 is connected to a portion of the connection pad 32a of the gate line 32 in the contact hole 33a via a gate line contact layer 42d.

Next, as shown in FIG. 8, a passivation film (overcoat film) 45 made of silicon nitride or the like is formed at a predetermined position on the upper surface so as to have a film thickness of about 2000 Å.
In this state, the gate line connection electrode 44 and the drain line connection electrode 43 in the passivation film 45.
Apertures 45a to 45c are formed in portions corresponding to the central portions of a and the pixel electrode 40. In this case, the opening 45c is formed in the passivation film 45 at a portion corresponding to the center of the pixel electrode 40.
This is to increase the transparency above. Thus, the liquid crystal display device is completed.

As described above, the long holes 41 are formed in the gate insulating film 33 between the pixel electrode 40 and the drain lines 43 on both sides of the pixel electrode 40 in parallel with both ends of the pixel electrode 40. even if the unnecessary portions of the semiconductor thin film 34 and n ⁺ -type silicon layer 38 on the gate insulating film 33 between each of the drain lines 43 located on both sides remain, the semiconductor thin film 34 and n ⁺ -type remaining The unnecessary portion of the silicon layer 38 can be removed together with the gate insulating film 33 when forming the elongated hole 41. Therefore, the remaining semiconductor thin film 34 and the n ⁺ type silicon layer 3
It is possible to prevent the drain line 43 and the pixel electrode 40 from being short-circuited by the unnecessary portion of 8 and prevent the display quality from deteriorating. As a result, the yield of liquid crystal display elements is improved. Further, since the long hole 41 is formed at the same time as the contact hole 33a is formed in the gate insulating film 33, the number of steps can be prevented from increasing.

In the first embodiment, the long holes 41 are formed in the gate insulating film 33 between the gate lines 32 and between the pixel electrodes 40 and the drain lines 43 in parallel with both ends of the pixel electrodes 40. However, the present invention is not limited to this, and the elongated holes 52 may be formed all around the pixel electrode 40.

Next, referring to FIGS. 9 to 11 in order,
The structure of the liquid crystal display element and the method for manufacturing the same according to the second embodiment of the present invention will be described. In the second embodiment, the steps up to the step shown in FIG. Let's start with.

After the step shown in FIG. 5 of the first embodiment,
When dry etching is performed using a third photoresist pattern (not shown) as a mask, as shown in FIG. 9, the connection pad 32a of the gate line 32 in the gate insulating film 33 is formed.
A contact hole 33a is formed above, and a long hole 51 wider than the drain line 43 is formed between the gate lines 32 and in a portion corresponding to the drain line 43. In this case as well, even if unnecessary portions of the n ⁺ type silicon layer 38 and the semiconductor thin film 34 remain between the drain line 43 and the pixel electrode 40, they remain when forming the long hole 51 by dry etching. Unnecessary portions of the n ⁺ type silicon layer 38 and the semiconductor thin film 34 are removed together with the gate insulating film 33.

Next, as shown in FIG. 10, a drain contact layer 42a and a source contact layer 42b made of chromium or the like are formed on the respective upper surfaces of the drain region 38a and the source region 38b to a film thickness of about 250 Å, and the drain is formed. A source electrode S and a drain electrode D made of aluminum or the like are formed on the respective upper surfaces of the contact layer 42a for source and the contact layer 42b for source with a film thickness of about 4000Å. In this case, at the same time, the drain line 43 is formed at a predetermined position on the upper surface of the gate insulating film 33 via the drain line contact layer 42c, and the drain line connection electrode 43 is formed at one end of the drain line 43.
a is formed, and the contact hole 3 of the gate line 32 is formed.
A gate line connection electrode 44 is formed on the upper surface of the connection pad 32a exposed in 3a via a gate line contact layer 42d. In this state, the drain region 3
8a is connected to the drain line 43 via the drain contact layer 42a and the drain electrode D, and the source region 38b is connected to the pixel electrode 40 via the source contact layer 42b and the source electrode S. Further, a gate line connection electrode 44 is connected to a portion of the connection pad 32a of the gate line 32 in the contact hole 33a via a gate line contact layer 42d.

Next, as shown in FIG. 11, a passivation film (overcoat film) 45 made of silicon nitride or the like is formed at a predetermined position on the upper surface so as to have a film thickness of about 2000 Å. In this state, openings 45a to 45c are formed in portions of the passivation film 45 corresponding to the central portions of the gate line connection electrode 44, the drain line connection electrode 43a, and the pixel electrode 40, respectively. In this case, the reason why the opening 45c is formed in the portion of the passivation film 45 corresponding to the center of the pixel electrode 40 is to increase the transparency on the pixel electrode 40. Thus, the liquid crystal display device is completed.

Since the elongated hole 51 having a width wider than that of the drain line 43 is formed in the portion of the gate insulating film 33 corresponding to the drain line 43, the gate insulation between the pixel electrode 40 and the drain line 43 is performed. Even if unnecessary portions of the semiconductor thin film 34 and the n ⁺ type silicon layer 38 remain on the film 33, the remaining semiconductor thin film 34 and n
The unnecessary portion of the ⁺ type silicon layer 38 can be removed together with the gate insulating film 33 when forming the long hole 51.
Therefore, the drain line 43 and the pixel electrode 40 are not short-circuited by unnecessary portions of the remaining semiconductor thin film 34 and the n ⁺ -type silicon layer 38, and the display quality can be prevented from deteriorating. As a result, the yield of liquid crystal display elements is improved. Further, since the long hole 51 is formed at the same time as the contact hole 33a is formed in the gate insulating film 33, the number of steps can be prevented from increasing. Further, since the long hole 51 is formed in the portion of the gate insulating film 33 corresponding to the drain line 43, it is not necessary to secure a large space for forming the long hole 51 between the drain line 43 and the pixel electrode 40. It is possible to prevent the aperture ratio from lowering.

Next, referring to FIGS. 12 to 14 in order, the structure of the liquid crystal display element and the method for manufacturing the same according to the third embodiment of the present invention will be described. In the third embodiment, the first embodiment will be described. Since the steps up to the step shown in FIG. 5 are the same, the steps thereafter will be described.

After the step shown in FIG. 5 of the first embodiment,
When dry etching is performed using a third photoresist pattern (not shown) as a mask, as shown in FIG. 12, a contact hole 33a is formed in a portion of the gate insulating film 33 corresponding to the external connection pad 32a of the gate line 32, and the gate line 33a is formed. Slots 52 are formed between the pixel electrodes 40 and the drain lines 43 at predetermined positions between the pixel electrodes 40 and the drain lines 43 along both ends of the pixel electrodes 40. In this case as well, even if unnecessary portions of the n ⁺ type silicon layer 38 and the semiconductor thin film 34 remain between the drain line 43 and the pixel electrode 40, they remain when the long hole 52 is formed by dry etching. N ⁺
Unnecessary portions of the type silicon layer 38 and the semiconductor thin film 34 are removed together with the gate insulating film 33.

Next, as shown in FIG. 13, a drain contact layer 42a and a source contact layer 42b made of chromium or the like are formed on the upper surfaces of the drain region 38a and the source region 38b to a film thickness of about 250 Å, and the drain is formed. A source electrode S and a drain electrode D made of aluminum or the like are formed on the respective upper surfaces of the contact layer 42a for source and the contact layer 42b for source with a film thickness of about 4000Å. In this case, at the same time, the drain line 43 is formed at a predetermined position on the upper surface of the gate insulating film 33 via the drain line contact layer 42c, and the drain line connection electrode 43 is formed at one end of the drain line 43.
a is formed, and the contact hole 3 of the gate line 32 is formed.
A gate line connection electrode 44 is formed on the upper surface of the connection pad 32a exposed in 3a via a gate line contact layer 42d. In this state, the drain region 3
8a is connected to the drain line 43 via the drain contact layer 42a and the drain electrode D, and the source region 38b is connected to the pixel electrode 40 via the source contact layer 42b and the source electrode S. Further, a gate line connection electrode 44 is connected to a portion of the connection pad 32a of the gate line 32 in the contact hole 33a via a gate line contact layer 42d.

Next, as shown in FIG. 14, a passivation film (overcoat film) 45 made of silicon nitride or the like is formed at a predetermined position on the upper surface so as to have a film thickness of about 2000 Å. In this state, openings 45a to 45c are formed in portions of the passivation film 45 corresponding to the central portions of the gate line connection electrode 44, the drain line connection electrode 43a, and the pixel electrode 40, respectively. In this case, the reason why the opening 45c is formed in the portion of the passivation film 45 corresponding to the center of the pixel electrode 40 is to increase the transparency on the pixel electrode 40. Thus, the liquid crystal display device is completed.

As described above, since the long holes 52 are formed in the gate insulating film 33 between the pixel electrode 40 and the drain lines 43 on both sides thereof in contact with both ends of the pixel electrode 40, the pixel electrode 40 and both sides thereof are formed. Even if unnecessary portions of the semiconductor thin film 34 and the n ⁺ -type silicon layer 38 remain on the gate insulating film 33 between the drain line 43 and the drain line 43, the remaining semiconductor thin film 34 and the n ⁺ -type silicon layer 38 The unnecessary portion can be removed together with the gate insulating film 33 when forming the elongated hole 52. Therefore, the drain line 43 and the pixel electrode 40 may be removed by unnecessary portions of the remaining semiconductor thin film 34 and the n ⁺ type silicon layer 38.
Therefore, it is possible to prevent the display quality from deteriorating because there is no short circuit between them. As a result, the yield of liquid crystal display elements is improved. Further, since the elongated hole 52 is formed at the same time as the contact hole 33a is formed in the gate insulating film 33, the number of steps can be prevented from increasing. Furthermore, since the long holes 52 are formed along both ends of the pixel electrode 40, it is possible to prevent the aperture ratio from decreasing, and the drain line 43 does not get over the long holes 52.
There is no risk of disconnection due to the drain line 43 bending at the end of the elongated hole 52.

In the third embodiment, the long holes 52 are formed in the gate insulating film 33 between the gate lines 32 and between the pixel electrodes 40 and the drain lines 43 along both ends of the pixel electrodes 40. However, the present invention is not limited to this, and the elongated holes 52 may be formed all around the pixel electrode 40. In addition, in the above-described first to third embodiments, the long holes 41, 51, and 52 penetrating the gate insulating film 33 and reaching the glass substrate 31 are described as the openings, but the present invention is not limited to this, and the remaining n ⁺ -type is used. It may be a long groove in which the upper portion of the gate insulating film 33 is shaved off to the extent that unnecessary portions of the silicon layer 38 and the semiconductor thin film 34 can be removed.

[0031]

As described above, according to the present invention, since the opening is formed in the insulating film at least between the pixel electrode and the signal line, the insulating film is formed on the insulating film between the pixel electrode and the signal line. Even if an unnecessary portion of the semiconductor thin film or the ion diffusion layer may remain, the unnecessary portion of the semiconductor thin film or the ion diffusion layer remaining when forming the opening can be removed together with the insulating film. Therefore, it is possible to prevent the display quality from being deteriorated without causing a short circuit between the signal line and the pixel electrode due to the unnecessary portion of the remaining semiconductor thin film or ion diffusion layer. In this case, as in the third aspect of the invention, since the opening is formed in contact with the end of the pixel electrode, the aperture ratio can be prevented from being lowered. Further, according to the invention of claim 7 or 8, since the opening is formed at the same time when the contact hole is formed in the insulating film, the number of steps can be prevented from increasing.

[Brief description of drawings]

FIG. 1A is a plan view showing a state in which a semiconductor thin film, a channel protective film forming layer, and a photoresist pattern are sequentially formed on a glass substrate in manufacturing the liquid crystal display element according to the first embodiment of the present invention. 7B is a sectional view taken along the line BB, and FIG. 9C is a sectional view taken along the line CC.

2 is a step following FIG. 1, in which (A) is a plan view, FIG.
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 3 is a step following FIG. 2, in which (A) is a plan view;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 4 is a step following FIG. 3, in which (A) is a plan view;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

5 is a step following FIG. 4, in which (A) is a plan view, FIG.
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 6 is a step following FIG. 5, in which (A) is a plan view;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 7 is a step following FIG. 6, in which (A) is a plan view;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 8 is a step following FIG. 7, in which (A) is a plan view;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 9 is a step following the step of FIG. 5 of the first embodiment in manufacturing the liquid crystal display element according to the second embodiment of the present invention, in which (A) is a plan view and (B) is a line BB thereof. The sectional view which follows, (C) is the sectional view which follows the CC line.

10 is a step following FIG. 9, in which (A) is a plan view,
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 11 is a step following FIG. 10, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 12 is a step following the step of FIG. 5 of the first embodiment in manufacturing the liquid crystal display element according to the third embodiment of the present invention, in which (A) is a plan view and (B) is a line BB thereof. The sectional view which follows, (C) is the sectional view which follows the CC line.

FIG. 13 is a step following FIG. 12, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 14 is a step following FIG. 13, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 15 is a plan view showing a state in which a semiconductor thin film, a channel protective film forming layer, and a photoresist pattern are sequentially formed on a glass substrate in manufacturing a conventional liquid crystal display element;
(B) is a sectional view taken along the line BB, and (C) is its C-
Sectional drawing which follows the C line.

FIG. 16 is a step following FIG. 15, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 17 is a step following FIG. 16, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 18 is a step following FIG. 17, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 19 is a step following FIG. 18, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

FIG. 20 is a step following FIG. 19, in which (A) is a plan view, (B) is a sectional view taken along the line BB, and (C) is a sectional view taken along the line CC.

21 is a step following FIG. 20, in which (A) is a plan view, (B) is a cross-sectional view taken along the line BB, and (C) is a cross-sectional view taken along the line C-C.

[Explanation of symbols]

31 glass substrate 32 gate line 33 gate insulating film 33a contact hole 34 semiconductor thin film 38 n ⁺ type silicon layer 40 pixel electrode 41 long hole 43 drain line G gate electrode S source electrode D drain electrode

Claims (8)

[Claims] 1. A liquid crystal display device having a pixel electrode and a signal line formed on an insulating film, wherein an opening is formed at least in the insulating film between the pixel electrode and the signal line. Liquid crystal display device. 2. A liquid crystal display device having a plurality of signal lines arranged on an insulating film and pixel electrodes formed between the signal lines, wherein the pixel electrodes and the signals located on both sides thereof are provided. A liquid crystal display element, wherein an opening is formed in the insulating film between the line and the line. 3. The liquid crystal display element according to claim 1, wherein the opening is formed in contact with an end of the pixel electrode. 4. A liquid crystal display device having a plurality of signal lines arranged and formed on an insulating film, and a pixel electrode formed between each of the signal lines, wherein the pixels adjacent to each other in the arrangement direction of the signal lines. A liquid crystal display element, wherein an opening having a width wider than that of the signal line is formed in the insulating film between electrodes, and a part of the signal line is located in the opening. 5. A plurality of pixel electrodes are formed in an array on an insulating film, an opening is formed in the insulating film at a predetermined position along a peripheral portion of the pixel electrode, and a signal line is formed on the insulating film. A method of manufacturing a liquid crystal display device, characterized in that at least a part of the opening is formed between a signal line and the pixel electrode. 6. A plurality of pixel electrodes are arranged in an array on an insulating film, an opening is formed in the insulating film between adjacent pixel electrodes, and the opening is narrower than the width of the opening on the insulating film. The method of manufacturing a liquid crystal display element, wherein the signal line is formed so that a part thereof is located in the opening. 7. A scan line having a connection electrode is formed on a substrate, an insulating film is formed on the entire upper surface of the scan line, and a plurality of pixel electrodes are formed in an array on the insulating film. A contact hole is formed in the insulating film, an opening is formed in the insulating film at a predetermined location along the peripheral portion of the pixel electrode, and a signal line is formed on the insulating film with the signal line and the pixel electrode. A method for manufacturing a liquid crystal display element, characterized in that at least a part of the opening is formed between the two. 8. A scan line having a connection electrode is formed on a substrate, an insulating film is formed on the entire upper surface of the scan line, and a plurality of pixel electrodes are formed in an array on the insulating film. A contact hole is formed in the insulating film, an opening is formed in the insulating film between the adjacent pixel electrodes, and a signal line whose width is narrower than the width of the opening is partially formed on the insulating film. Is formed so as to be located inside the opening.