JPH09326962A - Digital camera - Google Patents

Abstract

(57) Abstract: A digital camera that sets a black level correctly and efficiently generates a video signal even when the video signal is transmitted at a low speed. SOLUTION: A digital camera for picking up an image by a CCD is provided with an OB detection section for calculating a difference value between a D-RAM and a CCD optical black average value and a predetermined black level value. The output signal is stored in the D-RAM, and in parallel with this, O
The difference value is calculated by the B detection unit. The calculated difference value is D-
The signal of one field is held while being read from the RAM, the read signal is corrected by the difference value, and a video signal is generated from the corrected signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera used for image input of a personal computer, a videophone or the like, and more particularly to a black level setting of the digital camera.

[0002]

2. Description of the Related Art In a digital camera for picking up an image by a photoelectric conversion element (CCD), in order to clamp a black level of an image to a constant value, optical black signal values provided outside a light receiving area of the CCD are integrated and averaged. The value is calculated, the difference between the average value and the predetermined value of the black level is calculated as the correction amount, and the correction process is performed to subtract the correction amount from the output of the light receiving area. For example, if the black level is set to 64,
If the average value in optical black is 66, the difference 2 is subtracted from the output value of the light receiving area. As a result, the output of the CCD used to generate the video signal is corrected and the black level becomes 64.

Conventionally, the correction amount is calculated from the output of the optical black one field before and the correction is sequentially performed for each field, or the correction amount is calculated from the output of the optical black two fields before and the odd field is calculated. And the even fields are sequentially corrected for each frame.

By the way, a digital camera performs photoelectric conversion by a CCD and processing of its output signal at a constant speed, for example, 60 fields per second to generate a video signal. The video signal is sent from an external interface to an external device such as a personal computer, but the sending speed needs to match the processing speed of the external device and does not necessarily match the signal processing speed of the digital camera.

When the external device requires an input at a speed lower than the processing speed of the camera, that is, when the number of fields of the video signal transmitted from the camera needs to be less than the number of fields to be generated, the camera is limited to some fields. The speed is adjusted by not sending. This speed adjustment is performed by an external interface, and in the conventional digital camera, even when outputting at a low speed, the video signals of all fields are once generated and the fields that are not transmitted are discarded.

FIG. 18 shows the configuration of a conventional digital camera. The output of the CCD provided in the image pickup unit 211 is subjected to processing such as automatic gain control (AGC) by the preprocessing unit 212, and converted into a digital signal by the AD conversion unit 213. The digital signal is subjected to the black level clamp processing or the like in the video signal processing unit 214, and then becomes a video signal composed of a luminance signal and a color signal. The video signal is temporarily stored in the storage unit 215, and the external interface 216
Is read out and sent to an external device (not shown).

The control unit 217 includes a drive unit 218 for driving the CCD, an AD conversion unit 213, and a video signal processing unit 21.
4 is controlled to generate a video signal at a constant speed. The control unit 217 also gives an instruction to the external interface 216 to read the video signal from the storage unit 215 and to send it to the outside, so that only the video signals of some fields are sent to the external device.

In the above-mentioned camera, a video signal is generated for a field that is discarded without being transmitted, similarly to the field that is transmitted. Therefore, the correction amount for setting the black level can be obtained from the optical black outputs of all the fields, and the correction can always be performed using the optical black outputs of one field or two fields before. .

When providing a color image, each pixel of the CCD is made to correspond to one of three colors of R, G and B by a filter, and an image signal of one pixel is output value of several pixels located in the vicinity of the pixel. Generate from. At this time, it is necessary to simultaneously output signals from the CCD over a plurality of lines, and conventionally, a line memory is used to adjust the input timing of the plurality of lines to the video signal processing unit. FIG. 19 shows an example of the configuration. In this example, one line of a video signal is generated from an output signal of three lines of CCD, and two line memories 91 and 92 are used for synchronizing three lines.

[0010]

In the conventional digital camera, since the black level of each field is set based on the correction amount obtained from the output of the field before that field, strictly speaking, the correct black level is set. There is a problem that the setting is not made and a subtle error occurs in the video signal.

If the sending speed is slower than the generation speed of the video signal, the video signal of a part of the field is discarded and the wasteful processing of generating the discarded video signal is performed. . In order to avoid this wasteful processing and efficiently process the signal, the generated video signal should not be discarded, but the output of the CCD itself should be discarded. Then, the correction amount for setting the black level is set. Some fields cannot be calculated. Moreover,
The control becomes extremely complicated because the signal processing cannot be performed at a constant speed.

It is an object of the present invention to provide a digital camera which sets a black level correctly and efficiently generates a video signal even when transmitting at a low speed.

[0013]

In order to achieve the above object, the present invention has a photoelectric conversion element that outputs a signal according to the amount of received light, and outputs a video signal from the output signal of the light receiving area of the photoelectric conversion element. In a digital camera that generates and sets the reference level of the output signal of the light receiving area based on the output signal outside the light receiving area, the reference level of one field of the output signal of the light receiving area becomes the output signal outside the light receiving area of the same field. Set based on

The photoelectric conversion element outputs a signal not only from the light receiving area but also from outside the light receiving area. The output signal of the photoelectric conversion element has a value that changes according to the amount of received light, but it has a certain value even when no light is received. The value is output as a signal outside the light receiving area. By setting the reference level of the output signal of the light receiving area based on the output signal of the outside of the light receiving area, the displacement amount from the reference level of the output signal of the light receiving area represents the light receiving amount. The output value of the photoelectric conversion element when it does not receive light varies depending on environmental conditions such as temperature, but by setting the reference level of one field of the output signal of the light receiving area based on the output signal of the same field outside the light receiving area. Therefore, the correct reference level is always set regardless of the change in the environmental conditions, and the video signal is generated from the signal indicating the true light receiving amount.

The above digital camera may be a camera which sends a video signal to the outside at a speed slower than the speed at which the photoelectric conversion element outputs the signal. For example, when the photoelectric conversion element outputs at a rate of 60 fields per second, the number of sending fields of the video signal per second is set to be less than 60. This sending speed is set according to the receiving ability of the external device that receives the video signal. Also at this time, since the reference level of the light receiving area is set based on the output signal outside the light receiving area of the field, the video signal is generated from the signal indicating the true light receiving amount.

In the digital camera, specifically, the output signal of the photoelectric conversion element is temporarily stored in the storage means,
The output signal of the photoelectric conversion element stored in the storage means is read out and the video signal is generated by the video signal processing means.
While the output signal of the photoelectric conversion element is being stored in the storage means, processing such as obtaining the average value of the output signals outside the light receiving area is performed, and then the output signal of the light receiving area is read from the storage means to set the reference level. Processing can be performed. A video signal is generated from the signal after setting the reference level.

In the digital camera, the AD conversion means for converting the analog output signal of the photoelectric conversion element into a digital signal and writing the digital signal in the storage means, and the writing of the AD conversion means into the storage means are controlled and stored in the storage means. Storage control means for reading out the digital signal. The output signal of the photoelectric conversion element is converted into a digital signal suitable for storage by the AD conversion means and stored in the storage means. The storage control means controls the writing and also reads out a signal from the storage means.

The digital camera further stores a predetermined value corresponding to the reference level of the video signal, and is provided with an output signal outside the light receiving area of the photoelectric conversion element which is converted into a digital signal by the AD conversion means, and is output outside the light receiving area. The level difference detecting means for calculating the average value of the signals in the predetermined area in the above, and obtaining and storing the difference value between the average value and the predetermined value, the digital signal read by the storage control means and the level difference detecting means are stored. The level difference adjusting means for adding or subtracting the difference value to or from the given digital signal and outputting the signal after the calculation to the video signal processing means.

The difference value between the average value of the signal in a predetermined area outside the light receiving area of the photoelectric conversion element and the predetermined value corresponding to the reference level of the video signal is a correction amount for setting the level of the light receiving area. By adding or subtracting this correction amount to the signal of the light receiving area, the reference level of the signal value of the light receiving area becomes a predetermined value, and the amount of displacement from the reference level of each signal value represents the true light receiving quantity. Become. The video signal processing means generates a video signal from the signal representing the true amount of received light. The level difference detecting means stores the calculated difference value and holds it while adding or subtracting the signal of one field.

In order to achieve the above object, the present invention provides
A photoelectric conversion element that outputs an analog signal according to the amount of received light to a digital camera, an AD conversion unit that converts the output signal of the photoelectric conversion element into a digital signal and outputs the digital signal, and a photoelectric conversion element of the output signals of the AD conversion unit Of the signal of the light receiving area, storage control means for controlling the writing of the output signal of the AD conversion means to the signal storage means and reading out the signal stored in the signal storage means, and the AD conversion means. Among the output signals, an average value calculating means for calculating and outputting an average value of a signal of a predetermined area outside the light receiving area of the photoelectric conversion element, and a predetermined value stored, and an average value output from the average value calculating means. A difference value holding means for calculating and holding a difference value with respect to a predetermined value, and a signal read from the signal storage means by the storage control means to change the value of the signal by the difference value held by the difference value holding means. A video signal generating means for generating a video signal from the output signal of the signal value adjusting means, and a video signal transmitting means for transmitting the video signal generated by the video signal generating means to the outside. Prepare

The analog output signal of the photoelectric conversion element is AD
Converted into a digital signal, the signal of the light receiving region of the photoelectric conversion element is stored in the signal storage means,
The signal outside the light receiving area is given to the average value calculating means. The average value calculating means calculates the average value of the signal values in the predetermined area and outputs it to the difference value holding means. The difference value holding means stores a predetermined value, and calculates and holds the difference value between the average value given by the average value calculation means and the predetermined value. The calculation of the average value and the difference value by the average value calculation means and the difference value holding means is performed in parallel with the storage of the signal of the light receiving region in the signal storage means.

The signal stored in the signal storage means is read by the storage control means and given to the signal value adjusting means, and the value can be changed by the difference value held by the difference value holding means. Here, the signal whose value can be changed by the signal value adjusting means is a signal in the same field as the field for which the difference value was obtained, and all signals in the light receiving area in that field are the predetermined values stored in the difference value holding means. It will be the standard value. A video signal for one field is generated by the video signal generating means from the signal in the light receiving area for which the reference value is set in this way, and the generated video signal is sent to an external device by the video signal sending means.

In the above digital camera, the difference value held by the difference value holding means is not updated until the storage control means completes reading the signal of one field from the signal storage means.

While the storage control means is reading a signal from the signal storage means, photoelectric conversion by the photoelectric conversion element, conversion of the output signal into a digital signal by the AD conversion means,
The signal storage means stores the signal of the light receiving area and the average value calculating means calculates the average value of a predetermined area outside the light receiving area. The difference value holding means calculates the difference value between the average value given by the average value calculation means and the predetermined value, but does not update the held difference value with a new difference value at the same time as the calculation.
The difference value holding means updates the difference value after waiting for the storage control means to read the signal of one field from the signal storage means. Therefore, the difference value does not change while the signal value adjusting means is processing the signal of one field, and the change amounts of the signal value of one field are all the same.

The reading speed of the signal from the signal storage means by the storage control means is the same as the sending speed of the video signal from the video signal sending means. When the video signal is sent at a low speed, the reading of the signal by the storage control means and the processing of the signal value adjusting means are also slowed down, but even in this case, the signal value of one field changes by the same amount.

Specifically, a flip-flop for inputting the calculated difference value to the difference value holding means is provided, and the difference value is written to the flip-flop when the photoelectric conversion element finishes outputting the signal of one field. Then, the write control clock of the flip-flop is prohibited until the storage control means completes reading the signal of one field from the signal storage means.

Even when the photoelectric conversion element has finished outputting the signal of one field, if the write clock of the flip-flop is prohibited, the difference value is not written to the flip-flop. The difference value held by the difference value holding means is
It is updated when the photoelectric conversion element finishes outputting the signal of 1 field after the storage control means completes reading the signal of 1 field.

In the above digital camera, wherein the video signal generating means generates the video signal of one line from the signals of a plurality of lines, the signal value adjusting means adds or subtracts the signal given from the storage controlling means and the difference value. The storage control means reads out signals of a plurality of lines from the signal storage means and gives them to the signal value adjusting means, and the signal value adjusting means sequentially adds and subtracts the signals given from the storage controlling means. To perform calculations using a container.

The signal value adjusting means is supplied with signals of a plurality of lines from the storage controlling means, and the signal value adjusting means sequentially processes the signals of these lines with only one adder / subtractor. By the process of adding or subtracting the difference value, the value of the signal in the light receiving region is changed by the difference value, and the reference is set to the predetermined value stored in the difference value holding means. The image generating means generates one line of the image signal from the signals of the plurality of lines after the reference setting.

In the digital camera, wherein the video signal generating means generates the video signal of one line from the signals of a plurality of lines, the signal value adjusting means adds or subtracts the signal given from the storage controlling means and the difference value. The storage control means sequentially reads signals of a plurality of lines from the signal storage means and gives them to the signal value adjusting means, and the signal value adjusting means is the storage control means from the signal storing means to the next signal. It is also possible to perform the arithmetic operation by the adder / subtractor on one signal given from the storage control means while reading out.

The signal value adjusting means adds or subtracts the difference value to or from the signals of a plurality of lines sequentially given from the storage control means by means of only one adder / subtractor, and the reference of the signal is stored in the predetermined value stored in the difference value holding means. Set to the value. At this time, the reading of the signal from the signal storage means by the storage control means and the addition or subtraction operation of the signal value adjusting means are performed in parallel, until the storage control means finishes reading all the signals of the plurality of lines. The signal value adjusting means does not have to wait for the calculation.

Specifically, the storage control means is provided with a flip-flop for fetching the signal read from the signal storage means, and when the signal value adjusting means finishes the calculation for one signal, the next signal is fetched in the flip-flop. To the signal value adjusting means.

In the digital camera, wherein the AD conversion means outputs a signal having a bit number larger than the number of bits constituting one storage unit of the signal storage means, the difference of the difference value holding means is added to the signal value adjusting means. A value is divided into a signal having the same number of bits as one storage unit and the divided signal is selected and output, and addition of the signal given from the storage control means and the output signal of the difference value dividing means or The storage control means is provided with a signal storage unit for adding and subtracting one storage unit for performing subtraction, and an adder / subtractor having the same number of bits, and a carry storage unit for storing and storing a carry stored in the arithmetic operation of the adder / subtractor. The signal read from the means and the read address are given to the signal value adjusting means, and the signal of the difference value dividing means is selected on the basis of this address and the carry storage means to the adder / subtractor. So as to control the provision of carry.

The signal storage means stores the output signal of the AD conversion means by dividing it by the number of bits of one storage unit of its own.
The average value calculation means and the difference value holding means perform the calculation with the same number of bits as the output signal of the AD conversion means. Therefore, the difference value held by the difference value holding means also has the same number of bits as the output signal of the AD conversion means. On the other hand, the storage control means gives the signal of the number of bits of one storage unit read from the signal value adjusting means to the signal value adjusting means. The signal value adjusting means divides the difference value into a signal having a bit number of one storage unit by the difference value dividing means in order to add or subtract two signals having different bit numbers. The adder / subtractor also has the same number of bits as the number of bits in one storage unit, and a carry to be given to a signal of higher bits may occur in the operation of the adder / subtractor. This carry is stored in the carry storage means.

The adder / subtractor performs processing as to which of the divided signals is selected by the difference value dividing means and output to the adder / subtractor, and whether the carry stored in the carry storage means is given to the adder / subtractor. It is necessary to decide according to the upper and lower levels of the signal. That is, when the number of bits of the output signal of the AD conversion means is twice the number of bits of one storage unit of the signal storage means, the number of bits of the output signal of the AD conversion means is separately set for the upper signal and the lower signal. When the number of bits of one storage unit of the signal storage means is three times or more, the outputs of the difference value dividing means and the carry storage means must be controlled separately in consideration of the intermediate signal. According to the address of the signal read from the signal storage means by the storage control means, the higher order,
It is possible to discriminate between middle and low order, and the above control is performed based on this.

In the above digital camera, specifically, the AD conversion means outputs a signal having a bit number twice as many as the number of bits constituting one storage unit of the signal storage means, and the signal storage means outputs 1 signal of the AD conversion means. One output signal is divided into two and stored at adjacent addresses, and the storage control means gives the value of the least significant bit of the read address to the signal value adjusting means,
The difference value dividing means selects the signal after division according to the value of the given bit, and the carry storage means provides the carry to the adder / subtractor and stops it according to the value of the given bit. .

The output signals of the AD conversion means are upper and lower 2
It is divided into one signal and stored in the signal storage means. At this time, since the higher-order signal and the lower-order signal are stored in the adjacent addresses, the odd / even of the address value is determined depending on whether it is the higher-order signal or the lower-order signal. The oddness of the address value is represented by the least significant bit, and by giving the least significant bit of the address to the signal value adjusting means together with the signal read by the storage control means, the signal value adjusting means determines whether the upper signal or the lower signal. Know if given In accordance with the value of the least significant bit, the difference value dividing means selects the difference value divided into two, and the carry storing means carries out and stops the carry,
The calculation by the adder / subtractor is properly performed.

In the digital camera in which the AD conversion means outputs a signal having a number of bits larger than the number of bits constituting one storage unit of the signal storage means, the signal value adjusting means is supplied from the storage control means. Signal reproducing means for reproducing and outputting a signal having the same number of bits as the output of the AD converting means from a plurality of signals of one storage unit, and addition or subtraction of the output signal of the signal reproducing means and the difference value of the difference value holding means. An adder / subtractor having the same number of bits as the output of the AD conversion means for performing

When the AD conversion means outputs a signal having a number of bits larger than the number of bits constituting one storage unit of the signal storage means, as described above, the signal value adjusting means is operated by the storage control means to perform the calculation. The number of bits of the given signal and the difference value held by the difference value holding means must be the same.
The signal reproduction means reproduces a signal having the same number of bits as the output signal of the AD conversion means, that is, a signal having the same number of bits as the difference value from a plurality of signals of one storage unit given from the storage control means. The adder / subtractor has the same number of bits as the output of the AD conversion means, and adds or subtracts the output signal of the signal reproduction means and the difference value of the difference value holding means as they are to obtain a reference for the signal in the light receiving region of the photoelectric conversion element. Is a predetermined value stored in the difference value holding means.

[0040]

1 is a block diagram of the configuration of a first embodiment of a digital camera of the present invention. In FIG. 1, reference numeral 11 denotes an image pickup unit including a CCD 10, and light from a subject is imaged on a light receiving surface of the CCD 10 by an image pickup lens (not shown). CCD 10 performs photoelectric conversion,
It outputs an electrical signal according to the amount of received light.

FIG. 2 schematically shows the light receiving surface of the CCD 10. The CCD 10 has a light receiving area 31 at the center,
The light that has passed through the imaging lens and is incident is received by the light receiving region 31. Areas 32 on both sides of the light receiving area 31 are shielded from light, and an optical black 33 is provided on a part thereof. Here, the light receiving area 31 is set to a size of 362 horizontal pixels × 492 vertical pixels, and the optical black 33 is set to a size of 4 horizontal pixels × 128 vertical pixels. CCD
10 outputs signals not only from the light receiving area 31 but also from outside the light receiving area 32.

Reference numeral 19 is a drive unit for driving the CCD 10. The drive unit 19 supplies drive power to the CCD 10 and gives a field shift pulse S1 for instructing the start of photoelectric conversion and the output of charges accumulated by photoelectric conversion. Here, the period of the field shift pulse is 1/6
It is set to 0 seconds, in other words, the CCD 10 is 6 seconds per second.
The photoelectric conversion is performed 0 times and a 60-field signal is output.

Reference numeral 12 is a pre-processing unit that samples and holds the output signal of the CCD 10 and performs processing such as AGC. Thirteen
Is an AD conversion unit that converts an analog signal output from the preprocessing unit 12 into a digital signal. The AD conversion unit 13 converts the output signal of the entire area of the CCD 10 given by the preprocessing unit 12 in pixel units. Reference numeral 14 is a storage unit that stores a digital signal output from the AD conversion unit 13, and here, a dynamic random access memory (D-RAM) is adopted. The storage unit 14 stores the signal from the light receiving region 31 of the CCD 10 among the output signals of the AD conversion unit 13.

Reference numeral 15 is a storage control unit for controlling the input / output of the storage unit 14. The storage control unit 15 manages the address of the storage unit 14, controls the writing of the output signal of the AD conversion unit 13 into the storage unit 14, and reads the signal stored in the storage unit 14.

Reference numeral 17 denotes an optical black detector for processing the output signal from the optical black 33 provided outside the light receiving area of the CCD 10 in order to set the black level of the output signal of the CCD 10 (hereinafter referred to as OB detector). That). The OB detector 17 has a CC from the AD converter 13.
Although the signals of the entire area of D10 are given, the OB detection unit 17
Among these, the output signal from the optical black 33 is extracted, the sum of the signal values is calculated, and the average value is calculated. The OB detector 17 holds a predetermined value as the value of the black level to be set, and subtracts this predetermined value from the calculated average value to obtain a correction amount for correcting each value of the output signal of the CCD 10. .

Reference numeral 16 is a correction unit for correcting the value of the signal read from the storage unit 14 by the storage control unit 15 with the correction amount calculated by the OB detection unit 17. Reference numeral 18 denotes a video signal processing unit that generates a video signal by subjecting the signal corrected by the correction unit 16 to γ conversion, white balance conversion, conversion into a luminance / color difference (Y / C) signal, and the like. Storage controller 15
The processing operation is controlled by the control signal S2 given from Reference numeral 21 is a sending unit for sending the generated video signal to an external device (not shown). The sending unit 21 sends the control signal S3 requesting new data for sending to the outside to the storage control unit 15
Output to

Reference numeral 20 denotes a control unit, which applies a control signal S4 to the drive unit 19 to control the operation of the CCD 10 via the drive unit 19 and causes the video signal processing unit 18 to generate parameters such as conversion coefficients necessary for generating a video signal. Donate S5. The control unit 20 is provided with a clock generation unit 22, and the timing of the digital camera is controlled based on various clock signals generated by the clock generation unit 22. For example, the storage control unit 15 may use the storage unit 14 based on the data clock DCLK.
Is controlled to read the signal value of one pixel in one cycle of the data clock DCLK.

The setting of the black level of the output signal of the CCD 10 in the digital camera having the above structure will be described below. As described above, the optical black 33 has a size of 4 pixels × 128 lines, and its signal value is processed by the OB detection unit 17. For this processing, the drive unit 19 outputs the control signal S6 to the OB detection unit 17. Control signal S
6 has four signals PH4 and PR in addition to the vertical synchronizing signal VD.
4, LH128 and LR128. These four
The signal timing is shown in FIGS. 3 (a) and 3 (b). Signals PH4 and PR4 are for respectively instructing the integration of the horizontal 4 pixels of the output signal of the optical black 33 and an instruction for clearing the integration, and signals LH128 and LR12.
8 is the vertical 128 of the signal value of the integrated 4 pixels
It is for giving an instruction to integrate the lines and an instruction to clear the integration.

FIG. 4 shows the configurations of the OB detection unit 17 and the correction unit 16. An adder 41 and a register 42 are provided to integrate the horizontal 4 pixels of the optical black 33, and an adder 43 to integrate the vertical 128 lines.
And a register 44 are provided. AD for the adder 41
The output signal of the conversion unit 13 is given, and the signals PH4 and PR
4, LH128 and LR128 determine the total sum of the output signals of the optical black 33, and register 4
It is output from 4.

This total sum is divided by the average value calculation circuit 45 to obtain an average value, which is input to the subtractor 46. The subtractor 46 sets the black level value to be set (64 here)
Is subtracted from the average value to calculate a difference value which is a correction amount. This difference value is input to the latch circuit 47 composed of a flip-flop and latched by the vertical synchronizing signal VD so as not to change for one vertical period. The above is the configuration and operation of the OB detection unit 17.

The correction section 16 is composed of an adder / subtractor 48, and is given the signal read from the storage section 14 by the storage control section 15 and the output signal of the latch circuit 47. The adder / subtractor 48 adds or subtracts the difference value, which is the output of the latch circuit 47, to the signals sequentially given from the storage controller 15, and outputs the difference value to the video signal processor 18. By this process, the CCD 10
The value of the output signal of the light receiving area 31 of is corrected and the black level is set to a predetermined value.

The output signal of the AD conversion unit 13 is written in the storage unit 14 on the one hand, and is applied to the OB detection unit 17 on the other hand to be used for calculating the difference value for setting the black level. These processes are performed in parallel. Is done. As described above, the storage control unit 15 controls the writing to the storage unit 14, and when the writing of the signal for one field is completed, the reading of the signal of the field and the supply to the adder / subtractor 48 are started. To do. At this point, the difference value calculated by the OB detector 17 has already been completed, and the latch circuit 47 outputs the difference value calculated from the optical black 33 of the field. Therefore, the black level of the signal of one field is set based on the output of the OB detector 17 of that field.

A video of one field is generated by the video signal processing unit 18 from the signal whose level is set in this way. The generated video signal is sequentially transmitted from the transmission unit 21 to the external device. The above digital camera performs photoelectric conversion of 60 fields per second to generate video signals of all fields and outputs video signals of all fields. If the sending speed of the video signal is fast and one field can be sent within the one field imaging period, this does not cause a problem.

However, depending on the external device, the speed at which the video signal is received may be slow, and the time required to send the video signal for one field may extend over a plurality of fields for image pickup by the CCD 10. In that case, the storage controller 15 reads the signal in accordance with the sending speed. However, in the above process, the latch circuit 47 receives the next vertical synchronizing signal V while reading one field.
D will be given, and this will change the correction amount, and the signal value will be incorrect. The second embodiment for dealing with this inconvenience will be described below.

The basic structure of the digital camera of the second embodiment is almost the same as that shown in FIG. 1, and the duplicated description will be omitted. In the present embodiment, a clock enable is provided to the flip-flops that form the latch circuit of the OB detection unit 17, and the end of the reading of the signal for one field from the storage unit 14 is detected, and the clock is supplied until this detection is performed. The configuration is such that enable is prohibited and clock enable is allowed after detection is made. Further, in the present embodiment, the storage capacity of the storage unit 14 is one field, and the sending unit 21 performs isochronous transfer.

FIG. 5 shows the timing of clock enable, and FIG. 6 shows the configurations of the OB detection unit 17 and the correction unit 16. In FIG. 5, the signal WEND is a write detection signal which is cleared by reset and becomes “1” after detecting the end of writing of the signal of one field.
The storage control unit 15 counts the write control pulse to the storage unit 14 generated by the storage control unit 15, detects that one field has been reached, and generates it.

The clock enable is permitted and the correction amount of the latch circuit 51 is updated until the signal WEND is obtained. At this time, the memory control unit 15 does not read the signal from the memory unit 14, and the adder / subtractor 48 does not operate. The signal value is not corrected. When the signal WEND is obtained, the clock enable is prohibited and the correction amount of the latch circuit 51 is not updated and is kept constant. At this time, the storage control unit 15 reads the signal from the storage unit 14 and gives it to the adder / subtractor 48,
The signal value is corrected. When the storage controller 15 finishes reading the signal for one field, the clock enable is permitted again, and a new correction amount is written in the latch circuit 51.

The signal WEND may be generated by detecting the vertical synchronizing signal VD generated by the driving section 19. In this case, it is not necessary to provide the storage control unit 15 with a counter for counting the write control pulse, and the configuration is simplified. However, since the first vertical synchronizing signal VD after reset release is not guaranteed that the circuit operation is correctly performed in one field, it must be ignored. This is because the detection of the signal WEND indicates that 1 field signal is not stored in the storage section 14,
This is to prevent the storage control unit 15 from erroneously recognizing that the fields have been stored.

FIG. 7 shows the relationship between the vertical synchronizing signal VD after reset release and the validity of the stored contents of the storage unit 14. This illustrates a case where a new signal is written in the storage unit 14 while reading the signal from the storage unit 14. Even if a signal is read in the field following the first vertical synchronization signal VD, an invalid signal is output because only a portion of the signal in the write period after reset release is stored in the storage unit 14. This inconvenience is avoided by generating the signal WEND by the second and subsequent vertical synchronization signals VD after the reset is released, and the correct signal can be read.

FIG. 8 shows the operation of the OB detector 17 when the time required for sending the video signal of 1 field from the sending unit 21 is about 1.5 times as long as the imaging of 1 field of the CCD 10, its control signal and The relationship of the output correction amounts is shown together. The correction amount held by the latch circuit 51 is kept constant throughout the entire period of reading the signal from the storage unit 14, and the correction amount for correcting the signal stored in the storage unit 14 is constantly calculated. Has been done. Therefore, it is possible to start the next reading at the end of the first one vertical scanning from the time when the reading is completed.

If the latch circuit is not controlled by the clock enable and the calculation of the correction amount itself is stopped and held, the read operation is performed when the writing of one field to the storage unit is completed as described above. It cannot be restarted. It becomes necessary to detect the start of a new vertical scan and the detection of the end of the vertical scan that follows,
This leads to an increase in the waiting time in reading.

The storage unit 14 of this embodiment has only a storage capacity corresponding to one field signal, and writing to the storage unit 14 is performed at the same period as the photoelectric conversion of the CCD, but it should be transmitted. Overwriting of a new signal over a signal whose field has not been read is prevented. For example, in FIG.
In the middle third field, writing and reading of the storage unit 14 are simultaneously executed for a part of the period. It is known that the sending unit 21 performs isochronous transfer to send a 1-field video signal.
This is possible because it has been confirmed that signal overwrite will not occur. When the sending unit 21 does not perform isochronous transfer, if the storage capacity of the storage unit 14 is set to a level that can store a signal of two fields, the loss of the signal due to overwriting can be prevented and the same processing can be performed. .

When the sending speed of the video signal is slower than the imaging speed by the CCD, the video signal is generated and sent to the outside for the field once the storage control unit 15 has started to read, but the storage unit 14 Some of the fields stored in the above are overwritten without being read. For example, if the time required to transmit the video signal of one field is 1.5 times the imaging time of one field, C
One-third of all fields output by the CD are overwritten without being read. The average value of optical black is calculated for these fields, but the difference value obtained from this is discarded without being used.

A third embodiment of the present invention will be described. In this embodiment, one line of the video signal is generated from a plurality of lines of the output signal of the CCD 10. In this case, the storage control unit 15 needs to read signals of a plurality of lines from the storage unit 14, but as the storage unit 14, a D-RAM is used.
Therefore, it is possible to easily read a plurality of desired lines substantially simultaneously by simply setting the read address appropriately. Therefore, it is not necessary to use the line memory as in the conventional case.

FIG. 9 shows a configuration relating to the management of the read address of the storage controller 15, and FIG. 10 shows a read timing chart. Here, it is assumed that one line of the video signal is generated from three consecutive lines. The storage control unit 15 has an address generator 101 for supplying a read address to the storage unit 14 and two adders 103 and 104.
And a selector 105, and three sets of two-stage flip-flops 106 and 107 for receiving the read signal.
It is equipped with 108, 109, 110, 111,
It has a line position generator 102 for controlling these operation timings.

The address generator 101 sequentially generates the address of the signal of 362 pixels in the first line of the three continuous lines. The adder 103 adds the number of pixels 362 for one line to the address generated by the address generator 101 to generate the address of one pixel on the second line. The adder 104 adds the number of pixels 724 for two lines to the address generated by the address generator 101 to generate the address of one pixel on the third line.

The address in the storage section 14 of the kth pixel of the jth line of the output signal of the light receiving area 31 of the CCD 10 is A
When expressed by j, k (j = 1, 2, ..., 492, k = 1, 2, ..., 362), when the address generator 101 generates addresses Aj ′, k ′, addition is performed. The devices 102 and 103 respectively have the address Aj '.
+ 1, k 'and address Aj' + 2, k 'will be generated.
3 of the address generator 101 and the adders 103 and 104
The two output addresses are input to the selector 105.

The address generator 101 is supplied with the data clock DCLK from the clock generator 22 of the controller 20 and generates one address in the four cycles. Similarly, the line position generator 102 is also supplied with the data clock DCLK, and outputs the output switching signal every 1 cycle of the selector 1.
Give to 05. The selector 105 sequentially selects the three input addresses in accordance with the signal and selects the storage unit 14
Output to The line position generator 102 outputs the switching signal to the selector three times, and then suspends the output of the switching signal for one cycle of the data clock DCLK. Therefore, the reading of the signal from the storage unit 14 is performed with four cycles of the data clock DCLK as one cycle.
The signal of one pixel on each of the three lines is sequentially read during the period of one read cycle.

The three read signals are taken in by the flip-flops 106, 107 and 108 at the preceding stage. The line position generators 102 are connected to each other by a data clock DCLK.
3 signals NLINE and NPLUS that are shifted by one cycle
1L and NPLUS2L are generated and given to the preceding flip-flop to control the signal fetch timing. The fetched signals are respectively output to the flip-flops 10 in the subsequent stages.
Output from 9, 110, and 111 to the correction unit 16. The acquisition of the signal of the previous stage into the latter stage of the signal is synchronized by the clock DCLK4 having four periods of the data clock DCLK provided from the clock generation unit 22 as one period.

The correction unit 16 is provided with three adders / subtractors corresponding to the three signals from the storage control unit 15 (not shown). Each adder / subtractor adds or subtracts the correction amount held by the OB detector 17 to the input signal and outputs the added signal to the video signal processor 18. Thus, the video signal processing unit 18 is simultaneously supplied with three signals of three lines. The address generator 101 sequentially generates addresses of 362 to read all the signals of three lines from the storage unit 14, and the video signal processing unit 18 generates one line of the video signal from these signals.

A fourth embodiment of the present invention will be described. In the third embodiment, the adder / subtractor is provided for each of the three signals of the three lines to perform the correction calculation separately. However, in the present embodiment, only one adder / subtractor reads out from the storage unit 14. The correction calculation of the three other signals is performed. FIG. 11 shows the configuration of the correction unit 16 of this embodiment. The above-mentioned three sets of two-stage flip-flops 106 to 11
1 is provided after the adder / subtractor 48 here.
The configuration and control signal of the storage control unit 15 for supplying the read address to the storage unit 14 are the same as those in the third embodiment.

The adder / subtractor 48 adds or subtracts the correction amount held by the OB detector 17 to the signals sequentially read from the memory 14. The output of the adder / subtractor 48 is given to the preceding flip-flops 106, 107, 108, and its fetching is done by the signals NLINE, NPLUS1L, NPL given from the line position generator 102 of the storage controller 15.
Controlled by US2L. The three signals in the front stage are synchronized with the clock DCLK4 and output to the video signal processing unit 18 via the flip-flops 109, 110, 111 in the rear stage.

In this embodiment, only one adder / subtractor for correction calculation is required, and the circuit configuration of the camera is reduced as compared with the third embodiment. However, the adder / subtractor is 3
It is necessary to perform a double operation, and if the reading from the storage unit 14 becomes faster, the operation of the adder / subtractor cannot follow the fetch clock.

In the fifth embodiment, the reading of the signal from the storage unit 14 and the correction calculation by the adder / subtractor are performed in parallel. FIG. 12 shows the configuration of the correction unit 16. A flip-flop 131 is provided in front of the adder / subtractor 48. The signal from the storage unit 14 is taken into the flip-flop 131 by the data clock DCLK and given to the adder / subtractor 48. While the adder / subtractor 48 is performing a correction operation on one signal, the next signal is output to the flip-flop 131.

The output signal of the adder / subtractor 48 is the storage controller 1
5 signal NLI provided by the line position generator 102
NE ', NPLUS1L', and NPLUS2L 'capture the flip-flops 106, 107, 108 in the preceding stage, transfer them to the flip-flops 109, 110, 111 in the subsequent stage by the clock DCLK4, and output them to the video signal processing unit 18.

FIG. 13 is a timing chart of this embodiment.
The operation will be described by taking the signal N in the figure as an example. The read operation of the signal N to the storage unit 14 is started from the rising of the data clock DCLK.
The output of signal N from is valid for data clock D
This is after a time of about half a cycle of CLK has elapsed. This signal N is taken into the flip-flop 131 at the next data clock DCLK, and the adder / subtractor 48 corrects the signal N. Therefore, the calculation of the adder / subtractor 48 is performed by the storage unit 1.
Data clock DCLK for read operation from 4
It will be delayed by one cycle. The output of the adder / subtractor 48 becomes valid as the signal N in the latter half of one cycle of the data clock DCLK. A signal NLINE ′ obtained by shifting the output signal of the adder / subtractor 48 by a half cycle with respect to the data clock DCLK.
Is taken into the flip-flop 106 at the preceding stage.

Signal N + of the other two lines following signal N +
Similarly, 1 and N + 2 are processed and taken into the flip-flops 107 and 108, respectively. Signals N, N + 1, N + 2 of the flip-flops 106, 107, 108 at the previous stage
Is a clock D having a cycle four times as long as the data clock DCLK.
It is synchronized with CLK4 and sent to the flip-flop in the subsequent stage. As a result, three signals of three lines are simultaneously given to the video signal processing unit 18.

In any of the above embodiments, the number of bits of the digital signal output from the AD conversion unit 13 and the storage unit 1
The case where the number of bits of one storage unit of 4 is the same has been described. However, when a memory having a small number of constituent bits is used as the storage unit 14, or in order to express a signal value with high accuracy, the AD conversion unit 13 outputs a digital signal having a larger number of bits than the constituent bit number of the storage unit 14. In some cases.

In the digital camera of the sixth embodiment, the number of bits in one storage unit of the storage unit 14 is smaller than the number of bits of the digital signal output from the AD conversion unit 13.
The configuration of the digital camera of this embodiment is the same as that shown in FIG. 1, and the different details will be described. The storage unit 14 needs to divide and store the output signal of the AD conversion unit 13. Here, one signal is divided into upper and lower parts, the upper part signal is stored in an odd address, and the lower part signal is stored in an even address, side by side.

The storage control unit 15 first reads the lower-order signal from the storage unit 14 and gives it to the correction unit 16, and then reads the higher-order signal and gives it to the correction unit 16. In addition, the storage controller 1
5 gives the read signal and the least significant bit of the address from which the signal is read to the correction unit 16.

The OB detecting section 17 extracts the signal of the optical black 33 from the signal given from the AD converting section 13, obtains its average value, and calculates the difference value from the predetermined value representing the black level to be set. The correction amount is used by the correction unit 16, but the same number of bits as the output signal of the AD conversion unit 13 is processed until the difference value is calculated. The OB detection unit 17 includes a difference value division unit (not shown), divides the calculated difference value into two and holds them separately, and outputs the upper and lower values thereof to the correction unit 16 as separate signals.

The configuration of the correction unit 16 is shown in FIG. 14 and FIG.
The timing chart of the signal processing of this embodiment is shown in FIG. The correction unit 16 includes a selection unit 120, an adder / subtractor 121, a carry storage unit 122, a carry control unit 123, and two registers 124 and 125. Selector 12
0, the adder / subtractor 121, and the registers 124 and 125 have the same number of bits as one storage unit of the storage unit 14. The selection unit 120 selects a higher-order signal and a lower-order signal of the correction amount given from the OB detection unit 17, and outputs the selected signal to the adder / subtractor 121. This selection is controlled by the value of the least significant bit given from the storage controller 15. The selection unit 120 outputs the lower signal when the value of the given least significant bit is “0”, and outputs the upper signal when the value is “1”.

The adder / subtractor 121 adds or subtracts the signal supplied from the storage controller 15 and the signal supplied from the selector 120 to correct the signal value. At this time, the lower-order signal and the higher-order signal are appropriately operated by the control by the value of the least significant bit. A carry may occur in the operation of the lower signal, and this carry is output to and stored in the carry storage unit 122. The adder / subtractor 121 also takes the carry input into the calculation.

The carry control unit 123 has a storage control unit 15
When the value of the least significant bit of the address given by is 1 is given to the adder / subtractor 121 as the carry input, the value stored in the carry storage unit 122, and the least significant bit is "1".
When it is “0”, the “0” is given as it is to the adder / subtractor 121. Therefore, the carry input of the adder / subtractor 121 is
It becomes "0" in the lower order operation, and becomes "1" or "0" in the higher order operation depending on whether or not the carry of the lower order operation preceding it occurs.

The adder / subtractor 121 stores the calculation result in the register 12
It outputs to 4, 125. These registers 124, 12
The output signal of the adder / subtractor 121 is taken in by the clock DCLK1 having a half cycle of the data clock DCLK.
The timing is controlled by / 2, but each has a clock enable, and is permitted or prohibited according to the value of the least significant bit given from the storage control unit 15 to the correction unit 16. In the register 124, the value of the least significant bit is "
When it is 1 ”, it is permitted and when it is“ 0 ”, it is prohibited, and the higher-order signal is taken in. Since the value of the least significant bit is given to the register 125 via the inverter 126, the value of the least significant bit is“ 0 ”. When it is permitted, when it is "1", it is prohibited, and the lower signal is fetched.

The output signals of the two registers 124 and 125 are combined into a single signal having a doubled bit number and supplied to the video signal processing section 18. Therefore, the video signal processing unit 18 can perform the video signal generation process with the same number of bits as the output signal of the AD conversion unit 13.

When the number of bits of the digital signal output from the AD converter 13 exceeds twice the number of bits of one memory unit of the memory 14, the signal is divided into three or more and stored. . In this case, it is impossible to control only the least significant bit of the address as described above, but if it is, for example, 4 or less, the control may be performed based on the lower 2 bits.

The seventh embodiment will be described. The digital camera according to the present exemplary embodiment is similar to the fifth exemplary embodiment in C
Although one line of the video signal is generated from the output signal of three lines of the CD 10, the AD converter 13 outputs the bit number of one memory unit as the memory 14 as in the sixth embodiment. A D-RAM smaller than the number of bits of a digital signal is used. However, unlike the sixth embodiment, the signal read from the storage unit 14 is restored to the same number of bits as the output of the AD conversion unit 13 before performing the correction calculation in the correction unit 16.

Here, an example is shown in which the output of the AD conversion unit 13 is 8 bits and one storage unit of the storage unit 14 is 4 bits. The storage unit 14 divides the output signal from the AD conversion unit 13 into upper and lower parts and stores them.
Then, the process is performed in the order of higher rank.

FIG. 16 shows the configuration of the correction unit 16, and FIG.
The timing chart is shown in FIG. The configuration of the correction unit 16 is almost the same as that of the fifth embodiment shown in FIG. 12, but another flip-flop 130 is provided in front of the flip-flop 131. These flip-flops 13
0 and 131 are 4 having the same number of bits as one storage unit of the storage unit 14.
It is a bit configuration. The adder / subtractor 48 and the three sets of two-stage flip-flops 106 to 111 have an 8-bit configuration with the same number of bits as the output of the AD conversion unit 13.

The 4-bit output signal from the storage unit 14 is applied to the front-stage flip-flop 130, and its output is supplied to the rear-stage flip-flop 131. In FIG. 17, Upp is a high-order signal and Low is a low-order signal.
The flip-flops 130 and 131 are fetched by the data clock DCLK, and the signal fetched by the flip-flop 130 at the preceding stage is fetched by the flip-flop 131 at the subsequent stage with a delay of one cycle. The outputs of the front-stage flip-flop 130 and the rear-stage flip-flop 131 are combined into one 8-bit signal and input to the adder / subtractor 48. This signal changes every cycle of the data clock DCLK, but the correct signal value is obtained once every two times.
The valid signal and the invalid signal appear alternately.

The adder / subtractor 48 uses this 8-bit signal and OB
Addition or subtraction with the 8-bit difference value calculated and held by the detection unit 17 is performed. The output signal of the adder / subtractor 48 is also 1 in 2
Becomes valid once. In FIG. 17, Val represents a valid signal and Inv represents an invalid signal. The output signal of the adder / subtractor 48 is given to the flip-flops 106, 107 and 108 at the previous stage. Adder / subtractor 4 for these flip-flops
The eight output signals are taken in by the three control signals NLINE ", NPLUS1L", and NPLUS2 shown in FIG.
It is controlled by L ″. These control signals are generated by the storage controller 15 from the clock DCLK2 having a cycle twice that of the data clock DCLK.

The preceding flip-flops 106, 107,
The signal of 108 is synchronized with the clock DCLK8 having a cycle eight times the data clock DCLK, is provided to the flip-flops 109, 110, and 111 at the subsequent stage, and is output to the video signal processing unit 18. Video signal processing unit 18
Generates one line of the video signal from the signal of three lines, and the generated video signal is sent from the sending unit 21 to the external device.

As is apparent from the above description, in the present invention, the black level of the output of each field of the CCD is set based on the optical black output of that field, so that an error occurs due to the time lag in the black level setting. Absent. Further, since the output signal of the CCD is temporarily stored and the stored signal is read to correct the black level setting, even when it is necessary to send the video signal to an external device at a low speed, the optical signal of the same field can be easily read. The black level can be set from the black output. Furthermore, since wasteful processing of generating a video signal that is not transmitted is not performed, the processing efficiency is high, and even when transmitting at a low speed, a storage capacity of a signal for one field is sufficient.

[0095]

According to the digital camera of the first aspect, the output signal of the light receiving area of the photoelectric conversion element has its reference level set based on the level of the output signal outside the light receiving area of the same field as this. Even if there is a change in environmental conditions such as temperature, the level is always set properly without being affected by it. Therefore, the video signal generated from the output signal of the light receiving area is always generated based on the true amount of received light, and the video correctly reflects the brightness and color of the subject.

In the digital camera of the second aspect, when the receiving speed of the external device receiving the video signal does not follow the output speed of the photoelectric conversion element, the sending speed from the camera can be matched with the receiving speed of the external device. Therefore, the camera can be used as a video input device of a low speed external device.

In the digital camera of the third aspect, since the output signal of the photoelectric conversion element is stored in the storage means, by reading this, the reference level of one field is set based on the output signal of that field. It is possible to do so reliably and easily. Further, the level setting process can be performed at any time after the storage. If, while storing the output signal of the photoelectric conversion element in the storage means, processing such as obtaining the average value of the output signal outside the light receiving area is performed in parallel with this, at the same time as the completion of the processing or the completion of the storage. The level setting process can be started, and the pre-processing time until the start of video signal generation can be suppressed to the minimum necessary. Moreover, it is possible to generate a video signal of only the field to be used, and it is not necessary to perform unnecessary processing.

In the digital camera of the fourth aspect, since the signal converted into the digital signal is stored in the storage means, storage control such as management of storage address is easy. Moreover,
When one line of the video signal is generated from the signals of a plurality of lines, when the same signal is read from the storage means a plurality of times and used, it is not necessary to convert it into a digital value many times and the processing speed is reduced. do not do.

According to the fifth aspect of the digital camera, setting the level of the output signal of the CCD of one field based on the output value of the field can be easily realized with a simple structure.

According to the digital camera of claim 6,
The output signal of the photoelectric conversion element of one field is processed separately for the light receiving area and the outside of the light receiving area, and at the same time as or before the storage of the output signal of the light receiving area is completed, the output signal of the predetermined area outside the light receiving area is received. The correction amount for setting the reference of the signal value of the area is calculated and stored, and the reference of the output signal value of the photoelectric conversion element of one field can be set by the value of the output signal of the field itself. Is. Therefore, even if there is a change in environmental conditions such as a temperature change, the value of the output signal of the photoelectric conversion element is not affected by the change, and the true amount of light received is accurately represented. And it is possible to provide an image that correctly expresses colors.

In the digital camera of the present invention, when the video signal transmission speed is set to be slower than the output of the photoelectric conversion element, the reference of the signal value of the output of the photoelectric conversion element is used as the reference of the output signal of the field for the transmission field. It is possible to reliably set it by the value of, and it is possible to generate a video signal from a signal representing the true amount of received light. Since no video signal is generated for the fields that are not transmitted, wasteful processing is eliminated and processing efficiency is improved. This camera is suitable for providing a video signal to an external device having a low processing speed.

According to the digital camera of the eighth aspect, the above effects can be obtained with a simple structure.

In the digital camera according to claim 9, when one line of the video signal is generated from a plurality of lines of the output of the photoelectric conversion element, the correction when setting the reference of the signal value of one field by the signal value of that field The processing can be performed by only one adder / subtractor. Therefore, it is not necessary to provide an adder / subtractor for each line, which simplifies the camera configuration.

In the digital camera of the tenth aspect, when one line of the video signal is generated from a plurality of lines of the output of the photoelectric conversion element, it is not necessary to provide an adder / subtractor for correcting the signal value for each line. The structure of the camera is simple, and the correction process can be performed quickly.

According to the eleventh aspect of the digital camera, a quick correction process can be realized without impairing the feature that the configuration is simple.

According to the digital camera of the twelfth aspect, it is possible to set the reference of the signal value of one field by the signal value of the field by using the memory device having a small number of bits constituting the memory unit. . Conversely, since the signal value is represented by a larger number of bits than the number of bits constituting the memory device, the accuracy of the signal value can be increased and a large signal value can be processed. .

According to the thirteenth aspect of the digital camera, the above effect can be realized by exchanging a minimum amount of information of 1 bit, the camera configuration is simple, and the processing efficiency is good.

In the digital camera of the fourteenth aspect, the storage device having a small number of constituent bits can be used to set the reference of the signal value of one field by the signal value of the field. Moreover, it is not necessary to perform a special operation such as a carry process in the addition and subtraction, and the correction process can be performed by an ordinary adder / subtractor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital camera of the present invention.

FIG. 2 is a diagram showing a light receiving area of a CCD and optical black.

FIG. 3 is a diagram showing control signals for processing an optical black output.

FIG. 4 is a diagram showing a configuration of an OB detection unit and a correction unit according to the first embodiment.

FIG. 5 is a diagram showing a timing of updating a correction amount in the second embodiment.

FIG. 6 is a diagram showing a configuration of an OB detection unit and a correction unit according to a second embodiment.

FIG. 7 is a diagram showing a relationship between a vertical synchronization signal and validity of stored contents of a storage unit according to the second embodiment.

FIG. 8 is a diagram showing a timing of signal processing according to the second embodiment.

FIG. 9 is a diagram showing a configuration of a storage control unit according to a third embodiment.

FIG. 10 is a diagram showing the timing of signal processing in the third embodiment.

FIG. 11 is a view showing the arrangement of a correction unit according to the fourth embodiment.

FIG. 12 is a view showing the arrangement of a correction unit according to the fifth embodiment.

FIG. 13 is a diagram showing a timing of signal processing in the fifth embodiment.

FIG. 14 is a view showing the arrangement of a correction unit according to the sixth embodiment.

FIG. 15 is a diagram showing the timing of signal processing in the sixth embodiment.

FIG. 16 is a view showing the arrangement of a correction unit according to the seventh embodiment.

FIG. 17 is a diagram showing the timing of signal processing in the seventh embodiment.

FIG. 18 is a diagram showing a configuration of a conventional digital camera.

FIG. 19 is a diagram showing a configuration when one line of a video signal is generated from a plurality of lines in a conventional digital camera.

[Explanation of symbols]

10 CCD (photoelectric conversion element) 11 imaging unit 12 preprocessing unit 13 AD conversion unit (AD conversion unit) 14 storage unit (storage unit) (signal storage unit) 15 storage control unit (storage control unit) 16 correction unit (level adjustment) Means) (signal value adjusting means) 17 optical black detecting section (level difference detecting means) (average value calculating means, difference value holding means, difference value dividing means) 18 video signal processing section (video signal processing means) (video signal generation) 19) Driving section 20 Control section 21 Sending section 21 (Video signal sending means) 22 Clock generating section 31 Light receiving area 33 Optical black 41, 43 Adder 42, 44 Register 45 Average value calculating circuit 46 Subtractor 47 Latch circuit 48 Adder / subtractor 51 Latch Circuit (Flip-Flop) 101 Address Generator 102 Line Position Generator 103, 104 Adder 105 Selector 106-111 Flip-flop 120 Selector (difference value dividing means) 121 Adder / subtractor 122 Carry memory (carry memory) 123 Carry controller 124, 125 Register 126 Inverter 130, 131 Flip-flop (signal reproducing means)

Claims (14)

[Claims] 1. A photoelectric conversion element for outputting a signal according to the amount of received light, wherein a video signal is generated from an output signal of a light receiving area of the photoelectric conversion element, and a reference level of the output signal of the light receiving area is set to the reference level. In a digital camera set based on an output signal outside the light receiving area, a reference level of one field of the output signal of the light receiving area is set based on an output signal outside the light receiving area of the same field. . 2. The digital camera according to claim 1, wherein the video signal is sent to the outside at a speed lower than the speed at which the photoelectric conversion element outputs the signal. 3. An output signal of the photoelectric conversion element is temporarily stored in a storage means, and the output signal of the photoelectric conversion element stored in the storage means is read out to generate a video signal by a video signal processing means. The digital camera according to claim 1, wherein the digital camera is a digital camera. 4. An AD that converts an analog output signal of the photoelectric conversion element into a digital signal and writes the digital signal in the storage means.
The digital camera according to claim 3, further comprising: a conversion unit; and a storage control unit that controls writing of the AD conversion unit into the storage unit and reads out a digital signal stored in the storage unit. . 5. A predetermined value outside the light receiving area is provided by storing a predetermined value corresponding to a reference level of a video signal and receiving an output signal outside the light receiving area of the photoelectric conversion element converted into a digital signal by the AD conversion means. A level difference detecting means for calculating an average value of the signals in the area and obtaining and storing a difference value between the average value and the predetermined value; a digital signal read by the storage control means and the level difference detecting means The level difference adjusting means for adding or subtracting the difference value to or from the given digital signal and outputting the signal after the calculation to the video signal processing means. The digital camera according to claim 4, wherein the digital camera is a digital camera. 6. A photoelectric conversion element that outputs an analog signal according to the amount of received light, an AD conversion unit that converts the output signal of the photoelectric conversion element into a digital signal and outputs the digital signal, and an output signal of the AD conversion unit. A signal storage unit that stores a signal of a light receiving region of the photoelectric conversion element, and a storage unit that controls writing of an output signal of the AD conversion unit into the signal storage unit and reads out a signal stored in the signal storage unit. A control means, an average value calculation means for calculating and outputting an average value of signals in a predetermined area outside the light receiving area of the photoelectric conversion element among the output signals of the AD conversion means, and storing a predetermined value, A difference value holding unit for calculating and holding a difference value between the average value output from the average value calculation unit and the predetermined value; and a signal read from the signal storage unit by the storage control unit. A signal value adjusting means for changing and outputting the value of the signal by a difference value held by the difference value holding means; a video signal generating means for generating a video signal from an output signal of the signal value adjusting means; A digital camera, comprising: a video signal transmitting means for transmitting the video signal generated by the signal generating means to the outside. 7. The difference value holding means does not update the held difference value until the storage control means completes reading a signal of one field from the signal storage means. The camera described in. 8. The photoelectric conversion element is provided with a flip-flop for inputting the calculated difference value to the difference value holding means.
When the output of the field signal is completed, the difference value is written to the flip-flop, and the write control clock of the flip-flop is prohibited until the storage control means completes reading the signal of one field from the signal storage means. The digital camera according to claim 7, wherein: 9. The digital camera according to claim 6, wherein the video signal generation means generates a video signal of one line from a signal of a plurality of lines, wherein the signal value adjusting means is from the storage control means. The storage controller has one adder / subtractor that adds or subtracts a given signal and the difference value, and the storage control unit reads signals of a plurality of lines from the signal storage unit and supplies the signals to the signal value adjusting unit. A digital camera characterized in that the adjusting means sequentially performs the arithmetic operation by the adder / subtractor on the signal given from the storage control means. 10. The digital camera according to claim 6, wherein the video signal generating means is 1 from signals of a plurality of lines.
In the case of generating a video signal of a line, the signal value adjusting means has one adder / subtractor that adds or subtracts the signal given from the storage control means and the difference value, and the storage control means has the signal The signals of a plurality of lines are sequentially read from the storage means and given to the signal value adjusting means, and the signal value adjusting means controls the storage control while the storage control means is reading the next signal from the signal storage means. A digital camera, wherein the adder / subtractor performs an operation on one signal given by the means. 11. The storage control means has a flip-flop for taking in the signal read from the signal storage means, and when the signal value adjusting means completes the operation for one signal, the next signal is sent to the flip-flop. 11. The digital camera according to claim 10, wherein the digital camera is captured and provided to the signal value adjusting means. 12. The digital camera according to claim 6, wherein the AD conversion means outputs a signal having a number of bits larger than the number of bits forming one storage unit of the signal storage means. A difference value dividing means for dividing the difference value of the difference value holding means into a signal having the same number of bits as the one storage unit and selecting and outputting the divided signal to the value adjusting means; Signal and the output signal of the difference value dividing means, the adder / subtractor having the same number of bits as one storage unit for adding or subtracting, and the carry generated by the arithmetic operation of the adder / subtractor is stored in the carry. A carry storage means provided to the signal storage means, and the storage control means supplies the signal read out from the signal storage means and the read address to the signal value adjusting means, Zui by digital camera and controlling the provision of the carry into the adder-subtractor from the selection and the carry storage means of the signal of the difference value dividing means. 13. The AD conversion means outputs a signal having a bit number twice as many as the number of bits constituting one storage unit of the signal storage means, and the signal storage means outputs one output signal of the AD conversion means. The data is divided into two and stored in adjacent addresses, the storage control means gives the value of the least significant bit of the read address to the signal value adjusting means, and the difference value dividing means outputs the divided signal to the bits. 13. The digital camera according to claim 12, wherein the carry storage means performs the carry supply to the adder / subtractor and the stop thereof according to the value of the bit. 14. The digital camera according to claim 6, wherein the AD conversion means outputs a signal having a number of bits larger than the number of bits forming one storage unit of the signal storage means. Signal reproducing means for reproducing and outputting to the value adjusting means a signal having the same number of bits as the output of the AD converting means from the plurality of signals of the one storage unit given from the storage controlling means, and the output of the signal reproducing means. A digital camera comprising an adder / subtractor having the same number of bits as the output of the AD conversion means for performing addition or subtraction of a signal and the difference value of the difference value holding means.