JPH09331029A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A memory cell of a diode type ROM is miniaturized. Bit lines BL1 to BL3 are formed by an N type diffusion layer formed on a P type silicon substrate, and word lines WL1 to WL3 are formed on the silicon substrate in a direction orthogonal to the bit lines BL1 to BL3. There is. The word lines WL1 to WL3 have a lower layer of a P-type polysilicon layer and an upper layer of a tungsten silicide layer, and the intersections of the bit lines and the word lines are the memory cells C11 to C33, respectively. Memory cells C11 to C
In 33, memory cells C11 and C22 are written with data so that the bit line and the word line are not electrically connected to each other, and two kinds of diodes in opposite directions are formed, so that other memory cells are electrically connected. One type of diode is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor memory device (ROM), and more particularly to a diode type mask RO.
The present invention relates to M and its manufacturing method. This semiconductor memory device may be used as such or with other semiconductor devices.
Formed into chips.

[0002]

2. Description of the Related Art In a memory device such as a mask ROM, the size of each memory element greatly affects the cost of the device. Therefore, high integration is being promoted by making full use of miniaturization technology. A diode ROM is known as one type of mask ROM. Diode type ROM is MO
Compared with the S-transistor type ROM, the structure is simple, and since the source / drain regions required for the MOS transistor are not provided, the memory cell can be made much smaller. Also, the operating speed is faster than that of the MOS transistor.

As an example of a diode-type ROM, there has been proposed a method of selecting whether to form a diode or not depending on the presence or absence of a contact according to the data to be written (see Japanese Patent Laid-Open No. 60-176266).
In the ROM of the reference, a plurality of lines are formed of one conductivity type semiconductor on an insulator, an insulating film is provided on the surface thereof, a semiconductor wire of an opposite conductivity type intersecting the line is provided, and the line and the wiring are Contacts are formed at the intersections of the data corresponding to the data "1" and "0".

[0004]

In the reference ROM, data is written depending on the presence / absence of a contact at the intersection of a word line and a bit line. Therefore, the size of the memory cell is different from the contact and the margin of misalignment. There is a drawback that it becomes large because it requires a space for. Therefore, the present invention is a diode type RO
The purpose is to further reduce the size of the M memory cell.

[0005]

According to the present invention, a memory cell in which data is written not by the presence or absence of a contact but by forming a diode in advance at each intersection of a bit line and a word line so as not to conduct between both lines. Data writing is performed by forming a junction in the opposite direction by ion implantation.

Therefore, the diode type ROM of the present invention
Is a band-shaped bit line made of a semiconductor layer and formed in parallel with each other, and a plurality of band-shaped word lines formed in a two-layer structure in which the lower layer is in direct contact with the bit line and intersects with the bit line. In addition, one kind of junction or two kinds of junctions in opposite directions are formed at the intersections of the bit lines and the word lines according to the data to be stored.

The bit line is preferably a diffusion layer formed on a semiconductor substrate or a polysilicon layer formed on an insulating film. The word line preferably has a polycide structure in which the lower layer is a polysilicon layer and the upper layer is a refractory metal silicide layer.

In order to manufacture the ROM of the present invention, the manufacturing method of the present invention includes the following steps (A) to (C). (A) Band-shaped bit lines parallel to each other by forming a diffusion layer of the first conductivity type on a semiconductor substrate or by forming a polysilicon layer of the first conductivity type on an insulating film and patterning it (B) forming a polycide layer having a structure of a second conductivity type polysilicon layer as a lower layer and a refractory metal silicide layer as an upper layer from above the bit line, and patterning the polycide layer in a direction intersecting the bit line. Step of forming a plurality of strip-shaped word lines, (C) forming a resist pattern having openings at the intersections between the bit lines and the word lines that do not conduct according to the data to be stored And using the mask as a mask, ion-implanting the first conductivity type impurity into the polysilicon layer of the word line.

In the diode type ROM of the present invention, a current flows in the forward direction of the diode in the memory cell in which one kind of junction is formed at the intersection of the bit line and the word line, and two kinds of junctions in the opposite direction are formed. No current flows in either direction in the formed memory cell. In this way, the data written in the memory cell can be read depending on whether the current flows or does not flow.

[0010]

FIG. 1 shows an embodiment. (A) is a schematic plan view and (B) is an equivalent circuit diagram thereof. Bit lines BL1 to BL are formed by an N type diffusion layer formed on a P type silicon substrate.
3 is formed, and the bit line B is formed on the silicon substrate.
Word lines WL1 to W in a direction orthogonal to L1 to BL3
L3 is formed. The word lines WL1 to WL3 have a lower layer of a P-type polysilicon layer and an upper layer of a tungsten silicide layer, and the intersections of the bit lines and the word lines are the memory cells C11 to C33, respectively.

Of the memory cells C11 to C33, data is written to the memory cells C11 and C22 so that the bit line and the word line are not electrically connected, and the junction is formed so as to be electrically connected to the other cells. And
As shown in the equivalent circuit diagram, memory cells C11 and C2
In 2, two types of diodes in opposite directions are formed.

FIG. 2 shows a manufacturing method of the embodiment of FIG. 1 in which the bit line is an N type diffusion layer formed on a P type silicon substrate. (A) to (C) are plan views showing the process, and (a) to (c) are sectional views taken along line XX 'in each plan view. .

(A) A channel stopper layer 6 for element isolation and a field oxide film 4 thereon are formed on a P-type silicon substrate 2 by a normal process. At this time, the bit line in the memory area becomes an elongated continuous silicon substrate layer without a field oxide film. Then, an N-type impurity such as arsenic is injected into the memory region with an energy of 20 to 100 KeV and an injection amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² to form an N-type diffusion layer 8 serving as a bit line. .

(B) A polysilicon film 100 is formed on the substrate 2.
A P-type polysilicon film 10 is formed by depositing the P-type polysilicon film 10 to a thickness of 0 to 3000 Å and introducing P-type impurities such as boron by an ion implantation method or a diffusion method. A tungsten film 12 having a thickness of 1000 to 3000 Å is formed on the polysilicon film 10, and the tungsten film 12 and the polysilicon film 10 are patterned by photoengraving and etching. The word line 13 is formed. This allows word lines 13 and bit lines 8
A PN junction is formed at the intersection of and a diode is formed,
A memory array is formed.

The tungsten film 12 and the polysilicon film 10 are subjected to the respective heat treatments or the heat treatments thereafter.
Serves as a polycide layer, and the P-type impurity in the polysilicon layer 10 diffuses toward the N-type diffusion layer of the bit line 8 to form a P ⁻ layer 14 at the intersection of the word line 13 and the bit line 8.

(C) In each memory cell of the memory array, a resist pattern 16 having an opening 18 is formed in a diode portion which is turned off for writing data, and N-type impurities such as phosphorus are used as a mask with the resist pattern 16 as a mask.
Implantation is performed with an energy of V at an implantation dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ / cm ² . The implantation condition at this time is a sufficient implantation amount to invert the P-type polysilicon layer 10 of the word line into the N-type layer 20, and the P-type in the lower silicon substrate.
^- an energy that does not affect the layer 14. After removing the resist 16, an insulating film is formed under known conditions,
A contact hole is opened and a metal wiring is formed.

Returning to FIG. 1, the operation of this embodiment will be described. A plurality of bit lines formed of the N type diffusion layer and a plurality of word lines including P type polysilicon are orthogonal to each other and are formed continuously to form an array-shaped diode. Since the memory cell in which this diode is formed has a PN junction, when a positive voltage is applied to the word line, a forward current flows from the word line to the bit line. Therefore, by applying a positive voltage to the selected word line and reading the current from the selected bit line, the memory cell at the intersection of the word line and the bit line is determined to be ON. By opening both the unselected word line and bit line, no current flows in the unnecessary direction.

Next, in the memory cell in which the data is written, the word line layer becomes the N-type polysilicon layer and becomes the NPN junction. Therefore, even if a positive voltage is applied to the word line, the current flows in the opposite direction and no current flows, and it is determined to be OFF.

Since an N-type region and a P-type region coexist in the polysilicon layer 10, a current does not flow in the polysilicon layer 10, but since the tungsten silicide layer 12 is present thereon, a current flow as a word line. Is secured.

In the embodiment, since the bit line 8 is the N type diffusion layer and the word line is the P type polysilicon layer 10, the N type diffusion layer as the diffusion layer has a lower resistance than the P type diffusion layer. , It is convenient for increasing the operation speed. Further, since phosphorus can be implanted as an N-type impurity in order to write data so that a current does not flow between the word line and the bit line, it is easier than implantation of a P-type impurity. However, the conductivity types P and N in the embodiment may be reversed.

Instead of the tungsten silicide layer 12 for ensuring the current flow in the word line, another refractory metal silicide layer may be used. The bit line is not limited to the diffusion layer and can be formed by a polysilicon film formed on an insulating film as shown in the reference.

[0022]

According to the diode type memory device of the present invention, data is written depending on whether one type of diode is formed in the memory cell at the intersection of the word line and the bit line or two types of diodes in the opposite direction are formed. Because I did
Since it is not necessary to provide a contact for each memory cell, a small memory cell can be realized. The diode type memory device is basically smaller in size per memory cell than the MOS transistor type and has a higher operation speed. As described above, according to the present invention, the high-speed and highly integrated mask R is used.
OM can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment, (A) is a schematic plan view, and (B) is an equivalent circuit diagram thereof.

FIG. 2 is a diagram showing a manufacturing method of the embodiment of FIG.
(A) to (C) are plan views showing the process, and (a) to (c) are sectional views taken along line XX 'in each plan view.

[Explanation of symbols]

 2 Silicon substrate 8 bit line 10 word line polysilicon layer 12 word line tungsten silicide layer 13 word line

Claims (5)

[Claims] 1. A strip-shaped bit line made of a semiconductor layer and formed in parallel with each other, and a plurality of strip-shaped bit lines formed in a direction of intersecting the bit line with a lower layer in direct contact with the bit line in a two-layer structure. A read-only semiconductor memory comprising a word line, and one junction or two junctions in opposite directions are formed at an intersection of the bit line and the word line according to data to be stored. apparatus. 2. The read-only semiconductor memory device of claim 1, wherein the bit line is a diffusion layer formed on a semiconductor substrate. 3. The read-only semiconductor memory device according to claim 1, wherein the bit line is a polysilicon layer formed on an insulating film. 4. The word line has a polysilicon layer as a lower layer,
4. The read-only semiconductor memory device according to claim 1, wherein the upper layer is a polycide structure of a refractory metal silicide layer. 5. A method of manufacturing a semiconductor memory device including the following steps (A) to (C). (A) Band-shaped bit lines parallel to each other by forming a diffusion layer of the first conductivity type on a semiconductor substrate or by forming a polysilicon layer of the first conductivity type on an insulating film and patterning it (B) forming a polycide layer having a structure of a second conductivity type polysilicon layer as a lower layer and a refractory metal silicide layer as an upper layer from above the bit line, and patterning the polycide layer in a direction intersecting the bit line; A step of forming a plurality of strip-shaped word lines, (C) forming a resist pattern having openings at the intersections between the bit lines and the word lines that do not conduct according to the data to be stored And using the mask as a mask, ion-implanting the first conductivity type impurity into the polysilicon layer of the word line.