JPH09331455A - Image decoding method and apparatus - Google Patents

Abstract

(57) Abstract: Data encoded by utilizing the correlation between bits cannot be processed in parallel at high speed by a plurality of decoders. SOLUTION: In a first phase, a prediction state is generated, a prediction state RAM is read, and a decoded value is determined. next,
In the second phase, post-decoding renormalization of registers, code input, and prediction state update are performed. Then, after the MSB decoded value of the first phase is determined,
The phases are shifted so as to create the predicted reference state of the first phase of B. Similarly, after the LSB decoded value of the first phase is determined, the phases are shifted so as to create the predicted reference state of the first phase of the MSB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding method and apparatus for decoding encoded data of an n-bit image.

[0002]

2. Description of the Related Art Conventionally, when an encoded image of n bit planes (where n is an integer of 2 or more) is decoded,
It is common to use a 1-bit decoder and take n times as long as decoding, or treat each bit plane as separate coded data, and perform n decodings with n decoders. there were.

[0003]

However, the former method has a problem that it cannot be used for equipment requiring high-speed processing because the processing time takes n times, and the latter method has a problem that the correlation between bits at the time of encoding. However, there is a problem that the compression rate does not increase because it cannot be used. The present invention has been made to solve the above problems, and provides an image decoding method and apparatus in which coded data using the correlation between bits is operated in parallel at high speed by a plurality of decoders. That is.

[0004]

In order to achieve the above object, the present invention is an image decoding method for decoding coded data of an n-bit image, wherein n kinds of decoders are used. The decoding step of decoding the coded data of 1) and the prediction reference state generating step of reflecting the respective decoding results on other bit planes.

The present invention is also an image decoding apparatus for decoding encoded data of an n-bit image, and a decoding means for decoding n kinds of encoded data by n decoders, Prediction reference state generation means for reflecting each decoding result in another bit plane.

In such a configuration, n decoders decode n types of coded data, and the decoding results of each are reflected in other bit planes.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The arithmetic code used in the embodiment is QM used in JBIG and JPEG which are ISO international standards.
-It is assumed that the Coder method or the like is used.

FIG. 1 is a block diagram showing a configuration of a decoder in the embodiment. In this example, an n-bit plane image (when n = 2) is decoded.
In the figure, 10 is an image memory for storing image data of a decoding result, 11 and 21 are prediction state generators, 12 and 22 are prediction state RAMs, 13 and 23 are LSZ-ROMs, 14 and
24 is an arithmetic decoder, 15 and 25 are UPDATE-RO
M, 16 and 26 are output circuits, 19 is an MSB decoder, 29
Is the LSB decoder.

The operations of the two decoders 19 and 29 are basically the same, and will be described here in common.

In the above structure, the image memory 10-a stores encoded 2-bit image data.
This data is input to the prediction state generator 11 (21),
The prediction state for the decoded symbols is determined. This prediction state is input to the prediction state RAM 12 (22) as an address, and the prediction symbol [0:
Superior symbol (MPS) / 1: Inferior symbol (LP
S)] and an index indicating its appearance probability are output.

Next, in the LSZ-ROM 13 (23),
L is the parameter that the index uses in the arithmetic decoding operation
Converted to SZ value. Then, the arithmetic decoder 14 (24)
Then, the decoding process based on the arithmetic operation is performed, and the decoded symbol (MSB or LSB) is output to the image memory 10-b through the output circuit 16 (26).

Codewords 100 and 200 are the MSB code and the LSB code, respectively.
24.

Further, from the arithmetic decoder 14 (24), a modification request signal concerning prediction in each prediction state is UPDATE.
-The corrected data output to the ROM 15 (25) is stored in the prediction state RAM 12 (22).

Further, the output 101 of the arithmetic decoder 14 in the MSB decoder 19 is input to the prediction state generator 21 of the LSB decoder 29 and used for determining the LSB prediction state.

Similarly, the output of the arithmetic decoder 24 is input to the prediction state generator 11 and used for determining the prediction state of the MSB.

FIG. 2 is a block diagram showing the configuration of the encoder in the embodiment. In the figure, 30 is an image memory, 31 is a prediction state generator, 32 is a prediction state RAM, 3
3 is LSZ-ROM, 34 is arithmetic encoder, 35 is UPD
ATE-ROM, 36 is an output circuit, and 37 is a gate.

In the above structure, the image memory 30 stores 2-bit image data to be encoded. This data is input to the prediction state generator 31, and the prediction state for the encoded symbol is determined.

Next, the prediction state RAM 32 outputs a prediction symbol [0/1] in each prediction state and an index indicating its appearance probability. LSZ-ROM
In 33, the index is converted into an LSZ value which is a calculation parameter used in the arithmetic encoder 34.

Then, the arithmetic encoder 34 performs an encoding process by an arithmetic code using these values and the encoded symbol value, and the code is output from the output circuit 36.

Usually, as a method of generating two types of codes, that is, an MSB code and an LSB code, there are a method using two encoders and a method using one encoder in time division. In the embodiment, the latter method is used. Generate two types of codes. That is, in the first pass, the gate 37 is controlled to encode only the MSB, and in the second pass, only the LSB is encoded.
Two types of codes are generated.

FIG. 3 is a block diagram showing the structure of the prediction reference state generation circuit. As shown in the figure, it is composed of a plurality of latch circuits, a one-line memory and a lead line,
The value of the symbol around the decoded symbol can be referred to.

The generation of the predicted reference state in the embodiment will be described in detail below.

FIG. 4 is a diagram for explaining the arrangement of pixels. In the figure, M is the upper bit and L is the lower bit.
Is represented. In addition, the image (m ×
n) is treated as a 2m × n image. Note that this merit is that even if an encoder for 1 bit is used, a code that utilizes the correlation between bit planes can be easily realized.

FIG. 5 is a diagram showing template 1 at the time of MSB encoding / decoding. When encoding (decoding) M, which is a symbol to be encoded (decoded), a prediction state is generated using bits of ML of two pixels on the left and ML of four pixels immediately above one line. Therefore, at the time of MSB decoding, 500, 501, 502, 503 of the left pixel and 505, 506, 507, 508, 509, 510 of the pixels on one line are
A prediction state is generated using a total of 12 bits of 11,512 data.

FIG. 6 is a diagram showing the template 2 at the time of LSB encoding / decoding. When encoding (decoding) L, which is an encoding (decoding) target symbol, a prediction state is generated using the ML of the left two pixels, the ML bits of the four pixels immediately above one line, and the MSB of the same pixel. . Therefore, LS
At the time of B decoding, 500, 501, 502, 50 of the left pixel
3, 504 and pixels 506, 507, 50 on one line
13, total of 8,509,510,511,512,513
Generate prediction state using bit data.

On the encoder side, it is possible to improve the prediction accuracy of encoded symbols by using this MSB and separating the MSB prediction state and the LSB prediction state.

FIG. 7 is a diagram showing a processing flow of the MSB decoder and the LSB decoder. As shown, in the embodiment, the processing of the decoder is divided into the following two phases.

First, in the first phase, the prediction state is generated, the prediction state RAM is read, and the decoded value is determined. Next, in the second phase, renormalization of the register, code input, and update of the prediction state, which are post-decoding processing, are performed.

Then, after the MSB decoded value of the first phase is determined, the phases are shifted so as to create the predicted reference state of the first phase of LSB. Similarly, in the first phase L
After the SB decoded value is determined, the phases are shifted so as to create the predicted reference state of the first phase of the MSB.

FIG. 8 is a schematic flowchart showing a decoding process of one symbol in the embodiment. First, in step S101, a predicted reference state is generated, and then in step S10.
At 2, the index data and the prediction symbol are read from the prediction state RAM. Then, in step S103, LSZ
-The LSZ value is read from the ROM, and in step S104, the C register peculiar to the QM-Coder is compared with the A register to determine the decoded symbol. Next, step S10
In step 5, renormalization processing of the C and A registers peculiar to the QM-Coder is performed, and in the subsequent step S106, the updated index data and the predicted symbol are stored in the prediction state RAM.

In this way, each symbol is decoded by repeating the above processing. The first phase shown in FIG. 7 includes steps S101 to S104.
The second phase corresponds to steps S105 to S106, respectively.

As described above, according to the embodiment,
With 1 or n encoders, means for generating n kinds of codes, and n decoding means with predictive reference state generating means reflecting the respective decoding results, and shifting the phase of n decoders By performing operation such that one decoding result is output to another decoding process, n encoders can be operated in parallel even in encoding using correlation between bit planes, and high speed operation can be achieved. It becomes possible to perform a decryption process.

In the above-mentioned embodiment, the 2-bit plane has been described as an example, but the present invention is not limited to this. For example, in the case of 3 bits and 4 bits, it can be realized by delaying the phase by one phase.

It is needless to say that the present invention can be applied if even a 1-bit image is allowed to be divided into two, that is, a code of an odd pixel and a code of an even pixel.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

[0037]

As described above, according to the present invention,
It becomes possible to operate the data encoded by utilizing the correlation between bits at a high speed in parallel by a plurality of decoders.

[0038]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a decoder according to an embodiment.

FIG. 2 is a block diagram showing a configuration of an encoder in the embodiment.

FIG. 3 is a block diagram showing a configuration of a prediction reference state generation circuit.

FIG. 4 is a diagram for explaining an arrangement of pixels.

FIG. 5 is a diagram showing a template 1 at the time of MSB encoding / decoding.

FIG. 6 is a diagram showing a template 2 at the time of LSB encoding / decoding.

FIG. 7 is a diagram showing a processing flow of an MSB decoder and an LSB decoder.

FIG. 8 is a schematic flowchart showing a decoding process of one symbol in the embodiment.

[Explanation of symbols]

 10 Image Memory 11 Prediction State Generator 12 Prediction State RAM 13 LSZ-ROM 14 Arithmetic Decoder 15 UPDATE-ROM 16 Output Circuit 19 MSB Decoder 21 Prediction State Generator 22 Prediction State RAM 23 LSZ-ROM 24 Arithmetic Decoder 25 UPDATE -ROM 26 output circuit 29 LSB decoder

Claims (6)

[Claims] 1. An image decoding method for decoding encoded data of an n-bit image, comprising a decoding step of decoding n kinds of coded data by n decoders, and a decoding result of each. And a predictive reference state generating step of reflecting the above in other bit planes. 2. The image decoding according to claim 1, wherein the decoding step shifts the phases of the n decoders and outputs a decoding result of one decoder to another decoder. Method. 3. The prediction reference state generation step generates a prediction state by referring to a value of a symbol surrounding a symbol to be decoded by using a plurality of latch circuits, a one-line memory and a lead line. 1. The image decoding method described in 1. 4. An image decoding apparatus for decoding encoded data of an n-bit image, comprising decoding means for decoding n kinds of encoded data by n decoders, and decoding results of each. And a prediction reference state generation means for reflecting the above in another bit plane. 5. The image decoding according to claim 4, wherein the decoding means shifts the phase of each of the n decoders and outputs a decoding result of one decoder to another decoder. Device. 6. The predictive reference state generating means includes a plurality of latch circuits, a one-line memory and a lead line,
The image decoding apparatus according to claim 4, wherein the values of the symbols surrounding the decoding target symbol can be referred to.