JPH0934439A - Pixel data enhancement processing device and pixel data enhancement processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a desired emphasis process against picture element data at real time by emphasis-processing against a nonexistent picture element as an insignificant picture element on the designated position in an emphasis buffer. SOLUTION: This picture element data emphasis processing device is provided with an emphasis buffer 31 shifting in order input picture element data, and a processing means (individual AND-OR logic circuit) emphasis-processing a nonexistent picture element as an insignificant picture element, if it exists on the designated position in the emphasis buffer 31, when an existent picture element as a significant picture element appears in the designated range in the emphasis buffer 31. The picture element data are fed to the emphasis buffer 31, the picture element data are shifted in order in the emphasis buffer 31, and when an existent picture element as a significant picture element appears in the designated range in the emphasis buffer 31, emphasis process is performed against a nonexistent picture element as an insignificant picture element on the designated position in the emphasis buffer 31. Consequently, emphasis process can be univocally performed from the positional relation and the content, while transmitting the picture element data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a font data processing device capable of easily generating a desired type of character pattern such as shaded characters and outline emphasized characters from image data of a basic character pattern. .

[0002]

2. Description of the Related Art Conventionally, in order to display various emphasized characters such as shaded characters and outline emphasized characters, it is necessary to use character font data of each type. In this case, since each character font is prepared for each type of emphasized character, the data amount becomes enormous.

Therefore, by preparing a basic character font data set and emphasizing the basic character font data set as necessary, various character font types can be created with a small number of character font types. Attempts have been made to obtain letters.

Now, let us consider the character emphasis processing. For example, in the case of horizontally and vertically emphasized characters, the number of dots forming the character font is interpolated for the dots adjacent to the dots forming the character, as if the width of the lines and dots of the character were doubled. Make the character form as if it were emphasized characters, and if it is a shaded character,
Of the lines forming the character, the horizontal line is changed to a dot or dot, for example, and the dots separated from each other are changed in color to form a character as if a shadow were cast.

[0005]

Generally, what kind of method is used to perform various types of emphasis processing such as converting image data, for example, character pattern data into an outline emphasized character pattern or a shaded character pattern? Even before it is actually shown on the display. Therefore, it is necessary to read the pixel data from the frame buffer, perform emphasis processing on the pixel data, and save the emphasis processing result again in the display buffer.

Therefore, it is impossible to perform the emphasis processing in real time and use it for image display. Also,
The emphasis processing requires a considerable processing time and a memory for storing intermediate results.

Therefore, the object of the present invention is to
An object of the present invention is to provide a pixel data enhancement processing device and a pixel data enhancement processing method that do not require an intermediate result storage memory and can perform desired enhancement processing on pixel data in real time.

[0008]

In order to achieve the above object, the present invention is configured as follows. That is, when an existing pixel that is a significant pixel appears in an emphasis buffer that sequentially shifts the input pixel data and a specified range in this emphasis buffer, an insignificant pixel is displayed at a specified position in this emphasis buffer. If there is a non-existing pixel, the processing means for emphasizing the non-existing pixel is provided.

According to such a configuration, the pixel data is sent to the enhancement buffer, the pixel data is sequentially shifted in the enhancement buffer, and significant existing pixels appear within the specified range in the enhancement buffer. At this time, the emphasis process is performed on the non-existent pixel which is the involuntary pixel at the specified position in the emphasis buffer. In other words, when pixel data is sent through the enhancement buffer and when existing pixels appear within the specified range in the emphasis buffer, a method of applying emphasis processing to non-existing pixels at the specified position in the emphasis buffer is adopted. As a result, the emphasis process can be uniquely performed based on the positional relationship and the content during the pixel data transmission, and can be easily performed in real time. Further, since it can be performed in real time, the intermediate result storage memory becomes unnecessary.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, pixel data is sent to the enhancement buffer, the pixel data is sequentially shifted in real time in the enhancement buffer, and at the same time, significant pixels existing within a specified range in the enhancement buffer are detected. When it appears, the emphasis processing is performed on the non-existing pixel which is an involuntary pixel at the specified position in the emphasis buffer. The specified range and specified position in the emphasis buffer are given by parameter data. Then, by changing the parameter data, various enhancement processing can be performed on the pixel data.

For example, when an image of a character pattern is emphasized and displayed, pixel data of the character pattern is sent to the emphasis buffer, and the pixel data is sequentially shifted in real time in the emphasis buffer. Then, when an existing pixel that is a meaningful pixel as a pixel forming an image appears within a specified range in the enhancement buffer, a non-existent pixel that has no meaning in the image at a specified position in the enhancement buffer appears. If there is a pixel, it is emphasized.

In the present invention, the designated range and designated position in the enhancement buffer can be changed in various ways by the parameter data, so that the desired enhancement process can be carried out in real time by a simple method.

A feature of the present invention is that a real-time enhancement process of pixel data can be achieved, a frame buffer for storing pixel data after the enhancement is unnecessary according to the present invention, and a small enhancement mask is used to perform the enhancement. A buffer is enough. Further, in the present invention, only one parameter content is required to select a desired emphasis range and emphasis type.

(More Specific Embodiment 1) A specific embodiment of the present invention will be described below. In the following description, the bit content of pixel data is “1”.
When the bit content is "0", it indicates a non-existing pixel. Here, the existing pixels are significant pixels, in the case of a character font, the dots that represent the lines or points of the character, and the non-existing pixels are the dots that do not represent the lines or points of the character. is there.

Further, the meaning of emphasizing the pixel data means to give a color change or a contrast change of non-existing pixels surrounding the existing pixels within the emphasizing range. A specific example of the emphasis processing method will be described.

Pixel data enhancement includes one-dimensional horizontal enhancement, one-dimensional vertical enhancement, two-dimensional horizontal and vertical enhancement,
There are two-dimensional shadow enhancement, two-dimensional cage enhancement, and two-dimensional shadow enhancement with smooth corners.

Of these, the one-dimensional horizontal enhancement means that, as shown in FIG.
If a pixel adjacent to the existing pixel is a non-existing pixel, it is an emphasis process for processing as an emphasis pixel, and the pixel row before the process [I] is in a state as shown in [II] as a result of the emphasis process. .

Further, the one-dimensional vertical enhancement is as shown in FIG.
As shown in (b), in the pixel row in the vertical direction, if a pixel adjacent to the existing pixel is a non-existing pixel, the pixel is processed as an emphasized pixel. As a result of the processing, the state shown in [II] is obtained.

Further, the two-dimensional horizontal and vertical enhancement means that, as shown in FIG. 1C, with respect to the adjacent pixel in the horizontal direction and the vertical direction, the adjacent pixel does not exist. If it is a pixel, it is an enhancement process that is processed as an enhancement pixel, and the pixel column before the process [I] is in a state as shown in [II] as a result of the enhancement process.

The two-dimensional shadow enhancement is
As shown in FIG. 1D, with respect to the adjacent pixels in the horizontal direction, the vertical direction, and the diagonal direction centering on the existing pixel, if the adjacent pixel is a non-existing pixel, the emphasis process is performed as an emphasis pixel. , [I] before processing, the result of the emphasis processing is as shown in [II].

The two-dimensional cage enhancement (outline enhancement) means, as shown in FIG. 1 (e), if an adjacent pixel in the diagonally upper direction of an existing pixel is a non-existing pixel, the pixel position is used. This is an emphasis process for processing non-existing pixels on the diagonally higher position as an emphasis pixel, and a pixel row before the process of [I] becomes a state of II as a result of the emphasis process.

As shown in FIG. 1 (f), the two-dimensional shadow enhancement with smooth corners means that if the surrounding pixels of an existing pixel are non-existing pixels, the surrounding non-existing pixels are processed as enhanced pixels. As a result of the emphasis processing, the pixel column before the processing I, which is the emphasis processing, is brought into a state as shown in [II].

A specific processing method will be described below. [One-dimensional horizontal enhancement (see FIG. 2)] In the one-dimensional horizontal enhancement processing, while the pixel data is shifted in the display display order by the horizontal line buffer, the existing pixels appear in the designated enhancement region, and the horizontal line buffer This is a process of emphasizing the non-existing pixels at the center position of the horizontal line buffer when there is a non-existing pixel at the center position, and a process of emphasizing the pixels to the left and right of the existing pixel.

FIG. 2A is a diagram for explaining the state of one-dimensional horizontal enhancement processing, and shows a horizontal line buffer HB for horizontal enhancement processing. Horizontal line buffer HB
Is a buffer having a capacity for a plurality of pixels, and in the drawing, when pixel data is input from the left end side, pixel data emphasized from the right end is output. Horizontal line buffer H
The processing in B is as follows.

To perform one-dimensional horizontal enhancement, each line of pixel data is passed through the horizontal line buffer HB. Then, in this horizontal line buffer HB, the input pixel data is shifted from left to right in real time. And
During this shift, when a pixel exists at any position within the emphasis range defined by the horizontal emphasis parameter and no pixel exists at the center position CP of the horizontal line buffer HB, the center pixel is emphasized. To do.

The horizontal emphasis parameter is a parameter that determines which range of the area of the horizontal line buffer HB is to be emphasized. In the present invention, a pixel is placed at any position within the emphasis range according to the set horizontal emphasis parameter. And the pixel does not exist at the center position CP of the horizontal line buffer HB, the center pixel is emphasized.

For example, as shown in FIG. 2B, when the horizontal emphasis parameter is set to 2 pixels on the right and 2 pixels on the left, the horizontal line buffer HB has two pixels on the left and right (front and back) of the center position CP. Each minute is managed as an emphasis processing range, and if any one of the pixel data in the emphasis processing range is an existing pixel and the center position CP is not an existing pixel, the pixel at the center position is emphasized. . As a result, the output pixel data string is as shown in the figure.

Therefore, one-dimensional horizontal enhancement processing can be realized with simple control. The flow of processing will be specifically shown.

Consider the following bit string. “········································································································· 10001000 "Displays a pixel (indicates that it is an existing pixel), and". "Is neither.

It is assumed that it is desired to emphasize the display pixels by 2 bits each on the left and right sides (2 pixels on the left and right sides). Therefore, the emphasis processing range is 5 bits (5 pixels), and the data of "... 0 | 00100 | 0 ... | ** 1 ** | 0 ... Here, "*" is the highlighted pixel. Further, the portion surrounded by “| |” is the emphasis range.

That is, "... 0001000 ..
When the data of "..." is shifted in real time and moves to the emphasis range, in the present invention, times t1, t2,
(T1) 0001000 ｜ ・ ・ ・ ・ ・ ｜ ・ ・ ・ ・ ・ ・ ・ ・ (t2) ・ 000100 ｜ 0 ・ ・ ・ ・ ｜ ・ ・ ・ ・ ・ ・ ・ ・ (t3) ・ ・00010 ｜ 00 ・ ・ ・ ｜ ・ ・ ・ ・ ・ ・ ・ ・ (t4) ・ ・ ・ 0001 ｜ 000 ・ ・ ｜ ・ ・ ・ ・ ・ ・ (t5) ・ ・ ・ ・ 000 ｜ 10 * 0 ・ ｜ ・・ ・ ・ ・ ・ ・ ・ (T6) ・ ・ ・ ・ ・ 00 ｜ 01 ** 0 ｜ ・ ・ ・ ・ ・ ・ ・ ・ (t7) ・ ・ ・ ・ ・ ・ 0 ｜ 001 ** ｜ 0 ・ ・ ・ ・・ ・ ・ (T8) ・ ・ ・ ・ ・ ・ ・ ｜ 00 * 1 * ｜ * 0 ・ ・ ・ ・ ・ ・ (t9) ・ ・ ・ ・ ・ ・ ・ ｜ 0 ＊＊ 1 ｜ ＊＊ 0 ・ ・ ・・ ・ (T10) ・ ・ ・ ・ ・ ・ ｜ ･ ･ 0 ＊＊ ｜ 1 ＊＊ 0 ・ ・ ・ ・ (t11) ・ ・ ・ ・ ・ ・ ｜ ・ ・ ・ 0 * ｜ ＊ 1 ＊＊ 0 ・ ・ ・(t12) ・ ・ ・ ・ ・ ・ ｜ ・ ・ ・ ・ 0 ｜ ＊＊ 1 ＊＊ 0 ・ ・ (t13) ・ ・ ・ ・ ・ ・ ｜ ・ ・ ・ ・ ・ ｜ 0 ＊＊ １ ＊＊＊ ・"1" in emphasis range When a pixel at the center position of the emphasis range is “0” (non-existing pixel), the pixel is processed so as to be a pixel of “*”, and as a result, Original "0001000"
The pixel array (bit array) that becomes is finally "0 ** 1 **"
The pixel row (bit row) becomes "0". That is, when the pixel is "1", the left and right two pixels are emphasized.

Conventionally, a pixel to be displayed is searched from the frame buffer by some method and the left and right sides thereof are emphasized. This method takes time to search. However, in the present invention, instead of searching for data from the frame buffer, a FIFO is provided in the path for sending data to the frame buffer, and the processing is performed therein. This saves you the trouble of searching data.

Normally, when a pixel of interest (pixel of "1" (existing pixel)) such as "0001000" comes,
It is easy to think that the left and right sides (right and left of the pixel of "1") should be emphasized at the same time. However, although this complicates the processing and the hardware configuration, the present invention can simplify the processing and also the hardware configuration for the emphasis processing.

[One-dimensional vertical emphasis processing (see FIG. 3)] One-dimensional vertical emphasis processing shifts a set of rows of pixel data in the display order by the vertical buffer while displaying a specified emphasis range in the vertical buffer. If a non-existing pixel exists at the center position of the vertical buffer when an existing pixel appears inside, the process is to emphasize the non-existing pixel at the center position of this vertical buffer, and the pixels above or below the existing pixel are emphasized. Processing.

FIG. 3A is a diagram for explaining the state of one-dimensional vertical enhancement processing, and shows a vertical line buffer VB for vertical enhancement processing. Vertical line buffer VB
Is a buffer having a capacity for a plurality of pixels, and in the figure, when pixel data is input in parallel from the left side of the vertical line buffer VB, emphasized pixel data is output in parallel from the right side.

The processing in the vertical line buffer VB is as follows. To perform one-dimensional vertical enhancement, each line of pixel data is passed through the vertical line buffer VB. Then, in this vertical line buffer VB, the input pixel data is shifted from left to right in real time. Then, during this shift, if a pixel exists at any position within the emphasis range defined by the vertical emphasis parameter and no pixel exists at the center position CP of the vertical line buffer VB, the center pixel is set as the center pixel. Emphasize.

The vertical emphasis parameter is a parameter that determines which area of the area of the vertical line buffer VB (arrangement area in the vertical direction) is emphasized. In the present invention, the emphasis parameter is emphasized according to the set vertical emphasis parameter. When there is an existing pixel at any position within the range and there is no existing pixel at the central position CP of the vertical line buffer VB, the central pixel is emphasized.

For example, as shown in FIG. 3B, when the vertical emphasis parameter is set to 2 pixels above and 2 pixels below, in the vertical line buffer VB, two pixels above and below the center position CP are centered. Each is managed as an emphasis processing range,
When any one of the contents of the pixel data in the emphasis processing range is the existing pixel and there is no existing pixel at the central position CP, the central pixel is emphasized. As a result, the output pixel data string is as shown in the figure.

As described above, in order to perform one-dimensional vertical enhancement, each line of pixel data is given pixel data of a set of lines defined by the upper and lower enhancement parameters in parallel by the vertical buffer, and from left to right. When real-time shift is performed to, the center pixel is emphasized when there is a pixel existing in any position within the emphasis range defined by the vertical emphasis parameter during the shift and there is no pixel existing in the center position. I chose Therefore, it becomes possible to realize the one-dimensional vertical enhancement process with simple control.

The one-dimensional horizontal and vertical emphasis processing has been described above. Next, the two-dimensional horizontal and vertical emphasis processing will be described. [Two-dimensional horizontal and vertical enhancement (see FIG. 4)] Two-dimensional horizontal and vertical enhancement processing shifts a set of rows of pixel data in a display order in a buffer in the shape of a combination of horizontal and vertical buffers. On the other hand, when an existing pixel appears in the emphasis range, if there is a non-existing pixel at the center position of the buffer, this process is emphasized, and the left, right, upper and lower pixels of the existing pixel are emphasized.

To perform the two-dimensional horizontal and vertical emphasis processing, a line buffer in which the line buffers for the one-dimensional horizontal emphasis processing and the one-dimensional vertical emphasis processing are arranged orthogonally is used. That is, as shown in FIG. 4A, a horizontal line buffer H which is a line buffer for horizontal emphasis processing.
Two-dimensional line buffer TD in which B and a vertical line buffer VB, which is a line buffer for vertical emphasis processing, are orthogonally arranged.
B is used.

As shown in FIG. 4A, the horizontal line buffer HB portion and the vertical line buffer VB portion are buffers each having a capacity of a plurality of pixels, and the central intersection point is the central position CP. In the figure, when pixel data is input in parallel from the left side of the vertical line buffer VB, the emphasized pixel data is output in parallel from the right side.

Of course, in the horizontal line buffer HB portion, when pixel data is input from the left end side, it is sequentially shifted to the right in real time, and pixel data emphasized from the right end is output.

This example is a combination of one-dimensional horizontal enhancement and one-dimensional vertical enhancement. Pixel data for the required number of lines for vertical emphasis is input from the input side (left side in the figure) of the vertical line buffer VB and becomes parallel data input, but the horizontal line buffer HB portion is at the center corresponding to one line. It is in. Therefore, the pixel data string corresponding to the line position is serially sent from the input side to the output side (from the left side to the right side in the figure) in the horizontal line buffer HB portion.

Therefore, the pixel data input to the horizontal line buffer HB portion is shifted from left to right in real time, and during this shift, the pixel is located at any position within the enhancement range defined by the horizontal enhancement parameter. If the pixel exists and the pixel does not exist at the center position CP of the horizontal line buffer HB, the center pixel is emphasized.

The processing in the vertical line buffer VB part is
It looks like this: By inputting the pixel data corresponding to each line at the time of video display on the display to the corresponding array element position of the vertical line buffer VB, the input pixel data in this vertical line buffer VB portion is from left to right. Shift in real time. Then, during this shift, if a pixel exists at any position within the emphasis range defined by the vertical emphasis parameter and no pixel exists at the center position CP of the vertical line buffer VB, the center pixel is set as the center pixel. Emphasize.

When the video display control of the display is a television scan (XY scan) system, the screen is displayed by displaying pixels while scanning one line in the horizontal direction. In this case, the horizontal line buffer HB portion is used. The line input to corresponds to the line on the display. Then, in terms of timing, the pixel shifted to the center position CP in the horizontal line buffer HB portion becomes the pixel provided for display at that time.

The array element position of the vertical line buffer VB portion corresponds to each horizontal line of the television scan, but among the array elements of the vertical line buffer VB portion, the array element position corresponding to the horizontal line buffer HB portion is the current position. ,
It corresponds to the position of the TV scan, and the others correspond to the display lines past or future from that point.

Therefore, the corresponding line position of the image sequentially shifts to the array element position of the vertical line buffer VB portion as the control of the television scan progresses, and the pixels of each corresponding line are input. Within the range defined by the horizontal enhancement parameter, the pixel data at the center position CP of the horizontal line buffer HB is emphasized when the above enhancement condition is satisfied, and within the range defined by the vertical enhancement parameter. Then, when the above-mentioned emphasis condition is satisfied, the pixel data at the center position CP of the vertical line buffer VB portion is emphasized and given to the display as an image signal for display, and the result is [II] in FIG. 4B. As shown in the figure, it is possible to display an image that is image-enhanced so that the enhanced pixel appears around the existing pixel.

The example shown in FIG. 4B is an example in which horizontal enhancement parameters are set to two pixels on the right and two pixels on the left. In this case, in the horizontal line buffer HB, the center position CP is used as the center of the left and right pixels. 2 pixels (before and after) are managed as an emphasis processing range, and if any one of the contents of the pixel data in the emphasis processing range has a pixel and no pixel exists at the center position CP, Emphasize pixels.

Further, the vertical emphasis parameter is set to two pixels above and two pixels below, and in this case, in the vertical line buffer VB, two pixels above and below the center position CP are set as the emphasis processing range. If there is any one pixel in the content of the pixel data within the emphasis processing range and there is no pixel at the central position CP, the central pixel is emphasized. As a result, the output pixel data string is as shown in the figure.

As described above, in order to perform two-dimensional horizontal and vertical emphasis, a buffer having a structure in which a horizontal buffer and a vertical buffer are arranged orthogonally is used, and each line of pixel data is defined by a vertical emphasis parameter (vertical emphasis parameter). By giving it to the vertical emphasis buffer together with a set of lines, the buffer structure (structure in which the horizontal buffer and the vertical buffer are orthogonally arranged) shifts from left to right in real time, and is specified by the horizontal and vertical emphasis parameters during the shift. When a pixel exists at any position within the highlighted range and does not exist at the central position, the central pixel is emphasized. In this way, the processing can be simplified and the hardware configuration for the emphasis processing can be simplified.

The above is the description of the two-dimensional horizontal and vertical emphasis processing. Next, the two-dimensional shadow (bag) emphasis processing will be described. [Two-dimensional shadow (bag) enhancement (see FIG. 5)] The two-dimensional shadow (bag) enhancement processing uses a two-dimensional array enhancement buffer and sets a plurality of adjacent lines of an image as one set. Minute pixel data is input in parallel to each array element of the enhancement buffer of the two-dimensional array and shifted in the display display order by the enhancement buffer, while the pixels existing in the enhancement range are left, right, top, or bottom. The pixel of is emphasized.

To perform the two-dimensional shadow (bag) emphasis process, a buffer having an m × n matrix structure is used.
That is, as shown in FIG. 5A, m pixels in the horizontal direction (horizontal direction) and n pixels in the vertical direction (vertical direction) (however,
A two-dimensional enhancement processing buffer EB having a matrix configuration of m, n = 5 or more and any odd number) is used.

CP is the center position of the two-dimensional enhancement processing buffer EB. When a plurality of lines of pixel data are simultaneously input from the left side of the two-dimensional enhancement processing buffer EB in the figure, they are sequentially shifted to the right side in the figure in real time. Then, the pixel at the central position CP is controlled so as to be emphasized according to the condition.

By inputting the pixel data corresponding to each line at the time of display on the display, to the array element positions corresponding to the vertical direction of the enhancement buffer EB of the two-dimensional array, the input pixel data is stored in the enhancement buffer EB. Shift from left to right in the figure in real time. Then, during this shift, when a pixel exists at any position within the emphasis range defined by the emphasis parameter and no pixel exists at the center position CP of the emphasis buffer EB, the center pixel is emphasized.

When the video display control of the display is a television scan (XY scan) system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, the center of the emphasis buffer EB is displayed. The line input to the buffer portion at the horizontal line position passing through the position CP corresponds to the line displayed on the display. Then, in terms of timing, the pixel shifted to the center position CP of the enhancement buffer EB becomes the pixel provided for display at that time.

The vertical array element position of the enhancement buffer EB corresponds to each horizontal line of the television scan. Of these vertical array elements, the array element position corresponding to the buffer portion of the horizontal line position passing through the center position CP. Corresponds to the position of the TV scan at the present time, and the others correspond to the display lines past or future from that time.

Therefore, as the control of the television scan progresses, the corresponding line positions of the image sequentially shift to the vertical array element positions, and the pixels of each corresponding line are input. If the pixel data at the center position CP is emphasized and given to the display when the emphasis condition is satisfied within the range defined by, the existing pixels are displayed as shown in [II] of FIG. 5B. It is possible to display an image that is image-enhanced so that the pixels that have been subjected to the emphasis process appear around.

In FIG. 5, for shadow (bag) emphasis, pixel data for the required number of lines is parallelly input from the input side (left side in the figure) of the emphasis buffer EB which is the buffer for the two-dimensional emphasis processing. It is input corresponding to each line position, and is sequentially shifted in real time in the two-dimensional emphasis processing buffer EB toward the output side in the right direction in the figure.

At the vertical array element positions of the enhancement buffer EB for the two-dimensional enhancement process, the corresponding line positions of the image are sequentially shifted with the progress of the control of the television scan, and the pixels of each corresponding line are input. Therefore, in the enhancement buffer EB, a pixel exists at any position within the enhancement range defined by the enhancement parameter during real-time pixel data shift, and the two-dimensional enhancement processing buffer EB When no pixel exists at the central position CP, the pixel at the central position CP is emphasized.

In the example of FIG. 5B, the emphasis parameter is centered on the center position CP of the two-dimensional emphasis processing buffer EB, and the upper two pixels, the lower two pixels, the right two pixels, and the left two pixels. In the two-dimensional emphasizing process buffer EB, two pixels each vertically (vertically) and horizontally (front and back) of the center position CP are managed as an emphasizing process range, and the emphasizing process is performed. If any one of the contents of the pixel data sent to the range has a pixel, if there is no pixel at the center position for each line, the center pixel is emphasized. as a result,
The output pixel configuration as shown in the figure can be obtained.

As described above, as a method of performing two-dimensional shadow (bag) emphasis on pixel data of existing pixels (pixel data having an attribute relating to existence), a buffer having a plurality of rows and a plurality of columns matrix is used as an emphasis buffer. In addition, the data corresponding to a set of display lines determined by the enhancement parameter is input to the enhancement buffer and shifted in the row direction, while the pixel data corresponding to the position determined by the enhancement parameter is enhanced.

The emphasis process is performed so that when there is a pixel existing in the emphasis range (left or right or above or below the center bit position of the emphasis buffer), the existence pixel is present in the emphasis bit in the center bit position of the emphasis buffer. It is processed for a certain pixel. A horizontal line passing through the center bit position of the emphasis buffer is set as a display control line corresponding to the display control of the display, and shift control is performed in real time so that the pixel at the center bit position of the emphasis buffer becomes the display pixel of the display control of the display. As a result of emphasizing processing according to conditions, it becomes possible to realize two-dimensional shadow (bag) emphasizing processing with simple control.

The two-dimensional shadow (bag) emphasis has been described above. Next, the two-dimensional cage (bag) emphasis will be described. [Two-dimensional cage (bag) enhancement (see FIG. 6)] The two-dimensional cage (bag) enhancement processing uses a two-dimensional array enhancement buffer, and sets a plurality of adjacent lines of an image as one set.
A set of pixel data is input in parallel to each array element of the two-dimensional enhancement buffer and shifted in the display display order by the enhancement buffer while the existing pixels are shifted to the active position of the enhancement buffer. When there is a non-existing pixel at the center of the buffer, this pixel is emphasized.

To perform the two-dimensional cage (bag) emphasis processing, a buffer having an m × n matrix structure is used. That is, as shown in FIG. 6A, the horizontal direction (horizontal direction)
m pixels, n pixels in the vertical direction (vertical direction) (however, m, n
A two-dimensional enhancement processing buffer EB having a matrix configuration of (= an arbitrary odd number of 5 or more) is used.

CP is the center position of the two-dimensional enhancement processing buffer EB. When a plurality of lines of pixel data are simultaneously input from the left side of the two-dimensional enhancement processing buffer EB in the figure, they are sequentially shifted to the right side in the figure in real time. Then, the pixel at the central position CP is controlled so as to be emphasized according to the condition.

By inputting the pixel data corresponding to each line when the video is displayed on the display to the array element positions corresponding to the vertical direction of the enhancement buffer EB of the two-dimensional array,
In this emphasis buffer EB, the input pixel data is shifted from left to right in the figure in real time. Then, during this shift, when a pixel exists at any position within the emphasis range defined by the emphasis parameter and no pixel exists at the center position CP of the emphasis buffer EB, the center pixel is emphasized.

When the video display control of the display is a television scan (XY scan) system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, the center of the emphasis buffer EB is displayed. The line input to the buffer portion at the horizontal line position passing through the position CP corresponds to the line displayed on the display. Then, in terms of timing, the pixel shifted to the center position CP of the enhancement buffer EB becomes the pixel provided for video display on the display at that time.

The vertical array element position of the enhancement buffer EB corresponds to each horizontal line of the television scan. Of these vertical array elements, the array element position corresponding to the buffer portion of the horizontal line position passing through the center position CP. Corresponds to the position of the TV scan at the present time, and the others correspond to the display lines past or future from that time.

Therefore, as the control of the television scan progresses, the corresponding line position of the image sequentially shifts to the vertical array element position, and the pixels of each corresponding line are input. When there is an existing pixel at the activation position defined by 1. and there is no existing pixel at the center position CP, when the pixel data of the center position CP is emphasized and given to the display and is used for display, FIG.
As shown in [II] of (b), it is possible to display an image that is image-enhanced so that the enhanced pixel appears in the vicinity of the existing pixel.

In FIG. 6, for cage (bag) emphasis, pixel data for the required number of lines are input in parallel from the input side (left side in the figure) of the two-dimensional emphasis processing buffer EB corresponding to each line position. Then, the inside of the two-dimensional enhancement processing buffer EB is sequentially shifted in real time toward the output side in the right direction in the drawing.

In the two-dimensional emphasis processing buffer EB, a pixel exists at the activation position defined by the emphasis parameter during this shift, and no pixel exists in the center position CP of the two-dimensional emphasis processing buffer EB. In this case, the pixel at the center position CP is emphasized.

For example, as shown in FIG. 6B, when the enhancement parameter is set to the second pixel to the left of the second pixel below the center position CP of the enhancement buffer EB for two-dimensional enhancement processing. Then, with respect to the center position CP as a center, the coordinate position of the left second pixel at the second lower pixel is the activation position AP.
Becomes

Then, the emphasizing buffer EB manages the activation position AP as an emphasizing process monitoring area, and when the content of the pixel data sent to the emphasizing processing monitoring area is an existing pixel, the center position is detected. When the pixel of CP is a non-existing pixel, the pixel of the center position CP is controlled to be emphasized. As a result, the output pixel configuration shown in the figure is obtained.

As described above, in the two-dimensional cage (bag) emphasis, an emphasis buffer having a matrix structure of a plurality of rows and a plurality of columns is used, and data corresponding to a set of display rows determined by the emphasis parameter is displayed. While inputting to the emphasis buffer and shifting in the row direction, when the data of the existing pixel appears at the activation position in the emphasis buffer defined by the emphasis parameter, and the center position of the emphasis buffer is a non-existing pixel, The pixel at the center position is emphasized.

In the case of the example shown in FIG. 6, the activation positions AP are the upper two pixels and the left one pixel of the center pixel of the enhancement buffer. During the shift, when the existing pixel appears at any of the activated positions of the emphasis buffer and the center position is the non-existing pixel, the pixel at the center position is emphasized.

Therefore, it becomes possible to realize the two-dimensional shadow (bag) emphasizing process with simple control. The above has described the two-dimensional shadow enhancement. Next, the two-dimensional shadow (bag) enhancement with smooth corners will be described.

[Two-dimensional shadow (bag) enhancement with smooth corners (see FIG. 7)] This enhancement processing is similar to the shadow enhancement processing described above. The only difference is the activation region in the enhancement buffer, and the position of the enhancement processing (activation position) is determined for each position in the activation region.
The activated area is diamond-shaped.

To perform a two-dimensional (bag) enhancement that forms a shadow with smooth corners, a buffer having an m × n matrix structure is used. That is, as shown in FIG. 7A, horizontal (horizontal) m pixels and vertical (vertical)
A two-dimensional enhancement processing buffer EB having a matrix structure of n pixels (however, m and n = an arbitrary odd number of 5 or more) is used.

CP is the center position of the two-dimensional enhancement processing buffer EB. When a plurality of lines of pixel data are simultaneously input from the left side of the two-dimensional enhancement processing buffer EB in the figure, they are sequentially shifted to the right side in the figure in real time. Then, the pixel at the central position CP is controlled so as to be emphasized according to the condition.

By inputting the pixel data corresponding to each line at the time of display on the display to the array element positions corresponding to the vertical direction of the enhancement buffer EB of the two-dimensional array, the input pixel data is stored in this enhancement buffer EB. Shift from left to right in the figure in real time. Then, during this shift, when a pixel exists at any position within the emphasis range defined by the emphasis parameter and no pixel exists at the center position CP of the emphasis buffer EB, the center pixel is emphasized.

When the video display control of the display is a television scan (XY scan) system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, the center of the emphasis buffer EB is displayed. The line input to the buffer portion of the horizontal line position passing through the position CP corresponds to the line of the video display on the display. Then, in terms of timing, the pixel shifted to the center position CP of the enhancement buffer EB becomes the pixel provided for video display on the display at that time.

The vertical array element position of the enhancement buffer EB corresponds to each horizontal line of the television scan. Of these vertical array elements, the array element position corresponding to the buffer portion of the horizontal line position passing through the center position CP. Corresponds to the position of the TV scan at the present time, and the others correspond to the display lines past or future from that time.

Therefore, as the control of the television scan progresses, the corresponding line positions of the image sequentially shift to the vertical array element positions, and the pixels of each corresponding line are input. If an existing pixel appears within the activation range defined by, and the pixel data at the center position CP of the emphasis buffer EB is a non-existing pixel, the pixel data at the center position CP is emphasized and given to the display for display. By doing so, as shown in [II] of FIG. 7B, it is possible to display an image that is image-enhanced so that the pixels subjected to the emphasis process appear around the existing pixels.

In FIG. 7, in order to emphasize two-dimensional shadows (bags) with smooth corners, pixel data for the required number of lines are input in parallel to the input side of the emphasis buffer EB for this two-dimensional emphasis processing (see FIG. From the left side) corresponding to each line position and sequentially shifted in real time in the emphasizing buffer EB toward the output side in the right direction in the figure.

The activation region (enhancement range) is, for example, a diamond-shaped region centered on the center position CP of the enhancement buffer EB for two-dimensional enhancement processing, and a pixel existing at any position of this activation region. When the pixel at the center position CP is a non-existing pixel when appears, the pixel is controlled to be emphasized.

At the vertical array element positions of the enhancement buffer EB for the two-dimensional enhancement process, the corresponding line positions of the image are sequentially shifted as the television scan control progresses, and the pixels of the corresponding lines are input. Therefore, in the enhancement buffer EB, during the shift of pixel data,
A pixel exists at any position in the activation area defined by the emphasis parameter, and the pixel at the activation position determined at the pixel position is the data of the nonexistent pixel. An emphasis processing result such as 7 is obtained.

In the example of FIG. 7 (b), the emphasis parameter is centered on the center position CP of the emphasis buffer EB for two-dimensional emphasis processing, and the upper 2 pixels, the lower 2 pixels, the right 2 pixels, the left 2 pixels, and the diagonally upper position. 1 pixel and 1 pixel diagonally below,
In this case, in the two-dimensional emphasis processing buffer EB, two pixels each in the vertical direction (vertical direction), two pixels in the horizontal direction (front and rear) and one pixel in the diagonally upper and lower direction with respect to the center position CP are managed as activation areas AR. , If the content of the pixel data sent to the activation area AR is any one of the existing pixels, the pixel data of the center position CP of the enhancement buffer EB is the non-existing pixel. As a result of emphasizing, the pixel configuration as shown in the figure is obtained.

As described above, in order to perform the two-dimensional shadow (bag) enhancement with smooth corners, the enhancement buffer EB having a matrix configuration of a plurality of rows and a plurality of columns is used, and the pixel data corresponding to each line of the video display on the display is stored. Among them, one set of lines corresponding to the line defined by the emphasis parameter is sent to the emphasis buffer, and the emphasis buffer shifts from left to right (in the row direction) in real time. At the vertical array element position of the enhancement buffer EB, the corresponding line position of the image sequentially shifts so that the pixels of each corresponding line are input as the control of the television scan progresses. By providing the pixel for display, in the enhancement buffer EB, the pixel exists at any position within the enhancement range defined by the enhancement parameter during real-time pixel data shift, and the two-dimensional enhancement processing buffer EB When a pixel does not exist at the center position CP of the center position CP, when the pixel at the center position CP is emphasized, a two-dimensional shadow (bag) emphasized image with smooth corners can be displayed on the display, and simple control is possible. With, you can apply two-dimensional shadow enhancement processing with smooth corners in real time.

(More Specific Embodiment 2) The various emphasizing processing methods have been described above, but a specific hardware configuration example will be described below.

In the pixel data, the pixel data content “1” means an existing pixel, and the pixel data content “0” means a non-existing pixel. In other words, if the target is a character image, the pixel data “1” means that the dot data forming the character font is “1”, and the dot data is “1” on the display. Indicates that a dot is displayed, and "0" indicates that nothing is displayed.

The meaning of emphasizing the pixel data is to change the color and the target of the non-existing pixels surrounding the pixels existing in the emphasizing range. For example, emphasizing means highlighting, and emphasizing a pixel means highlighting a pixel.

[Configuration Example of One-dimensional Real-time Image Data Enhancement Processing Device] A configuration example of the one-dimensional real-time image data enhancement processing device for easily performing one-dimensional horizontal enhancement processing in real time is shown in FIG. Shown in.

In FIG. 8, 10 is a one-dimensional real-time image data emphasis processing device, 11 is an emphasis buffer,
12 is an AND-OR logic device, and 13 is an emphasis control register.

Of these, the emphasis buffer 11 is a line buffer, and in the figure, a structure using a line buffer having a structure of 9 pixels (9-bit serial) is shown. The emphasis buffer 11 has an input side on the left side of the drawing, and when an image is serially input line by line from the input side, it is sequentially shifted to the right side in real time. In the enhancement buffer 11, the array element position of the central fourth pixel (fourth bit) in the array of nine pixels (9-bit serial) is the central position CP.

The AND-OR logic device 12 is a device for performing an emphasis process, and is a logic device composed of an AND gate and an OR gate, and 9 sets of 2-input ANDs are arranged according to the number of arrangements of the emphasis buffer 11. It consists of gates AND1 to AND9 and one OR gate OR. The OR gate OR takes the OR logic of the outputs of the 9 sets of 2-input AND gates AND1 to AND9, and the output of the OR gate OR is the AND-OR logic device 1
This is the output of 2 and becomes the emphasis processing output.

The emphasis control register 13 is a register for setting horizontal emphasis control data, and the emphasis buffer 1
A register having a 9-bit configuration is used in accordance with the number of 1's arranged, and the data string set therein is provided as control data to each corresponding AND gate of the AND-OR logic device 12.

Specifically, of the 9-bit data of the emphasis control register 13, the first bit data is AND-O.
9 sets of two-input AND gates AND1 to AND9 of the R logic unit 12
Of the 9-bit data of the emphasis control register 13, the second bit data is input to one input terminal of the first 2-input AND gate AND1 and the second bit data is 9 sets of 2 of the AND-OR logic device 12. Of the input AND gates AND1 to AND9, the third bit data of the 9-bit data of the emphasis control register 13 is input to one input terminal of the second 2-input AND gate AND2, and the third bit data is AND-OR logic device. Of the 9 sets of 12 2-input AND gates AND1 to AND9,
It is configured to be input to one input terminal of the third two-input AND gate AND3, and so on, to one input terminal of the corresponding AND gate.

Of the 9 sets of 2-input AND gates AND1 to AND9 of the AND-OR logic device 12, the other input terminal of the first 2-input AND gate AND1 has the first array of the enhancement buffer 11. The retained data of the element is input, and A
The data held in the second array element of the enhancement buffer 11 is input to the other input terminal of the second 2-input AND gate AND2 of the ND-OR logic device 12, and the third data of the AND-OR logic device 12 is input. The holding data of the third array element of the enhancement buffer 11 is input to the other input terminal of the 2-input AND gate AND3, and so on.
The configuration is such that it is input to the other input terminal of the ND gate.

The operation of the present apparatus having such a configuration will be described. In this apparatus, desired horizontal enhancement control data is set in advance in the enhancement control register 13. Then, when the image data is serially input line by line to the enhancement buffer 11, the enhancement buffer 11 sequentially shifts the image data in real time. The enhancement buffer 11 is a line buffer having a serial array of 9 pixels, and the AND-OR logic unit 1 stores the data at each array position at that time.
It is input to the corresponding 2-input AND gate of the 9 sets of 2-input AND gates AND1 to AND9.

On the other hand, each of the two-input AND gates AND1 to AND9 of the AND-OR logic device 12 receives the corresponding one of the horizontal emphasis control data of the emphasis control register 13, and therefore, each 2-input AND gate. Gate AND1 ~ AN
D9 takes the AND logic of the pixel data given from the enhancement buffer 11 and the horizontal enhancement control data. When both are "1", the AND gate outputs "1". The output of each 2-input AND gate AND1-AND9 passes through the OR gate OR and becomes the output of the AND-OR logic unit 12.

After all, since the bit pattern of the horizontal emphasis control data set in the emphasis control register 13 and the value of each image data in the emphasis buffer 11 are ANDed, the horizontal emphasis control data of 9-bit structure is obtained. If the bit pattern is such that only the central bit of "1" is set to "1" and the other bits are set to "0", when "1" appears in the central array element of 9 pixels in the enhancement buffer 11, the AND-OR logic unit 1
The output of 2 becomes "1", and becomes "0" under other conditions.

Similarly, if a bit pattern in which only both sides of the central bit of the horizontal enhancement control data of 9-bit structure are set to "1" and the other bits are set to "0", the enhancement buffer 11 outputs 9 bits.
When a "1" appears in at least one of the array elements on both sides of the array element in the center of the pixel, the AND-OR logic unit 12
Output becomes "1", and becomes "0" under other conditions.

When "1" appears in the desired array element and "1" does not appear in the center array element of the enhancement buffer 11, among the 9 pixel array elements in the enhancement buffer 11, In order to perform the pixel enhancement processing for the array element in the center of, the following may be performed.

That is, the contents of the array element at the center of the emphasis buffer 11 are inverted by an inverter, the output of this inverter and the output EMPEN of the AND-OR logic unit 12 are ANDed, and the result is "1". When
The contents of the corresponding pixel of the central array element of the emphasis buffer 11 are emphasized.

When the video display control of the display is a television scan (XY scan) system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, input is made to the emphasis buffer 11. The line to be displayed becomes the display line. Then, if the pixel at the center position CP of the emphasis buffer 11 is set to be the display display corresponding pixel at that time, the pixel shifted to the center position CP of the emphasis buffer EB at that time is timing-wise. Pixels to be used for display on the display. Therefore, if the emphasis processing is performed at the timing when the above-described emphasis condition is satisfied,
The one-dimensional horizontal enhancement processing as described with reference to FIG. 2 can be performed in real time by the hardware having a simple configuration.

As described above, the bit pattern of the horizontal emphasis control data enables the emphasis output to be generated when the pixel data “1” appears at a desired position (array element) in the emphasis buffer 11. Become.

The above is the description of the apparatus for one-dimensional real-time horizontal enhancement processing. Next, an apparatus for one-dimensional vertical emphasis processing will be described. [Example of configuration of one-dimensional real-time image data enhancement processing device for vertical enhancement processing]
FIG. 8 shows an example of the configuration of a one-dimensional real-time image data enhancement processing device that enables one-dimensional vertical enhancement processing to be easily performed in real time.

In FIG. 9, reference numeral 20 denotes a one-dimensional real-time image data emphasis processing device for vertical emphasis processing, and 21
Is an emphasis buffer, 22 is an AND-OR logic device, and 23 is an emphasis control register.

Of these, the emphasis buffer 21 is a parallel buffer, which is an array buffer for one line and one pixel, and in the figure, nine lines of an image can be input at the same time. The structure using the buffer of FIG. The enhancement buffer 21 has an input side on the upper side of the drawing, and is configured to shift to the lower side in real time when an image is input from the input side in 9-line parallel. In the emphasis buffer 21, the central position CP is the position of the central 4 pixels (4th bit) in the array of 9 lines (9-bit parallel) × 1 pixel.

The AND-OR logic device 22 is a device for performing emphasis processing, and is a logic device composed of an AND gate and an OR gate, and 9 sets of 2-input ANDs are arranged according to the number of arrays of the emphasis buffer 21. It consists of gates AND1 to AND9 and one OR gate OR. The OR gate OR takes the OR logic of the outputs of 9 sets of 2-input AND gates AND1 to AND9, and the output of the OR gate OR is the AND-OR logic device 2
This is the output of 2 and becomes the emphasis processing output.

The emphasis control register 23 is a register for setting horizontal emphasis control data, and is used for the emphasis buffer 2
A register having a 9-bit configuration is used in accordance with the number of 1's arranged, and the data string set here is provided as control data to each corresponding AND gate of the AND-OR logic device 22.

Specifically, of the 9-bit data of the emphasis control register 23, the first bit data is AND-O.
9 sets of two-input AND gates AND1 to AND9 of the R logic unit 22
Of the 9-bit data of the emphasis control register 23, the second bit data is input to one input terminal of the first 2-input AND gate AND1 and the second bit data is 9 sets of 2 of the AND-OR logic device 12. Of the input AND gates AND1 to AND9, which is input to one input terminal of the second 2-input AND gate AND2, and of the 9-bit data of the emphasis control register 23, the third bit data is the AND-OR logic device. Of 9 sets of 22 2-input AND gates AND1 to AND9,
It is configured to be input to one input terminal of the third two-input AND gate AND3, and so on, to one input terminal of the corresponding AND gate.

Of the nine sets of two-input AND gates AND1 to AND9 of the AND-OR logic device 22, the first input array of the enhancement buffer 21 is arranged at the other input terminal of the first two-input AND gate AND1. The retained data of the element is input, and A
The data held in the second array element of the enhancement buffer 21 is input to the other input terminal of the second 2-input AND gate AND2 of the ND-OR logic device 22 and the third data of the AND-OR logic device 22 is input. The holding data of the third array element of the enhancement buffer 21 is input to the other input terminal of the 2-input AND gate AND3, and so on.
The configuration is such that it is input to the other input terminal of the ND gate.

The operation of the present apparatus having such a configuration will be described. In this apparatus, desired vertical emphasis control data is set in the emphasis control register 23 in advance. Then, when the image data is input to the emphasis buffer 21 in parallel for nine lines corresponding to the display order, the emphasis buffer 21 sequentially shifts the image data in real time in synchronization with the video display control timing.

The emphasizing buffer 21 is a buffer having a parallel array of 9 pixels, and the data at each array position at that time is provided with 9 sets of 2-input ANs of the AND-OR logic device 22.
Input to the corresponding 2-input AND gate of the D gates AND1 to AND9.

On the other hand, among the two-input AND gates AND1 to AND9 of the AND-OR logic device 22, the corresponding vertical emphasis control data of the emphasis control register 23 are respectively inputted, and therefore, the two-input AND gates are used. Gate AND1 ~ AN
D9 takes the AND logic of the pixel data given from the enhancement buffer 21 and the vertical enhancement control data. When both are "1", the AND gate outputs "1". The output of each 2-input AND gate AND1-AND9 passes through the OR gate OR and becomes the output of the AND-OR logic unit 12.

After all, since the bit pattern of the vertical emphasis control data set in the emphasis control register 23 and the value of each image data in the emphasis buffer 21 are ANDed, the vertical emphasis control data of 9-bit structure is obtained. If the bit pattern is such that only the central bit of "1" is set to "1" and the other bits are set to "0", when "1" appears in the central array element of 9 pixels in the enhancement buffer 21, the AND-OR logic unit 2
The output of 2 becomes "1", and becomes "0" under other conditions.

Similarly, if a bit pattern in which only both sides of the central bit of the vertical emphasis control data of 9-bit structure are set to "1" and the other bits are set to "0", the emphasis buffer 21 outputs 9 bits.
When a "1" appears in at least one of the array elements on both sides of the array element in the center of the pixel, the AND-OR logic unit 22
Output becomes "1", and becomes "0" under other conditions.

When "1" appears in the desired array element and "1" does not appear in the central array element of the enhancement buffer 21, among the 9 pixel array elements of the enhancement buffer 21, the enhancement buffer 21 concerned. To emphasize the array element at the center of, the following can be done.

That is, the contents of the array element at the center of the emphasis buffer 21 are inverted by an inverter, the AND logic of the output of this inverter and the output EMPEN of the AND-OR logic unit 22 is taken, and the result is "1". When
An emphasis control output EMPEN is generated in order to emphasize the contents of the corresponding pixel in the central array element of the emphasis buffer 21.

When the video display control of the display is a television scan system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, the array element position at the center of the emphasis buffer 21 is displayed. The line input to (center position CP) becomes the display line. If timing control is performed so that the pixel at the center position CP of the enhancement buffer 21 becomes the display display corresponding pixel at that time, in terms of timing,
The pixel shifted to the center position CP of the enhancement buffer 21 becomes the pixel provided for display at that time.

Therefore, if the emphasizing process is performed at the timing when the above emphasizing condition is satisfied, the one-dimensional vertical emphasizing process as described with reference to FIG. 3 can be executed in real time by the hardware having a simple structure. Like

As described above, by the bit pattern of the vertical emphasis control data, the emphasis control output EMPEN is generated when the pixel data "1" appears at a desired position (array element) in the emphasis buffer 21, and the emphasis processing is performed. Will be able to do.

The above is an example of the emphasis processing apparatus used for the one-dimensional emphasis processing. There is also a two-dimensional emphasis process as the emphasis process, which will be described below. [Configuration Example of Two-dimensional Real-time Image Data Enhancement Processing Device] FIG. 10 shows a configuration example of the two-dimensional real-time image data enhancement processing device. FIG.
In 0, 30 is a two-dimensional real-time image data enhancement processing device, 31 is an enhancement buffer, and 32 is AND-
An OR logic unit, 33 is a horizontal enhancement control register, and 34 is a vertical enhancement control register.

Of these, the enhancement buffer 31 has a configuration in which a plurality of sets of line buffers are arranged in parallel, and in the figure, a configuration is shown in which a plurality of sets of line buffers of 9 pixels (9-bit serial) are used. 31a to 31n are the line buffers. The left side of each drawing of the emphasis buffer 31 is the input side, and when the image of n lines is input in parallel, the corresponding 1 line is input to each of the line buffers 31a to 31n, and these are sequentially moved to the right side in real time. It is a structure that is shifted. In the enhancement buffer 31, the array element position of the central fourth pixel (fourth bit) in the array of nine pixels (9-bit serial) in each of the line buffers 31a to 31n is the central position CP.

The horizontal emphasis control register 33 is a register for setting horizontal emphasis control data, and uses a register of 9 bits in accordance with the number of arrangements in each line buffer 31a to 31n of the emphasis buffer 31. The data string set in is AND-OR as control data
This is a configuration given to each corresponding AND gate of the logic device 32.

The vertical emphasis control register 34 is a register for setting vertical emphasis control data, and uses a 9-bit register according to the number of arrays of the emphasis buffer 31, and the data string set here is controlled. The data is given to each corresponding AND gate of the AND-OR logic device 32 as data.

The AND-OR logic device 32 is a device for performing emphasis processing, is a logic device composed of an AND gate and an OR gate, and has n + 1 sets of individual AND-OR logic circuits 32a ... 32n + 1.

In the case of the configuration shown in the figure, since the number of line buffers in the enhancement buffer 31 is n, a total of n + 1 sets of individual AND-OR logic circuits 32n + 1 for one set is additionally provided.

Individual AND-OR logic units 32a to 32n
+1 is a logic device composed of an AND gate and an OR gate, which have the same structure. That is, each of the individual AND-OR logic circuits 32 a to 32 n + 1 has nine sets of 2-input A corresponding to the number of arrangements of the emphasis buffer 31.
It consists of ND gates AND1 to AND9 and one OR gate OR.
The OR gate OR takes the OR logic of the outputs of 9 sets of 2-input AND gates AND1 to AND9, and each individual AND-OR
The output of the OR gate OR of the logic circuits 32a to 32n becomes the output of each individual AND-OR logic circuit 32a to 32n.

Each individual AND-OR logic circuit 32a-32
For n, the data of the corresponding bit in the horizontal enhancement control data of the horizontal enhancement control register 33 is input to the respective two-input AND gates AND1 to AND9, and among this data and each line buffer 31a to 31n of the enhancement buffer 31, This is a configuration in which the data at the corresponding array position in the corresponding line buffer is input and the two are ANDed.

Further, the individual AND-OR logic circuit 32n +
1, the data of the corresponding bit in the vertical enhancement control data of the vertical enhancement control register 34 is input to the respective 2-input AND gates AND1 to AND9, and this data and each individual AN are input.
Of the outputs of the D-OR logic circuits 32a to 32n, the output data of the corresponding individual AND-OR logic devices 32a to 32n are input and the AND of the two is performed. Then, the individual AND-OR logic circuit 32n + 1 constitutes 9
The result of ORing the outputs of the two-input AND gates AND1 to AND9 of the set is the output EMPEN of the AND-OR logic unit 32.
(Emphasis processing output).

Specifically, of the 9-bit data of the emphasis control register 33, the first bit data is AND-O.
Each individual AND-OR logic circuit 32a of the R logic device 32
9 sets of 2-input AND gates AND1 in each of 32n
~ AND9, the second bit data of the 9-bit data of the emphasis control register 33, which is input to one input terminal of the first 2-input AND gate AND1, is AND-.
Each individual AND-OR logic circuit 32a of the OR logic device 32
9 sets of 2-input AND gates AN for each up to 32n
Of the D1 to AND9, it is input to one input terminal of the second 2-input AND gate AND2, and is input to 9 of the emphasis control register 33.
Of the bit data, the third bit data is AND
Each individual AND-OR logic circuit 32 of the -OR logic device 32
9 sets of 2-input AND gates in a to 32n respectively
Of AND1 to AND9, the third 2-input AND gate AND3
One of the input terminals is input to one input terminal of the corresponding AND gate, and so on.

Of the 9 sets of 2-input AND gates AND1 to AND9 in each of the individual AND-OR logic circuits 32a to 32n of the AND-OR logic device 32, the other input of the first 2-input AND gate AND1 is input. The holding data of the first array element of the corresponding one line buffer in the line buffers 31a to 31n of the emphasis buffer 31 is input to the terminal, and the second array in each individual AND-OR logic circuit 32a to 32n is input. The emphasis buffer 3 is provided at the other input terminal of the 2-input AND gate AND2.
The data held in the second array element of the corresponding one line buffer in each of the one line buffers 31a to 31n is input, and the AND-OR logic device circuit 32a is input.
Data held by the third array element of the corresponding one line buffer of the line buffers 31a to 31n of the enhancement buffer 31 is input to the other input terminal of the third two-input AND gate AND3 of each of the line buffers 31 to 32n. , And so on, the data held by the array elements of the enhancement buffer 31 are input to the other input terminals of the corresponding AND gates.

The individual AND-OR logic circuit 32n
In +1, the data of the corresponding bit in the vertical enhancement control data of the vertical enhancement control register 34 is input to the respective 2-input AND gates AND1 to AND9, and this data and each individual A
Of the outputs of the ND-OR logic circuits 32a to 32n, the output data of the corresponding individual AND-OR logic circuits 32a to 32n, that is, the output data of the individual AND-OR logic circuit 32a, is output to the individual AND-OR logic circuit 32n + 1. First
An individual AND-OR logic circuit corresponding to the output data of the individual AND-OR logic circuit 32b to the second 2-input AND gate AND2 of the individual AND-OR logic circuit 32n + 1, and so on. 32a
The output data of .about.32n is input and the AND of both is taken. Then, the individual AND-OR logic circuit 32
Nine sets of two-input AND gates AND1 to AND9 forming n + 1
The result of ORing the outputs of the AND-OR logic unit 3
The second output is EMPEN (enhancement processing output).

The operation of the present apparatus having such a configuration will be described. In this apparatus, desired horizontal emphasis control data and vertical emphasis control data are set in the horizontal emphasis control register 33 and the vertical emphasis control register 34 in advance. Then, when a plurality of lines of the video display order of the display of the image data are input in parallel to the emphasis buffer 31, the emphasis buffer 31 sequentially shifts the image data in real time.

The emphasis buffer 31 is provided with a plurality of sets of line buffers having a serial arrangement for 9 pixels, and a plurality of lines in the display display order are input in parallel and sent to the line buffer corresponding to each line. As a result, each line buffer holds the data of the display line corresponding to the image, and these are shifted in real time. Then, the data at each array position of each line buffer at that time is ANDed.
-N sets of individual AND-OR logic circuits 32a to 32n of the -OR logic device 32 each having 9 sets of 2 inputs A
It will be input to the corresponding 2-input AND gate of the ND gates AND1 to AND9.

On the other hand, the horizontal enhancement control data of the enhancement control register 33 is stored in each of the 2-input AND gates AND1 to AND9 which are included in each of the n sets of individual AND-OR logic circuits 32a to 32n of the AND-OR logic device 32. Of these, the corresponding ones have been entered, so individual AND-O
In each of the R logic circuits 32a to 32n, the respective 2-input AND gates AND1 to AND9 of its own system take the AND logic of the pixel data destined for the own system given from the enhancement buffer 31 and the horizontal enhancement control data. When both are "1", the AND gate outputs "1". In each of the individual AND-OR logic circuits 32a to 32n, the output of each 2-input AND gate AND1 to AND9 of its own system passes through the OR gate OR of its own system, and the individual AND-OR logic circuit 32 is formed.
It is an input to n + 1.

In the individual AND-OR logic circuit 32n + 1, corresponding two of the outputs from the individual AND-OR logic circuits 32a to 32n are input to the two-input AND gates AND1 to AND9 of the own system, respectively, and vertical The corresponding one of the control data from the emphasis control register 34 is input. Then, the ANDs of these are taken, and the individual AN
Each 2-input AN of own system in D-OR logic circuit 32n + 1
The AND outputs of the D gates AND1 to AND9 are output through the OR gate OR of the individual AND-OR logic circuit 32n + 1 to output A
It is the output of the ND-OR logic unit 32.

Finally, the bit pattern of the horizontal emphasis control data set in the horizontal emphasis control register 33 is ANDed with the value of each image data in the emphasis buffer 31, and the result is set in the vertical emphasis control register 34. Since the value of the horizontal emphasis control data and the bit pattern of the horizontal emphasis control data are ANDed with that of the vertical emphasis control data, only the central bit of the horizontal emphasis control data and the vertical emphasis control data is set to "1". If the bit pattern is set to 0 and the other bits are set to “0”, the emphasis buffer 3
In 1, when "1" appears in the central array element of 9 pixels,
The output of the AND-OR logic device 32 is "1" and is "0" under other conditions.

Similarly, if the bit pattern is such that only both sides of the central bits of the horizontal enhancement control data and the vertical enhancement control data of 9-bit configuration are set to "1" and the other bits are set to "0", the enhancement buffer 31 When "1" appears in at least one of the array elements on both sides of the central array element of 9 pixels, the output from the AND-OR logic unit 32 becomes "1", and becomes "0" in other conditions.

Then, among the array elements of 9 pixels in the data for n lines of the enhancement buffer 31, "1" appears in the desired array element within the desired enhancement processing range and "1" appears in the central array element. Is not appearing,
In order to perform the enhancement process for the central array element of the enhancement buffer 31, the following process may be performed.

That is, the horizontal emphasis control data and the vertical emphasis control data are set to a bit pattern that defines the desired emphasis processing range, and the contents of the central array element in each line buffer of the emphasis buffer 31 are inverted by an inverter. , The output of these inverters for each system, the output EMPE of the AND-OR logic unit 32
For the line buffer of the system whose result is "1", the contents of the corresponding pixel of the central array element in the line buffer are emphasized by taking the AND logic with N.

When the video display control of the display is a television scan system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, the image input to the emphasis buffer 31 Pixel input control is performed so that the line input to the horizontal array element passing through the central position CP among a plurality of lines becomes the display line. Then, the emphasis buffer 31
If the pixel at the center position CP of the pixel is controlled so as to correspond to the display display corresponding pixel at that time, the pixel shifted to the center position CP of the enhancement buffer EB at that time is timing-wise. It becomes a pixel used for display display.

Therefore, when the above-described emphasized output is generated and the emphasizing process is performed at that timing,
The two-dimensional shadow (bag) emphasizing process described with reference to FIG. 5 can be performed in real time by hardware having a simple configuration.

In the case of the two-dimensional emphasis, when the pixel data of the line in the display order is input to the emphasis buffer, it is shifted in synchronization with the control timing of the video display, and the specified emphasis processing is performed by the AND-OR logic unit 32.

The size of the emphasis buffer 31 is AND-OR
It depends on the emphasis range that can be processed by the logic unit 32. If the emphasis range is 8 pixels (the width of the right, left, top, and bottom pixels is 4 pixels), the horizontal and vertical emphasis control registers 33,
The width of 34 is “enhancement range + 1”, and the emphasis buffer 31
Is a register having a size capable of handling 9 pixels, and the horizontal and vertical emphasis control registers 33 and 34 each have a 9-bit width. When the emphasis range is 8 pixels (8 bits), the number of sets of individual AND-OR logic circuits is equal to “emphasis range + 2”.

In addition, the circuit device shown in FIG.
It can simply be operated as an emphasis processing device in various emphasis modes according to the contents of data set in the horizontal and vertical emphasis control registers 33 and 34.

Then, when the output EMPEN of the AND-OR logic device 32 is "1", that is, when it is active, the control device for video display controls to emphasize the pixel to be displayed. , The pixels will be displayed with emphasis.

The data set in the horizontal and vertical emphasis control registers 33 and 34 for designating the desired emphasis mode may be manually applied to the horizontal and vertical emphasis control registers 33 and 34, respectively. However, it would be more convenient to be able to provide this automatically.

Therefore, as shown in FIG. 11, a mode selection key device 41 for selectively designating and inputting various modes and a parameter decoder 42 for outputting a corresponding parameter according to the input from the mode selection key device 41 are provided. The output of the parameter decoder 42 is supplied to the horizontal and vertical emphasis control registers 33 and 34.

In this device, a mode selection key device 41 having a key for setting an emphasis range and a type key as shown in Table 1 in which a key type and mode data output are associated with each other
When a mode selection key is selected and a highlight range and type are input, the mode selection key unit 41 outputs the mode data and the highlight range data corresponding to the selected and operated key.
Then, the parameter decoder 42 generates horizontal and vertical emphasis control data as shown in FIGS. FIG. 12 shows an example for the shadow (bag) enhancement mode, and FIG. 13 shows an example for the outline (shadow) enhancement mode. “Right”, “left”, “upper”, and “lower” of the emphasis parameter data in FIGS. 12 and 13 indicate emphasis ranges, which are “right” from the center position CP, respectively.
It indicates how many dot positions are in the range to "left", "upper", and "lower".

The mode selection keys include horizontal emphasis, vertical emphasis,
There are shadow (bag) enhancement, outline (shadow) enhancement, no enhancement processing, etc. Therefore, if one of these various enhancement modes is designated by a key selection operation, the parameter decoder 42 automatically uses the designated enhancement mode. The horizontal and vertical emphasis control data of is generated and set in the horizontal and vertical emphasis control registers 33 and 34, and the AND-OR logic unit 32 uses the horizontal emphasis, vertical emphasis, shadow (bag) emphasis, and outline ( It becomes possible to perform the enhancement processing corresponding to the designated mode among various enhancement modes of (shadow) enhancement and no enhancement processing.

[0156] Note that the mode data and the emphasis mode described above are merely examples. Therefore, it can be changed as necessary.

In this apparatus, in the two-dimensional emphasis mode, the horizontal emphasis control data output is used as the horizontal control register 3
3 and set the vertical emphasis control data to the vertical control register 34.

For the one-dimensional horizontal emphasis mode among the various emphasis modes, the contents of the horizontal control register 33 are controlled by the output horizontal emphasis control data to control the data string corresponding to the emphasis range according to the input emphasis parameter. It is set to data and the contents of the vertical emphasis register 34 are fixed as / 0/0/0/0/1/0/0/0/0 /.

For the one-dimensional vertical emphasizing mode, the contents of the vertical control register 34 are set to the control data of the data string corresponding to the emphasizing range according to the input emphasizing parameter by the output vertical emphasizing control data, and the horizontal emphasizing control data is set horizontally. The contents of the highlight register 33 are fixed as / 0/0/0/0/1/0/0/0/0 /.

In the non-emphasized mode, all bits of the horizontal emphasis control register 33 and the vertical emphasis control register 34 are set to zero. With the configuration using such control data, the two-dimensional enhancement processing device in FIG. 11 can be used for all enhancement processes.

Although not limited to the two-dimensional emphasizing processing device of FIG. 11, the emphasizing buffer described above has a buffer size of A.
It depends on the maximum emphasis range indicated by the ND-OR logic. For example, if the emphasis range is 8 pixels (the pixel width is 4 pixels when the left, right, top, and bottom pixels of the center pixel are the target of the emphasis range), the width of the emphasis control register is “enhancement”. Range + 1 "bits,
The width of the emphasis buffer is equal to "emphasis range + 1".

The above-described circuit device becomes a device capable of instructing horizontal and vertical emphasis simply by changing the contents of the emphasis control register and shifting the display line through the emphasis buffer.

In the above, the example is realized by the device configuration mainly composed of hard logic, but not limited to the hard logic, it can be realized also by the device of software control structure mainly composed of the microcomputer. Examples thereof are shown in FIGS.
Shown in

[Example 1 of Enhancement Processing Device Mainly Based on Microcomputer Technology] FIG. 14 is a first example of a enhancement processing device mainly for a microcomputer for one-dimensional horizontal enhancement processing or one-dimensional vertical enhancement processing. Is. Reference numeral 51 in the figure denotes an image processor, which has an emphasis processing means 51a. 52
Is a host processor, 53 is an external memory, and 54 is a video display controller. The host processor 52 is provided with emphasis control data, and the external memory 53 has a function of holding pixel data of an image to be displayed and transmitting the pixel data at a video display control timing of the display. Further, the video display control device 54 converts the pixel data of the image to be displayed, which is sent from the external memory 53, into a video signal and sends it at the timing of the display, and outputs the emphasizing processing result EM from the image processor 51.
When PEN is obtained, it has a function of generating and transmitting a video signal in which pixel data is emphasized accordingly.

The emphasis processing means 51a contains an emphasis buffer, an emphasis control register, and an AND-OR logic means,
The emphasis buffer corresponds to the emphasis buffer 11 in FIG. 8, the emphasis control register corresponds to the emphasis control register 13 in FIG.
The AND-OR logic means is the AND-OR logic device 1 of FIG.
2 corresponds to No. 2 and executes the same function as described in FIG. 8 to generate the output EMPEN of the emphasis processing result.

In this apparatus, the host processor 52 generates horizontal emphasis control data and supplies it to the image processor 51. Then, in the image processor 51, the emphasis processing means 51
This is set in the highlight control register in a. Then, when the data of the image to be displayed is serially input from the external memory 53 line by line to the emphasis buffer of the emphasis processing means 51a, the image data is sequentially shifted in real time in the emphasis buffer. The emphasis buffer is, for example,
It is a line buffer having a serial array of 9 pixels, and the data at each array position at that time is emphasized processing means 5
1a AND-OR logic means.

AND-OR logic means is AND-O of FIG.
The R logic unit 12 has the same function as that of the R logic unit 12 shown in FIG.
Similarly, for example, 9 sets of 2-input AND logic functions AND1 to AN
The data at each array position of the enhancement buffer having D9 is input to the corresponding 2-input AND logic function of the 9 sets of 2-input AND logic functions AND1 to AND9.

On the other hand, each two inputs A of AND-OR logic means
Among the horizontal emphasis control data of the emphasis control register, corresponding ones are given to the ND logic functions AND1 to AND9, respectively. Therefore, each two-input AND logic functions AND1 to AND9 are provided with the pixel data given from the emphasis buffer. The AND logic of the horizontal emphasis control data will be taken. When both are "1", the AND logic function outputs "1".
The output of each 2-input AND logic function AND1 to AND9 is AND-O.
It passes through the OR gate OR of the R logic means and becomes the output of the AND-OR logic means.

After all, since the bit pattern of the horizontal emphasis control data set in the emphasis control register and the value of each image data in the emphasis buffer are ANDed, the center of the horizontal emphasis control data of 9-bit structure is obtained. If only the bit of "1" is set to "1" and the other bits are set to "0", when "1" appears in the array element at the center of 9 pixels in the enhancement buffer, the output of the AND-OR logic means becomes "1". ", And" 0 "under other conditions. This AND-
The "1" output of the OR logic means becomes the EMPEN output of this AND-OR logic means.

Similarly, if a bit pattern in which only both sides of the central bit of the horizontal enhancement control data of 9-bit structure are set to "1" and the other bits are set to "0", the enhancement buffer has a central array element of 9 pixels. When "1" appears in at least one of the array elements on both sides, the output of the AND-OR logic means becomes "1", and becomes "0" under other conditions.

When "1" appears in a desired array element and "1" does not appear in the center array element of the emphasis buffer among the 9-pixel array elements of the emphasis buffer, the center of the emphasis buffer is highlighted. By providing the AND-OR logic means with the function of performing the enhancement process for the array elements, the one-dimensional horizontal enhancement process as described with reference to FIG. 2 can be performed in real time by the hardware having a simple configuration.

That is, the contents of the array element in the center of the emphasis buffer are inverted, and the AND logic of this inverted output and the output EMPEN of the AND-OR logic means is taken. When the result is "1", this " 1 "output enhancement processing means 5
It is passed to the video display controller 54 as the EMPEN output of 1a. The video display control device 54 converts the pixel data from the external memory 53 into a video signal corresponding to the data value and outputs the video signal. When the EMPEN output is received, the pixel data is emphasized and converted into a video signal and output. To do.

When the video display control of the display is a television scan system, the screen is displayed by displaying pixels while scanning one line at a time in the horizontal direction. In this case, a plurality of images input to the enhancement buffer are displayed. Pixel input control is performed so that the line input to the horizontal array element that passes through the central position among the lines corresponds to the video display line of the display. Then, if the pixel at the center position of the enhancement buffer is controlled to be the display display corresponding pixel at that time, the pixel shifted to the center position of the enhancement buffer at that time is timing-wise. Pixels used for video display on this display.

This pixel is supplied to the video display control device 54 so as to be converted into a video signal, and the emphasis output EM is obtained.
When the PEN is present, the video display control device 54 performs the emphasis process, so that the display device that receives the video signal from the video display control device 54 displays the existing pixels as a significant image, and performs the emphasis process. By displaying the pixels as emphasized pixels, it is possible to display the image subjected to the one-dimensional horizontal emphasis process.

The above is the description of the system for one-dimensional horizontal enhancement processing. Next, a system for one-dimensional vertical enhancement processing will be described. To realize the one-dimensional vertical enhancement processing, the following is done.

In this example, the function of the emphasis buffer of the emphasis processing means 51a is a buffer having an array for one line and one pixel and having a configuration of 9 lines × 1 pixel. The image data of 9 lines × 1 pixel is read from the external memory 53 at the display timing of the display. This makes it possible to easily perform one-dimensional vertical emphasis processing in real time.

The functional configuration follows that described with reference to FIG. Then, desired vertical emphasis control data is applied from the host processor 52 to the emphasis processing means 51a of the image processor 51.
The vertical emphasis control data is set in the emphasis control register of the emphasis processing means 51a. Then, when the image data is input to the emphasis buffer of the emphasis processing means 51a in parallel for 9 lines corresponding to the display order, the image data is sequentially shifted in real time in the emphasis buffer in synchronization with the video display control timing.

In the case of the above example, the emphasis buffer is a buffer having a parallel array of 9 pixels, and the data at each array position at that time is stored in 9 sets of two-input AND logic functions AND1 to AND-OR logic means. Corresponding 2-input A of AND9
Input to ND logic function.

On the other hand, each two inputs A of AND-OR logic means
To the ND logic functions AND1 to AND9, corresponding ones of the vertical emphasis control data of the emphasis control register are respectively input, and therefore, the 2-input AND logic functions AND1 to AND9 are provided with the pixel data given from the emphasis buffer, The AND logic of the vertical emphasis control data will be taken. When both are "1", the AND logic function outputs "1".
The output of each 2-input AND logic function AND1 to AND9 is OR logic OR
Output of the AND-OR logic means by passing
Become EN.

After all, the bit pattern of the vertical emphasis control data set in the emphasis control register by the host processor 52 and the AN of the value of each image data in the emphasis buffer.
Since it takes the form of D, only the central bit of the vertical emphasis control data of 9-bit structure is set to "1" and the other bits are set to "0".
In the enhancement buffer, if "1" appears in the central array element of 9 pixels, AND-O
The output of the R logic means becomes "1" and "0" under other conditions.
become.

Similarly, if a bit pattern in which only both sides of the central bit of the vertical emphasis control data of 9-bit structure are set to "1" and the other bits are set to "0", the emphasis buffer has 9 pixel array elements at the center. When "1" appears in at least one of the array elements on both sides, the output of the AND-OR logic means becomes "1", and becomes "0" under other conditions.

When "1" appears in a desired array element and "1" does not appear in the center array element of the emphasis buffer among the 9-pixel array elements of the emphasis buffer, the center of the emphasis buffer is highlighted. By providing the AND-OR logic means with the function of performing the enhancement process on the array elements, the one-dimensional vertical enhancement process as described with reference to FIG. 3 can be performed in real time by the hardware having a simple configuration.

That is, the contents of the array element at the center of the emphasis buffer are inverted and AND-ORed with this inverter output.
The AND logic with the output EMPEN of the logic means is taken, and when the result is "1", this "1" output is passed to the video display controller 54 as the EMPEN output of the emphasis processing means 51a. The video display controller 54 has an external memory 53.
When the EMPEN output is received, the pixel data is converted into a video signal and output.

When the display display control is a television scan system, the screen is displayed by displaying pixels while scanning each line in the horizontal direction. In this case,
The line input to the array element position (center position CP) at the center of the emphasis buffer becomes the display line. Then, if the timing control is performed so that the pixel at the center position CP of the enhancement buffer becomes the display display corresponding pixel at that time, the pixel shifted to the center position CP of the enhancement buffer at that time is timing-wise. Pixels to be used for display on.

Therefore, the output EMPEN is generated at the timing satisfying the above-mentioned emphasis condition, and the output EMPEN is given to the video display control device 54.
Then, the display pixel at that point is subjected to the emphasis process, the pixel data subjected to the emphasis process is converted into an image signal, and the other pixel data is converted into an image signal without the emphasis process. In the display device which has received the video signal, the existing pixels are displayed as significant images, and the pixels to be emphasized are displayed as emphasized pixels.

[Example of Emphasis Processing Device Supporting Various One-Dimensional and Two-Dimensional Emphasis Modes] An example of an emphasis processing device mainly supporting microcomputer technology and supporting various one-dimensional and two-dimensional emphasis modes will be described below. To do.

FIG. 15 shows an emphasizing processing apparatus which mainly supports microcomputer technology and supports various one-dimensional and two-dimensional emphasizing modes. In the figure, 61 is an image processor, and emphasizing processing means 61a and emphasizing mode. Decoder 6
1b and an emphasis parameter decoder 61c.

62 is a host processor, 63 is an external memory, and 64 is a video display controller. The host processor 62 is provided with the enhancement mode data and the enhancement control parameter, and the external memory 63 has a function of holding the pixel data of the image to be displayed and sending the pixel data at the display timing. The video display control device 64 converts the pixel data of the image to be displayed, which is sent from the external memory 63, into a video signal in response to the video display on the display and sends the video signal at the video display timing of the display. When the output EMPEN of the emphasis processing result is obtained, it has a function of generating and transmitting a video signal in which the pixel data is emphasized accordingly.

The emphasis processing means 61a includes an emphasis buffer, an emphasis control register, and an AND-OR logic means,
The emphasis buffer corresponds to the emphasis buffer 31 of FIGS. 10 and 11, and the emphasis control register is the emphasis control register 3 of FIG.
3, the AND-OR logic means corresponds to the AND-OR logic device 32 of FIGS. 10 and 11, and FIG.
The configuration is such that the same function as described with reference to FIG. 11 is executed to generate the output EMPEN of the emphasis processing result.

The enhancement mode decoder 61b receives the enhancement mode data shown in Table 1 from the host processor 62 and outputs information corresponding to the enhancement type. The enhancement parameter decoder 61c outputs the enhancement mode decoder 61b. Information and the emphasis control parameter given from the host processor 62, the emphasis range parameter data, the horizontal emphasis control data corresponding to the emphasis type, and the vertical emphasis control data are output, and the horizontal emphasis control register 33,
This is given to the vertical emphasis control register 34.

According to such a configuration, when the host processor 62 gives the data of the emphasis mode indicating the emphasis type and the emphasis control parameter, the emphasis mode decoder 61b.
Outputs information corresponding to the emphasis type, and the emphasis parameter decoder 61c uses the information from the emphasis mode decoder 61b and the emphasis control parameter including the information of the emphasis range provided from the host processor 62 to horizontally emphasize the emphasis type. The control data and the vertical emphasis control data are output and given to the horizontal emphasis control register and the vertical emphasis control register of the emphasis processing means 61a (see FIG. 12, FIG. 13, etc.).

As a result, desired horizontal enhancement control data and vertical enhancement control data are set in the horizontal enhancement control register and the vertical enhancement control register. Then, the pixel data of the image data is displayed in the display order and the pixel data of the line to be video-displayed at that time is stored in the external memory 63.
At the same time, the data is sent to the video display control device 64, and at the same time, a plurality of adjacent lines centering on the video display target line at that point in the display display order are stored in the external memory 6.
The data is read out from No. 3 and inputted into the emphasis buffer of the emphasis processing means 61a. Then, the enhancement buffer sequentially shifts the image data in real time.

The emphasis buffer of the emphasis processing means 61a has a constitution in which a plurality of line buffers having a serial arrangement of, for example, 9 pixels are provided, and a plurality of lines in the display order of the display are input in parallel to each line. As a result of being sent to the corresponding line buffers, the data of the corresponding display display lines of the image are held in each line buffer, and these are shifted in real time. Then, the data at each array position of each line buffer at that time is n of the AND-OR logic means.
9 sets of 2-input AND logic functions AND1 to AND9 each having a set of individual AND-OR logic functions 32a to 32n.
Will be input to the corresponding 2-input AND logic function.

On the other hand, each of the two-input AND logic functions AND1 to AND9 of the n sets of individual AND-OR logic functions 32a to 32n of the AND-OR logic means includes the horizontal emphasis control data of the emphasis control register. , The corresponding ones have been input, and therefore, the individual AND-OR logic functions 32a to 32n each have two inputs AN of their own system.
D logic functions AND1 to AND9 are the AN of the pixel data for the own system given from the enhancement buffer and the horizontal enhancement control data.
D logic will be taken. When both are "1", the AND logic function outputs "1". Individual AND-
In each of the OR logic functions 32a to 32n, the output of each 2-input AND logic function AND1 to AND9 of its own system is the OR of its own system.
Individual AND-OR logic function 32n through logic function OR
It becomes an input to +1.

In the individual AND-OR logic function 32n + 1, corresponding two of the outputs from the individual AND-OR logic functions 32a to 32n are input to the respective 2-input AND logic functions AND1 to AND9 of the own system, The corresponding one of the control data from the vertical emphasis control register is input. And those ANDs are taken and individual AND
-OR logic function 32n + 1 each 2-input AND of own system
The AND outputs of the logic functions AND1 to AND9 are output through the OR logic function OR of the individual AND-OR logic function 32n + 1 and become the output of the AND-OR logic means.

After all, the bit pattern of the horizontal emphasis control data set in the horizontal emphasis control register is ANDed with the value of each image data in the emphasis buffer, and the result is combined with the horizontal emphasis control register set in the vertical emphasis control register. Since the value of the control data and the bit pattern of the horizontal emphasis control data are ANDed with the value of the bit pattern of the control data, only the central bit of the horizontal emphasis control data and the vertical emphasis control data is set to "1", and the other. Is a bit pattern with "0", the output of the AND-OR logic means becomes "1" when "1" appears in the central array element of 9 pixels in the emphasis buffer, and "0" under other conditions. become.

Similarly, if a bit pattern in which only both sides of the central bit of each of the horizontal enhancement control data and the vertical enhancement control data of 9 bits are set to "1" and the other bits are set to "0", the enhancement buffer has 9 bits. When "1" appears in at least one of the array elements on both sides of the array element in the center of the pixel, the output from the AND-OR logic means becomes "1", and becomes "0" in other conditions.

Then, among the array elements of 9 pixels in the data of n lines in the enhancement buffer, "1" appears in the desired array element within the desired enhancement processing range and "1" appears in the central array element. In order to perform the emphasis process for the array element at the center of the emphasis buffer when it does not appear, the following process may be performed.

That is, with respect to the horizontal emphasis control data and the vertical emphasis control data, a bit pattern that defines the desired emphasis processing range is set, the contents of the central array element in each line buffer of the emphasis buffer are inverted, and Inverted output is AND-OR for each system
For the line buffer of the system whose result is "1", the contents of the corresponding pixel of the central array element in the line buffer are emphasized by taking the AND logic with the output EMPEN of the logic means. As a result, the two-dimensional shadow (bag) emphasizing process described with reference to FIG. 5 can be performed in real time by hardware having a simple configuration.

In the case of two-dimensional emphasis, when the pixel data of the lines in the display order (video display order) on the display are input to the emphasis buffer for a plurality of adjacent lines, the video display control timing is set in the emphasis buffer. And the specified emphasis processing is AND-O
Done by R logic means.

The size of the enhancement buffer depends on the enhancement range that can be processed by the AND-OR logic means. If the emphasis range is 8 pixels (the width of the right, left, top, and bottom pixels is 4 pixels), the width of the horizontal and vertical emphasis control registers is “the emphasis range + 1”, and the emphasis buffer 31 has 9 pixels. The horizontal and vertical emphasis control registers are 9-bit wide, and are of a size capable of handling minutes. When the emphasis range is 8 pixels (8 bits), the number of sets of individual AND-OR logic functions is "emphasis range +2".

Here, like the circuit device shown in FIG.
This apparatus can simply operate as an emphasis processing apparatus in various emphasis modes according to the contents of data set in the horizontal and vertical emphasis control registers.

The output EM of the AND-OR logic means
When PEN is "1", that is, when the video display controller 64 controls the pixel to be displayed to be emphasized, the pixel is emphasized and displayed.

The types of the emphasis modes are horizontal emphasis, vertical emphasis,
There are shadow (bag) enhancement, outline (shadow) enhancement, no enhancement processing, etc. Therefore, when one of these various enhancement modes is designated by the host processor 62 and the enhancement range is designated, the enhancement mode decoder 61b and the enhancement parameters are set. The horizontal and vertical emphasis control data for the specified emphasis mode is generated through the decoder 61c and set in the horizontal and vertical emphasis control registers, and the AND-OR logic means thereby performs the horizontal emphasis, vertical emphasis and shadow. It becomes possible to carry out the emphasizing processing corresponding to the designated mode among various emphasizing modes of (bag) emphasizing, outline (shadow) emphasizing, and no emphasizing processing.

The apparatus shown in FIG. 16 causes the external memory 63a to hold image data, emphasis mode and parameter data, and instead of giving the emphasis mode and parameter data from the host processor, the image data is emphasized in the emphasis mode and parameter data. The above data is given to the image processor 61.

In this case, the data is prepared by attaching the emphasis mode and the parameter data to the image data,
To store in the external memory 63a, read out a plurality of lines in the display order of the display in the same manner as described above, and give it to the AND-OR logic means, and also give the emphasis mode and parameter data to the emphasis mode decoder 61b and the emphasis parameter decoder 61c. Then, it becomes possible to carry out the emphasis processing similar to the above.

As a result, for example, when displaying character information, if the basic font information of the character to be displayed and the emphasis mode and parameter data are transmitted, the basic font is emphasized with a desired emphasis type. The processed image can be displayed on the display, and when transmitting character information, it is possible to obtain an effect that characters processed into various patterns can be displayed with a small amount of information.

Note that modes and parameters and examples of emphasis processing are shown in FIGS. FIG. 17A shows an example of cage enhancement processing, in which the parameters are right “00” and left “0”.
This is an example in which 0 ", upper" 10 ", and lower" 00 "are set. A black circle is an existing pixel and a white circle is an emphasized pixel. In this example, when an existing pixel appears in the emphasis range, The position of "10" above the existing pixel, that is, "10" is a binary number, but this corresponds to the decimal number "2". Therefore, if there is a non-existing pixel at the position of the second upper dot, this Is emphasized.

FIG. 17B also shows an example of cage emphasis processing, in which the parameters are right “00”, left “10”, and upper “0”.
This is an example in which 0 "and lower" 00 "are set. In this case,
When an existing pixel appears in the emphasis range, the position "10" to the left of the existing pixel, that is, "10" is a binary number, but this corresponds to the decimal number "2". As a result, if there is a non-existing pixel at the position of the second left dot, this is emphasized.

FIG. 17C is also an example of cage emphasis processing, in which the parameters are right “00”, left “10”, and upper “1”.
This is an example in which 0 "and lower" 00 "are set. In this case,
When an existing pixel appears in the emphasis range, the position is "10" to the left of and above the existing pixel, that is, "10".
Is a binary number, but this corresponds to the decimal number “2”, so if there is a non-existing pixel at the position of the upper second dot that is two dots to the left of the existing pixel, emphasize this. Shows.

FIG. 18A shows an example of bag emphasis processing.
In this example, the parameters are set to right "01", left "01", upper "01", and lower "01". In the case of this example, when an existing pixel appears in the emphasis range, “0” to the right of the existing pixel.
The positions of "1", left "01", upper "01", and lower "01", that is, "01" is a binary number, but this corresponds to the decimal number "1". Up, down,
This indicates that the non-existing pixels at the positions of the first dots on the left and right sides are emphasized.

FIG. 18B also shows an example of bag emphasis processing.
In this example, the parameters are set to right "10", left "10", upper "10", and lower "10". In the case of this example, when an existing pixel appears in the emphasized range, “1” to the right of the existing pixel is displayed.
Positions from 0 ", left" 10 ", upper" 10 ", and lower" 10 ", that is," 10 "is a binary number, but this corresponds to the decimal number" 2 ", so it is seen from the existing pixels. Up, down,
It indicates that the non-existing pixels at the positions up to the second dot on the left and right sides are emphasized.

FIG. 18C also shows an example of bag emphasis processing.
In this example, the parameters are set to right “01”, left “01”, upper “10”, and lower “01”. In the case of this example, when an existing pixel appears in the emphasis range, “0” to the right of the existing pixel.
Positions up to 1 ", left" 01 ", upper" 10 ", and lower" 01 ", that is," 01 "and" 10 "are binary numbers, but these are decimal numbers" 1 "and" 2 ". Because it corresponds to
This indicates that the non-existing pixels at the positions up to the first dot and the positions up to the second lower dot in the upper, left, and right of the existing pixels are emphasized.

Although various examples have been described above, in short, the present invention sends pixel data to the enhancement buffer, sequentially shifts the pixel data in the enhancement buffer, and causes pixels existing in the specified range in the enhancement buffer to exist. When it appears, the non-existing pixel at the designated position in the enhancement buffer is subjected to the enhancement process. Therefore, it becomes possible to carry out the desired emphasis processing in real time by a simple method, and for example, in the display of character information, it becomes possible to perform the desired emphasis processing with a small amount of information. A pixel data enhancement processing device and a pixel data enhancement processing method that are extremely effective for media and the like can be provided. It should be noted that the present invention is not limited to the above-described embodiments, but can be implemented by being modified in various ways.

[0215]

As described in detail above, according to the present invention,
It is possible to provide a pixel data enhancement processing device and a pixel data enhancement processing method that do not require a memory for storing intermediate results and can perform desired enhancement processing on pixel data in real time.

[Brief description of drawings]

FIG. 1 is a diagram for explaining various enhancements of pixel data.

FIG. 2 is a diagram for explaining the present invention, which is a diagram for explaining an aspect of an embodiment of the present invention for performing one-dimensional horizontal enhancement.

FIG. 3 is a diagram for explaining the present invention, which is a diagram for explaining an aspect of an embodiment of the present invention for performing one-dimensional vertical enhancement.

FIG. 4 is a diagram for explaining the present invention, which is a diagram for explaining an exemplary embodiment of the present invention for performing two-dimensional horizontal and vertical emphasis.

FIG. 5 is a diagram for explaining the present invention, which is a diagram for explaining an embodiment mode as an example of the present invention for performing two-dimensional shadow (bag) emphasis.

FIG. 6 is a diagram for explaining the present invention, which is a diagram for explaining an embodiment mode as an example of the present invention for performing two-dimensional outline (cage) emphasis.

FIG. 7 is a diagram for explaining the present invention, which is a diagram for explaining an embodiment of an example of the present invention for performing two-dimensional shadow (bag) emphasis.

FIG. 8 is a diagram for explaining the present invention and is a block diagram of a device configuration for explaining an embodiment of the present invention as an example for performing one-dimensional horizontal enhancement.

FIG. 9 is a block diagram for explaining the present invention, which is an apparatus configuration diagram for explaining an embodiment of the present invention as an example for performing one-dimensional vertical enhancement.

FIG. 10 is a diagram for explaining the present invention and is a block diagram of a device configuration for explaining an embodiment of the present invention as an example for performing various one-dimensional and two-dimensional enhancement processing.

FIG. 11 is a diagram for explaining the present invention, and is a device configuration block diagram for explaining an embodiment of the present invention as an example for performing various types of emphasis processing.

FIG. 12 is a diagram for explaining the present invention, showing an example of enhancement parameter data and horizontal and vertical enhancement control data for a shadow (bag) enhancement mode.

FIG. 13 is a diagram for explaining the present invention, showing an example of enhancement parameter data for the outline (shadow) enhancement mode and horizontal and vertical enhancement control data.

FIG. 14 is a diagram for explaining the present invention, and is a block diagram of a device configuration for explaining another embodiment of the present invention for performing various one-dimensional and two-dimensional enhancement processing.

FIG. 15 is a diagram for explaining the present invention, which is a block diagram of a device configuration for explaining another embodiment of the present invention for performing various one-dimensional and two-dimensional enhancement processing.

FIG. 16 is a diagram for explaining the present invention, and is a block diagram of a device configuration for explaining another embodiment of the present invention for performing various one-dimensional and two-dimensional enhancement processing.

FIG. 17 is a diagram for explaining the present invention, which is a diagram for explaining an example of a parameter in a shadow mode and a result of enhancement processing.

FIG. 18 is a diagram for explaining the present invention, which is a diagram for explaining an example of a parameter and a result of the emphasis process in the bag mode.

[Explanation of symbols]

11 ... Enhancement buffer 12, 32 ... AND-OR logic device 13, 23 ... Enhancement control register 20 ... One-dimensional real-time image data enhancement processing device 21, 31 ... Enhancement buffer 22, 32 ... AND-OR logic device 32a, ... 32n, 32n + 1 ... Individual AND-OR logic circuit 33 ... Horizontal enhancement control register 34 ... Vertical enhancement control register 42 ... Parameter decoder 51 ... Image processor 51a ... Enhancement processing means 52 ... Host processor 53 ... External memory 54 ... Video display control device AND1 to AND9 ... 2-input AND gate (2-input AN
D logic function) OR ... OR gate CP ... Center position

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/30 650 G06F 15/68 405 H04N 1/40 H04N 1/40 Z

Claims (9)

[Claims] 1. An emphasis buffer which sends pixel data to an emphasis buffer, sequentially shifts the pixel data in the emphasis buffer, and when a significant pixel existing pixel appears within a specified range in the emphasis buffer. A pixel data enhancement processing method, wherein enhancement processing is performed on a non-existing pixel that is an involuntary pixel located at a specified position in the pixel data enhancement processing. 2. The emphasis data is sent to the emphasis buffer, the pixel data is sequentially shifted in the emphasis buffer, and when an existing pixel that is a significant pixel appears within a specified range in the emphasis buffer, the emphasis buffer A pixel data enhancement processing method, wherein enhancement processing is performed on a non-existing pixel that is an involuntary pixel located at a central position in the pixel data. 3. The pixel data is sent to the enhancement buffer on a pixel-by-pixel basis in correspondence with the display on the display, the pixel data is sequentially shifted in the enhancement buffer, and significant pixels are present in a specified range in the enhancement buffer. A pixel data enhancement processing method characterized in that when a pixel appears, a horizontal enhancement process is performed to enhance a non-existing pixel which is an involuntary pixel at a central position in the enhancement buffer. 4. An enhancement buffer having an array for a plurality of lines is used, pixel data of each line for a plurality of lines is sent to the enhancement buffer in pixel units, and the pixel data is sequentially stored in the enhancement buffer. A vertical enhancement process that shifts and enhances a non-existent pixel, which is a nonsense pixel in the center position in the enhancement buffer, when a significant pixel, an existing pixel, appears within a specified range in the enhancement buffer. A pixel data enhancement processing method characterized in that 5. An enhancement buffer having an array of a plurality of lines is used, pixel data of each line of a plurality of lines is sent to the enhancement buffer in units of pixels corresponding to the display on the display, and the pixel data is stored in the enhancement buffer. While shifting sequentially with, within the specified range in the emphasis buffer,
When an existing pixel that is a significant pixel appears, emphasis processing is performed on pixel data at a predetermined activation position with respect to the pixel position when the pixel data is a non-existing pixel. Pixel data enhancement processing method. 6. An emphasis buffer that sequentially shifts input pixel data, and when an existing pixel that is a significant pixel appears within a specified range in this emphasis buffer, it is insignificant at a specified position in this emphasis buffer. If there is a non-existing pixel which is the pixel of the above, a processing means for enhancing the non-existing pixel is provided, and the pixel data enhancement processing apparatus. 7. An emphasis buffer that sequentially shifts input pixel data, and when an existing pixel that is a significant pixel appears within a specified range in the emphasis buffer, an insignificant pixel is placed at a central position in the emphasis buffer. If there is a non-existing pixel, the pixel data emphasis processing apparatus is provided with a processing means for emphasizing the non-existing pixel. 8. An emphasis buffer having an array of a plurality of lines and sequentially shifting the input pixel data, and when an existing pixel which is a significant pixel appears within a specified range in the emphasis buffer, this emphasis buffer is used. A pixel data enhancement processing apparatus comprising: a processing unit for enhancing a non-existent pixel that is an involuntary pixel at a central position in the buffer. 9. An emphasis buffer having an array of a plurality of lines and sequentially shifting input pixel data, and when an existing pixel which is a significant pixel appears within a specified range in the emphasis buffer, the pixel A pixel data enhancement processing apparatus, comprising: a processing unit that performs enhancement processing on pixel data at a predetermined activation position with respect to a position when the pixel data is a non-existing pixel.