JPH0936663A - Frequency conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the waveform roughness of the output signal that undergone the frequency conversion finely by providing an addition circuit which synthesizes the output signals of plural switch circuits and outputs these signals and then outputting a signal that has the sum or difference frequency component between the 1st and 2nd input signals received from the addition circuit. SOLUTION: A frequency conversion circuit consists of the 1st and 2nd input signal input terminals 1 and 7, the switch circuits 2, 4 and 6, the -2π/3 phase shift circuits 3 and 8, the -4π/3 phase shift circuits 5 and 9, an addition circuit 10 and an output terminal 11. In such a constitution, a signal that has the sum or difference frequency component between the 1st and 2nd input signals received from the circuit 10 is outputted. Thus a phase division number having the reduced roughness of the output signal waveform is obtained owing to use of those switch circuits. Therefore, the circuit constitution is simplified and the waveform roughness of the output signal that undergone the frequency conversion can be extremely improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit, and more particularly to a frequency conversion circuit to which a phase shift type single sideband signal generation method is applied.

[0002]

2. Description of the Related Art Conventionally, as a general means for obtaining a frequency conversion circuit or a single sideband signal (hereinafter abbreviated as SSB signal), for example, a multiplier, a balanced modulator, or a double balanced mixer (hereinafter , Abbreviated as DBM) to obtain a double sideband signal in which the carrier is suppressed, and then one of the sideband signals is selectively separated by a filter to obtain the SSB.
In principle, a signal may be generated, or a carrier wave and a signal may be phase-shifted by 90 degrees to two DBMs, and the output signals from the two DBMs may be added or subtracted in principle. A phase shift type SSB signal generation method in which the use of a filter is omitted is known (for example,
B. P. Rashii, "Detailed explanation of digital / analog communication method (first volume)", pages 226 to 251, CBS Publishing Co., Ltd., published March 28, 1985).

In the above-mentioned conventional frequency conversion circuit, when frequency conversion is performed using the first signal frequency f1 and the second signal frequency f2, when the frequencies are relatively high and the filter is easily applied, The sum frequency (f1 + f2) or the difference frequency (f1-f2) can be easily obtained by the multiplier and the filter. However, if either one of the frequencies is high and the other frequency is low, selective separation becomes difficult even if a filter is used.

Therefore, the phase shift type SSB is used.
It is a signal generation circuit. This circuit does not require a filter in principle (however, if one signal is a switching signal, or if a DBM or the like to be used performs a switching operation, a simple filter is used), and in terms of the operation of the DBM or the like. If the balance is good, the target sum frequency (f1 + f2) or difference frequency (f1-f2) can be selected, and the adjacent frequency f1 (or f2) is suppressed, and the above problem does not occur.

The DBM is a variable gm type D constructed by differentially connecting a diode bridge type and a plurality of transistors.
BM circuits are known. For example, the variable gm-type DBM circuit has an X-axis input terminal and a Y-axis input terminal, and the input circuit connected to each input terminal uses a double balanced differential circuit, and the X-axis and Y-axis input terminal portions are used. It is used here with a variable resistor for balancing.

FIG. 11 shows a circuit diagram of an example of a conventional frequency conversion circuit using the variable gm type DBM circuit described above. This frequency conversion circuit includes input terminals 81 and 85 and a DBM8.
2,-? / 2 phase shift circuit 83, DBM 84,-? / 2 phase shift circuit 86, and an adder circuit 87 for adding both output signals of the DBMs 82 and 84, and an output terminal 88. Each of the DBMs 82 and 84 switches the first input signal with the second input signal. DBM applied to general high frequency band
Is based on the switching operation.

FIG. 12 shows an S in which the DBM is replaced with a switch.
The circuit diagram of the other example of the conventional SB type frequency conversion circuit is shown. This conventional frequency conversion circuit has input terminals 91 and 9
9, switch circuits 92, 94, 96 and 98, inverting amplifiers 93, 97, -π / 2 phase shift circuits 95, 101, inverters 100 and 102, switch circuits 92, 94, 96.
And 98, and an output terminal 104. These FIG. 11 and FIG.
The basic operation of the conventional frequency conversion circuit 2 is the same. Therefore, the operation of the conventional frequency conversion circuit will be described with reference to the waveform chart of FIG. 13 by taking FIG. 11 as an example.

In FIG. 11, the first input signal e ₅₁ (t) from the input terminal 81 is applied to the DBM 42 and the −π / 2 phase shift circuit 4.
3 respectively. This first input signal e
₅₁ (t) is the waveform shown in FIG. 13 (A), which is A ₁ sinω
_It shall be represented by ₁ t. The −π / 2 phase shift circuit 83 shifts the phase of the first input signal e ₅₁ (t) by −π / 2 (rad.), And A ₁ sin (ω ₁ t has the waveform shown in FIG. 13B.
Generate a signal e ₅₂ (t) represented by −π / 2), and
Supply to 84.

On the other hand, the second input signal e ₅₃ (t) having the waveform shown in FIG. 13C is supplied from the input terminal 85 to the DBM 82 and the -π / 2 phase shift circuit 86 as a square wave for switching. . This second input signal e ₅₃ (t) is expressed by the following equation.

[0010] _{e 53 (t) = (4} / π) A 2 {sinω 2 t + (1/3) sin3ω 2 t + (1/5) sin5ω 2 t + (1/7) sin7ω 2 t + ...} ( 1) Further, the output signal e ₅₄ (t) of the −π / 2 phase shift circuit 86 is expressed by the following equation, and the second input signal e ₅₃ (t) is changed to −π / as shown in FIG. The waveform is a phase shifted by 2 (rad.).

E ₅₄ (t) = (4 / π) A ₂ (sin (ω ₂ t- (π / 2)) + (1/3) sin 3 (ω ₂ t- (π / 2)) + (1 / 5) sin5 (ω ₂ t- (π / 2)) + (1/7) sin7 (ω ₂ t- (π / 2)) + ...} (2) The DBM 82 outputs the first input signal e _51. By switching (t) with the second input signal e ₅₃ (t), a signal e ₅₅ (t) shown in FIG. 13E of the following equation is output.

E ₅₅ (t) =-(2 / π) A ₁ A ₂ [{cos (ω ₁ + ω ₂ ) t-cos (ω ₁ -ω ₂ ) t} + (1/3) {cos ( ω ₁ + 3ω ₂ ) t-cos (ω ₁ -3ω ₂ ) t} + (1/5) {cos (ω ₁ + 5ω ₂ ) t-cos (ω ₁ -5ω ₂ ) t} + (1/7 ) {cos (ω ₁ + 7ω ₂ ) t-cos (ω ₁ -7ω ₂ ) t} + ...] (3) Another DBM 84 inputs the first input signal e ₅₂ (t) to the second input. By switching with the signal e ₅₄ (t), the signal e ₅₆ (t) represented by the following equation shown in FIG.
Is output.

E ₅₆ (t) =-(2 / π) A ₁ A ₂ [{cos (ω ₁ t + ω ₂ t- π) -cos (ω ₁ -ω ₂ ) t} + (1/3) {cos (ω ₁ t + 3ω ₂ t-2π) -cos (ω ₁ t-3ω ₂ t + π)} + (1/5) {cos (ω ₁ t + 5ω ₂ t-3π) -cos (ω ₁ t-5ω ₂ t + 2π)} + (1/7) {cos (ω ₁ + 7ω ₂ t-4π) -cos (ω ₁ t-7ω ₂ t + 3π} + ...] (4) Addition The circuit 87 outputs the output signals e of the DBMs 82 and 84.
₅₅ (t) and e ₅₆ (t) are added to generate a signal e ₅₇ (t) represented by the following equation of the waveform shown in FIG. 13 (G), which is output to the output terminal 88.

E ₅₇ (t) = (4 / π) A ₁ A ₂ {cos (ω ₁ -ω ₂ ) t- (1/3) cos (ω ₁ + 3ω ₂ ) t + (1/5) { cos (ω ₁ -5ω ₂ ) t- (1/7) {cos (ω ₁ + 7ω ₂ ) t + ...} (5) Frequency-converted output signal e shown in equation (5)
₅₇ (t) is (ω ₁ − under the condition of ω ₁ << ω ₂
Based on the angular frequency of the difference of ω ₂ ), the triple component of (ω ₁ + 3ω ₂ ), the 5 × component of (ω ₁ −5ω ₂ ), (ω ₁ + 7ω
_It has an odd-order harmonic component such as a 7-fold component of ₂ ).
FIG. 14 shows the frequency spectrum of the output signal of this frequency conversion circuit.

As can be seen from the waveforms of the respective signals shown in FIG. 13, in the above-mentioned conventional frequency conversion circuit, the second input signal has four cycles during one cycle of the first input signal. On the other hand, the fundamental wave of the output signal is 3 (=
It is 4-1) cycle, and it can be confirmed that frequency conversion is performed.

[0016]

However, in the conventional frequency conversion circuit using the DBM shown in FIG. 11, the balance of the DBM is likely to collapse in an actual circuit, and it is difficult to obtain the best balance. Further, since a variable resistor is used in the variable gm type DBM circuit, there is a problem in terms of downsizing the circuit scale and productivity. Further, in the conventional frequency conversion circuit, it is difficult to completely correct the variation in the characteristics of the internal transistor even if the variable resistor is finely adjusted to achieve a balance, and as a result, the specifications of the variable gm type DBM are satisfied. The actual situation is to use a switch circuit that does not require a fixed balance adjustment. Further, in the conventional frequency conversion circuit shown in FIG. 11, since the roughness of the output signal waveform is related to the spectrum component of the harmonic, there is no problem if a filter for removing the harmonic is used, but the filter has a removal characteristic. As you need a fairly sharp and complexly structured filter.

On the other hand, in the conventional SSB type frequency conversion circuit constructed by using the switch circuit as shown in FIG. 12, the problem of DBM balance adjustment can be avoided,
There is a drawback that the circuit scale becomes slightly larger.

The present invention has been made in view of the above points,
An object of the present invention is to provide a frequency conversion circuit having a simple circuit configuration and capable of closely improving the roughness of the waveform of the frequency-converted output signal.

[0019]

In order to achieve the above object, the invention according to claim 1 is a phase dividing means for phase-dividing a first input signal into a plurality of channel signals having mutually different phases; Switching signal generation means for generating switching signals having the same number as the channel signals and different phases based on the input signal of the input signal, and a plurality of input channel signals provided in a one-to-one correspondence with the plurality of channel signals. Has a plurality of switch circuits for selectively outputting according to the switching signal from the switching signal generating means, and an adder circuit for synthesizing and outputting the output signals of the plurality of switch circuits respectively, and the frequency of the first input signal from the adding circuit. And a signal having a frequency component of the sum or difference of the frequency of the second input signal.

In order to achieve the above object, the invention according to claim 3 is a first phase dividing means for phase-dividing the first input signal into a plurality of first channel signals having mutually different phases. First switching signal generating means for generating switching signals having the same number as the first channel signals and different phases from each other based on the second input signal, and one-to-one correspondence with the plurality of first channel signals. A plurality of first switch circuits for selectively outputting the input first channel signals according to the switching signal from the first switching signal generating means and the output signals of the plurality of first switching circuits. Second phase dividing means for outputting a plurality of second channel signals having mutually different phases after combining them, and the same number as the second channel signals based on the second input signal and having different phases. Second switching signal generating means for generating a switching signal and a plurality of second channel signals, which are provided in a one-to-one correspondence with the plurality of second channel signals, are provided from the second switching signal generating means. A plurality of second switch circuits that selectively output according to the switching signal of 1., the output signals of the second switch circuits are combined, and the sum of the frequency of the first input signal and the frequency of the second input signal or The configuration is such that a signal having a difference frequency component is output.

According to the first aspect of the present invention, since the switch circuit is used instead of the double balanced modulator (DBM), it is possible to avoid the problem of characteristic deterioration due to the unbalance of the DBM. Further, according to the present invention, the first and second input signals have a plurality of phase ranges of 2π (rad.) At equal phase intervals, and a plurality of integers represented by 2 ⁿ (where n is a natural number) are excluded. By dividing the phase into an arbitrary number of them, switching each signal by the switch circuit, and then adding and synthesizing, the phase division of the circuit with the same output signal waveform roughness compared to the conventional circuit using the switch circuit is smaller. It can be realized with a number of configurations.

According to the third aspect of the invention, the input second
Of the first input signal and the frequency of the second input signal by synthesizing the output signals of the plurality of second switch circuits which selectively output the channel signal of 1 by the switching signal from the second switching signal generating means. Since the signal having the sum or difference frequency component is output, the addition circuit for obtaining the output signal in the final stage can be eliminated in addition to the effect of the invention according to the first aspect.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of FIG. The embodiment shown in FIG. 1 has input terminals 1 and 7, switch circuits 2, 4 and 6, -2π / 3 phase shift circuits 3 and 8, -4π / 3 phase shift circuits 5 and 9, and addition. It is composed of a circuit 10 and an output terminal 11.

Next, the operation of the circuit configuration diagram of FIG. 1 will be described. The first input signal e ₁ (t) is supplied from the input terminal 1 to the switch circuit 2, the −2π / 3 phase shift circuit 3, and the −4π / 3 phase shift circuit 5, respectively. This first input signal e
₁ (t) is the waveform shown in FIG. 2 (A), and A ₁ sinω ₁
shall be represented by t. The −2π / 3 phase shift circuit 3 shifts the phase of the first input signal e ₁ (t) by −2/3 (rad.), And A ₁ sin (ω ₁ t has the waveform shown in FIG. 2B. −
2π / 3), that is, a signal e ₂ (t) represented by −A ₁ cos (ω ₁ t−π / 6) is generated and supplied to the switch circuit 4.

The -4π / 3 phase shift circuit 5 shifts the phase of the first input signal e ₁ (t) by -4π / 3 (rad.), As shown in FIG.
In the waveform shown in (C), A ₁ sin (ω ₁ t-4π /
3), that is, a signal e ₃ (t) represented by −A ₁ sin (ω ₁ t−π / 3) is generated and supplied to the switch circuit 6. That is, the input signal e ₁ (t) is 2π (rad.).
Of the signal e by dividing the phase range of
₁ (t), e ₂ (t), and e ₃ (t).

On the other hand, the second input signal e ₄ (t) having the waveform shown in FIG. 2D is directly supplied from the input terminal 7 to the switch circuit 2 as a square wave for switching, while -2
It is supplied to the π / 3 phase shift circuit 8 and the -4π / 3 phase shift circuit 9, respectively, and is -2π / 3 (rad.) and -4π / 3 (ra).
d. ) Each phase is shifted. That is, the second input signal e ₄ (t) is also divided into three signals in the phase range of 2π (rad.) At equal phase intervals, and the signals e ₄ (t), e ₅ (t) and e
₆ (t).

This second input signal e ₄ (t) is expressed by the following equation.

[0028] _{e 4 (t) = (A} 2/2) + (2A 2 / π) {sinω 2 t + (1/3) sin3ω 2 t + (1/5) sin5ω 2 t + (1/7) sin7ω 2 t + ...} (6) Further, the output signal e ₅ (t) of the -2π / 3 phase shift circuit 8 is represented by the following equation, and the second input signal e ₅ is given as shown in FIG.
₄ (t) is a waveform obtained by shifting the phase of -2/3 (rad.).

[0029] _{e 5 (t) = (A} 2/2) - (2A 2 / π) {cos (ω 2 t-π / 6) - (1/3) cos3 (ω 2 t- π / 6) + (1/5) cos5 (ω ₂ t-π / 6)-(1/7) cos7 (ω ₂ t-π / 6) + ...} (7) Furthermore, in the -4π / 3 phase shift circuit 9, The output signal e ₆ (t) is expressed by the following equation, and as shown in FIG.
₄ (t) is a waveform obtained by phase shifting by -4π / 3 (rad.).

[0030] _{e 6 (t) = (A} 2/2) - (2A 2 / π) {sin (ω 2 t- π / 3) + (1/3) sin3 (ω 2 t-π / 3) + (1/5) sin5 (ω ₂ t-π / 3) + (1/7) sin7 (ω ₂ t-π / 3) + ...} (8) The switch circuit 2 in FIG. Switching the input signal e ₁ (t) with the second input signal e ₄ (t),
A signal e ₇ (t) represented by the following equation of the waveform shown in (G) is generated and output to the adder circuit 10.

[0031] _{e 7 (t) = (A} 1 A 2/2) sinω 1 t- (A 1 A 2 / π) [{cos (ω 1 + ω 2) t-cos (ω 1 -ω 2) t } + (1/3) {cos (ω ₁ + 3ω ₂ ) t-cos (ω ₁ -3ω ₂ ) t} + (1/5) {cos (ω ₁ + 5ω ₂ ) t-cos (ω _1- 5ω ₂ ) t} + (1/7) {cos (ω ₁ + 7ω ₂ ) t-cos (ω ₁ -7ω ₂ ) t} + ...] (9) On the other hand, the switch circuits 4 and 6 in FIG. Respectively generate the first signals e ₂ (t) and e ₃ (t) and the second signals e ₅ (t) and e _{6 respectively.}
Switching is performed at (t), and signals e ₈ (t) and e ₉ (t) represented by the following equations of the waveforms shown in FIGS. 2H and 2I are generated and output to the adder circuit 10.

[0032] _{e 8 (t) = - (} A 1 A 2/2) cos (ω 1 t-π / 6) + (A 1 A 2 / π) [{cos (ω 1 -ω 2) t + cos (ω ₁ t + ω ₂ t-π / 3}-(1/3) {cos (ω ₁ t-3ω ₂ t + π / 3) + cos (ω ₁ t + 3ω ₂ t-π / 3)} + (1/5) {cos (ω ₁ t-5ω ₂ t + 2π / 3) + cos (ω ₁ t + 5ω ₂ t-π)}-(1/7) {cos (ω ₁ t-7ω ₂ t + π) + cos (ω ₁ t + 7ω ₂ t-4π / 3)} + ...] (10) e ₉ (t) =-(A ₁ A ₂ ) sin (ω ₁ t-π / 3 )-(A ₁ A ₂ / π) [{cos (ω ₁ t + ω ₂ t-2π / 3) -cos (ω ₁ -ω ₂ ) t}-(1/3) {cos (ω ₁ t + 3ω ₂ t-4π / 3) -cos (ω ₁ t-3ω ₂ t + 2π / 3)}-(1/5) {cos (ω ₁ t + 5ω ₂ t-2π) -cos (ω ₁ t- 5ω ₂ t + 4π / 3)}-(1/7) {cos (ω ₁ t + 7ω ₂ t-2π / 3) -cos (ω ₁ t-7ω ₂ t + 2π)} + ...] ( 11) The adder circuit 10 adds the output signals e ₇ (t), e ₈ (t) and e ₉ (t) of the switch circuits 2, 4 and 6 respectively, and outputs the waveforms shown in FIG. , The output signal e ₁₀ (t) expressed by the following equation is output to the output terminal 11 of FIG.

E ₁₀ (t) = e ₇ (t) + e ₈ (t) + e ₉ (t) = (3A ₁ A ₂ / π) {cos (ω ₁ -ω ₂ ) t- (1/5 ) cos (ω ₁ + 5ω ₂ ) t + (1/7) cos (ω ₁ -7ω ₂ ) t- (1/11) cos (ω ₁ + 11ω ₂ ) t + (1/13) cos (ω ₁ -13ω ₂ ) t + ...} (12) As can be seen from the equation (12), the output signal e ₁₀ (t) includes the third harmonic component, the ninth harmonic component, and the odd harmonic component, 15th harmonic component, 21st harmonic component ,. . . Etc. have been removed. FIG. 3 shows the frequency spectrum of the output signal of the frequency conversion circuit of FIG. 1 expressed by the equation (12).

As can be seen from the operation waveforms shown in FIG. 2, the output signal e ₁₀ (t) shown in FIG. 2 (J) coincides with the equation shown in the equation (12), and the output signal e ₁₀ (t) shown in FIG. The roughness of the waveform is smaller than that of the output signal e ₅₇ (t) of the conventional circuit shown in FIG. Further, as is clear from the equation (12) and FIG. 3, since it is sufficient to remove the fifth harmonic component or more with a filter, the filter having a simpler and cheaper structure in which the sloped portion of the frequency characteristic is gentler than that of the conventional method. Can be used to remove harmonic components.

Next, another embodiment of the present invention will be described. FIG. 4 shows a circuit configuration diagram of the second embodiment of the present invention. In this example, the phase division number is "5",
The first input signal e ₁₁ (t) input from the input terminal 15
Is directly supplied to the switch circuit 16 and is also supplied to the phase shift circuits 17, 18, 19 and 20, respectively, which are −2π / 5 (rad.) And −4π / 5 (ra.
d. ), -6π / 5 (rad.) And -8π / 5 (ra.
d. ) After being phase-shifted into a signal e ₁₂ (t), a signal e ₁₃ (t), a signal e ₁₄ (t) and a signal e ₁₅ (t), they are supplied to the corresponding switch circuits 21, 22, 23 and 24. To be done.

The switch circuit 16 receives the first input signal e
₁₁ (t) is switched by the second input signal e ₁₆ (t) which is a rectangular wave from the input terminal 25, and the signal e
₂₁ (t) is output. At the same time, the switch circuits 21, 22, 23 and 24 receive the input signals e ₁₂ (t), e.
₁₃ (t), e ₁₄ (t), and e ₁₅ (t) are supplied to the second input signal e ₁₆ (t) by the phase shift circuits 26, 27, 28, and 29, respectively, −2π / 5 (rad.), -4π / 5 (ra
d. ), -6π / 5 (rad.) And -8π / 5 (ra.
d. ) Switching by the phase-shifted signals e ₁₇ (t), signal e ₁₈ (t), signal e ₁₉ (t) and signal e ₂₀ (t), and signals e ₂₂ (t), e ₂₃ (t), e ₂₄ (t) and e ₂₅
(T) is output.

The adder circuit 30 uses these switch circuits 1
Output signals e of 6, 21, 22, 23 and 24
₂₁ (t), e ₂₂ (t), e ₂₃ (t), e ₂₄ (t) and e
₂₅ (t) is added and synthesized, and a signal e represented by the following equation
₂₆ (t) is output to the output terminal 31. e ₂₆ (t) = e ₂₁ (t) + e ₂₂ (t) + e ₂₃ (t) + e ₂₄ (t) + e ₂₅ (t) = 5A ₁ A ₂ / π {cos (ω ₁ -ω ₂ ) t- (1/9) cos (ω ₁ + 9ω ₂ ) t + (1/11) cos (ω ₁ -11ω ₂ t) t-(1/19) cos (ω ₁ + 19ω ₂ ) + (1 / 21) cos (ω ₁ -21ω ₂ ) t -...} (13) As can be seen from the above equation, the output signal e of the adder circuit 30
₂₆ (t) is the angular frequency (ω ₁ −ω ₂ ) of the difference between the angular frequencies of the first input signal input to the input terminal 15 and the second input signal input to the input terminal 25. The frequency conversion signal has a waveform, and its waveform is finer than that of the embodiment of FIG. The frequency spectrum of the output signal e ₂₆ (t) is shown in FIG. 5 from the equation (13).

As can be seen from this frequency spectrum, the harmonic components contained in the output signal e ₂₆ (t) are shifted to a higher order side than the output signal e ₁₀ (t) in FIG.
Therefore, the harmonic component can be removed by using a filter having a simple and inexpensive structure in which the slope of the frequency characteristic is gentler than that in the first embodiment.

In the embodiment shown in FIG. 1, the minimum number of phase divisions is "3", and in the embodiment shown in FIG. 4, the number of phase divisions is "3".
Although it is set to 5 ", the number of phase divisions is not limited to this and is" 7 ","
9 "or any other odd number may be set as the minimum unit and multiplied by 2 ⁿ (where n is a natural number) times. That is, for example, the number of phase divisions is from the minimum unit" 3 "to" 6 "," 12 "," 2 ".
It may be 4 "," 48 ", ..., or" 5 "," 1 "
"0", "20", "40", ...
7 ”,“ 14 ”,“ 28 ”,“ 56 ”...
In short, all the numbers except the integer represented by 2 ⁿ are possible as the phase division number.

The embodiment of FIG. 1 in which the number of phase divisions is "3" corresponds to a circuit in which the number of phase divisions is "6" when applied to a conventional circuit, and in FIG. 4 in which the number of phase divisions is "5". The embodiment corresponds to a conventional circuit in which the number of phase divisions is "10". Therefore, as compared with the conventional circuit in the case of the phase division number "4" shown in FIG. 12, the circuit of FIG. Can be done easily.

As a result, the first and second embodiments described above are applied to an integrated circuit that takes advantage of the need for balance adjustment, an SSB modulation circuit, and other signal spectrum changing devices (for example, a secret device). It can be used for various applications.

By the way, in the above-described first and second embodiments, since the adder circuits 10 and 30 are required at the final stage as in the conventional circuit, the characteristic deterioration due to the level mixing error by the adder circuit occurs. May occur.

Therefore, the third embodiment of the present invention described below is designed to prevent the characteristic deterioration due to the level mixing error by the adder circuit. 6 is a circuit configuration diagram of a third embodiment of the frequency conversion circuit according to the present invention, and FIG. 7 is a signal waveform diagram for explaining the operation of FIG.

In FIG. 6, from the input terminal 41 to FIG.
The first input signal e ₃₁ (t) shown in (A) is input and supplied to the phase division circuit 42, where π (rad.).
Of the signal e having three types of phases different from each other by dividing the phase range of
₃₁ (t), e ₃₂ (t) and e ₃₃ (t). 7 (B) and 7 (C) respectively show the above signal e _32.
The waveforms of (t) and e ₃₃ (t) are shown. Here, FIG.
As can be seen from (A) to (C), e ₃₁ (t) is A ₁
sin ω ₁ t, e ₃₂ (t) is A ₁ sin (ω ₁ t-π
/ 3), e ₃₂ (t) is A ₁ sin (ω ₁ t-2π /
3).

On the other hand, the second input signal e ₃₈ (t) is shown in FIG.
The rectangular wave shown in (H) is supplied from the input terminal 46 to the switching signal generation circuit 47, the switch circuit 48, and the inverter 51. The switching signal generation circuit 47 generates signals e ₃₄ (t), e ₃₅ (t), and e ₃₆ (t), which are synchronized with the second input signal e ₃₈ (t) and have different phases, respectively and in parallel. Output. 7 (D), (E) and (F) show the above signals e ₃₄ (t) and e, respectively.
The waveforms of ₃₅ (t) and e ₃₆ (t) are shown. Here, the amplitude of the second input signal e ₃₈ (t) is −π <ω ₂ t <0.
In case of “0” at 0, and “A ₂ ” at 0 <ω ₂ t <π, it is expressed by the following equation.

[0046]

[Equation 1] However, in the above formula, n is a natural number.

The switch circuits 43, 44 and 45 described above receive the input signals e ₃₁ (t), e ₃₂ (t) and e ₃₃ (t).
Corresponding to the switching signals e ₃₄ (t), e ₃₅
(T) and e ₃₆ is passed through the high-level period input _(t), performs a switching operation for cutting off the low-level period input, thereby to synthesize a selected output signal 7
A signal e ₃₇ (t) having a waveform as shown in (G) is generated.

This signal e ₃₇ (t) is sent to the switch circuit 48.
Is supplied to the switch circuit 50 after being inverted and amplified by the inverting amplifier 49. Switch circuit 48
Receives the second input signal e ₃₈ (t) from the input terminal 46 as a switching signal, and the switch circuit 5
For 0, the signal e ₃₉ (t) shown in FIG. 7 (I) obtained by inverting the polarity of the second input signal e ₃₈ (t) by the inverter 51 is input as the switching signal, and the switching signals e ₃₈ (t) and e ₃₉ are respectively input. The switching operation is performed to pass the input signal only during the period when (t) is at the high level.

The output signals of the switch circuits 48 and 50 are respectively added and synthesized, and the signal e shown in FIG.
₄₀ (t) and output to the output terminal 52. This output signal e ₄₀ (t) is represented by the following equation, and the angular frequency (ω ₁ −ω ₂ ) of the difference between the first input signal e ₃₁ (t) and the second input signal e ₃₈ (t) ) Is a frequency-converted signal having a basic angular frequency.

E ₄₀ (t) = − (A ₁ A ₂ / π) [sin {ω ₂ t-ω ₁ t- (π / 6)} + (1/5) sin {5ω ₂ t + ω ₁ t + (5π / 6)}-(1/7) sin {7ω ₂ t-ω ₁ t- (π / 6)} + ・ ・ ・] (15) Also, the frequency spectrum of this output signal e ₄₀ (t) is As shown in FIG. 8 from the equation (15), the third harmonic component and the ninth harmonic component of ω ₂ become zero as in the case of FIG. Therefore, also in the embodiment of the present invention, the fundamental wave can be easily detected by using the filter having the gentler slope portion of the frequency characteristic than the conventional one.

The phase division circuit 42 shown in FIG.
It has any one of (A), (B), and (C)
You. FIG. 9A shows the first input input to the input terminal 55.
Signal e ₃₁If (t) is output to the output terminal 58 through,
Both are -π / 3 phase shift circuit 56 and -2/3 phase shift circuit 57.
Output signal e₃₂(T), e
₃₃(T) is generated and output to the output terminals 59 and 60.
It is good.

In FIG. 9B, the first input signal e ₃₁ (t) input to the input terminal 55 is output to the output terminal 58 through and the output signal is output via the −π / 3 phase shift circuit 56. e ₃₂ (t) is generated and output to the output terminal 59, and
Further, by passing through -π / 3 phase shift circuit 61, a total of -2π /
In this configuration, a signal e ₃₃ (t) having a phase shift of 3 (rad.) Is generated and output to the output terminal 60.

In FIG. 9C, the first input signal e ₃₁ (t) input to the input terminal 55 is output to the output terminal 58 through, and the -2π / 3 phase shift circuit 57 outputs the output signal e _33. The point that (t) is generated and output to the output terminal 60 is the same as the configuration of FIG. 9A, but the output signal e ₃₂ (t)
9 is different from that of FIGS. 9A and 9B. That is, the input signal e ₃₁ (t) and the output signal e ₃₃ (t) of the −2π / 3 phase shift circuit 57 are added by the adder circuit 62, and the added signal is passed through an amplifier 63 that amplifies the added signal with an appropriate gain.
The signal e ₃₂ (t) that is phase-shifted by π / 3 (rad.) is generated and is output to the output terminal 59.

Further, the switching signal generating circuit 47 shown in FIG.
Has the circuit configuration shown in FIG. 10, for example. FIG.
, The second input signal e ₃₈ (t) input from the input terminal 65 (the input terminal 46 in FIG. 6) is input to one input terminal of the 2-input exclusive OR circuit (EX-OR gate) 69. Meanwhile, the -π / 3 phase shift circuit 66 causes -π /
3 (rad.) Phase-shifted and input to the other input terminal of the EX-OR gate 69, the signal e ₃₄ (t) shown in FIG. 7D is extracted from the EX-OR gate 69 and output. It is output to the terminal 72.

The output signal of the -π / 3 phase shift circuit 66 is input to one input terminal of the EX-OR gate 70, while the -π / 3 phase shift circuit 67 further outputs -π / 3 (ra).
d. ) By being phase-shifted and input to the other input terminal of the EX-OR gate 70, the signal e ₃₅ (t) shown in FIG. 7E is extracted from the EX-OR gate 70 and output to the output terminal 73. To be done.

Further, the inverter 68 causes −π (ra
d. ) The phase-shifted second input signal and the phase-shifted second input signal extracted by the -π / 3 phase shift circuit 67 by a total of -2/3 (rad.)
7 (F) and the exclusive OR operation is performed here.
Is generated as a signal e ₃₆ (t) and is output to the output terminal 74.

The third embodiment shown in FIG. 6 is a three-division phase system, and among the three types of input signals output from the phase division circuit 42, the phases between adjacent signals are shown in FIG.
As shown in (C), it is −π / 3 (rad.), But in the present invention, similarly, the phase between adjacent signals is −π / 5.
The present invention can be applied to an odd-numbered phase division method such as a 5-division phase method that is (rad.) Or a 7-division phase method that the phase between adjacent signals is −π / 7 (rad.). In this case, the roughness of the waveform of the output frequency converted signal becomes finer as the number of phase divisions increases, but the basic circuit operation is the same as in FIG. 6 regardless of the number of phase divisions.

Note that in FIG. 6, the signal output to the output terminal 52 has a fundamental frequency which is the difference between the frequency of the first input signal and the frequency of the second input signal.
It is clear from the conventional circuit and its operation that the output signal of the fundamental frequency of the sum can be obtained by reversing the arrangement of the first input signal phase or the second input signal phase.

As described above, in the embodiment shown in FIG.
Since the switch circuits 43 to 45, 48 and 50 are used instead of M, there is basically no problem of characteristic deterioration due to imbalance in the operation of the DBM. 1. Since the addition circuit essential to the embodiment of FIG. 4 is replaced with the switch circuit to eliminate the need, the problem of characteristic deterioration due to mixing error of signal levels by the addition circuit does not occur.

In the embodiment of FIG. 6, the minimum number of phase divisions is "3". However, the number of phase divisions is not limited to "7", "9", and other odd numbers are the minimum units, and ,
It may be 2 ⁿ (where n is a natural number) times that. That is, for example, as the number of phase divisions, all the numbers except the integer represented by 2 ⁿ can be used as the number of phase divisions, as in the embodiments of FIGS. 1 and 4 described above.

The embodiment of FIG. 6 in which the phase division number is "3" corresponds to a circuit in which the phase division number is "6" when applied to a conventional circuit. Therefore, the number of phase divisions shown in FIG.
Compared with the conventional circuit in the case of 4 ", the circuit of FIG. 6 can greatly improve the roughness of the waveform of the output frequency converted signal, and the circuit configuration can be simplified. Similar to FIGS. 1 and 4, the present invention can be applied to various applications such as application to an integrated circuit that makes use of the need for balance adjustment, application to an SSB modulation circuit, and other signal spectrum changing devices (for example, a secret device).

[0062]

As described above, according to the present invention,
Since the switch circuit is used instead of the DBM, it is possible to avoid the problem of characteristic deterioration due to the unbalance of the DBM, and to use a circuit having the same output signal waveform roughness as the conventional circuit using the switch circuit. Since it can be realized with a configuration with a small number of phase divisions, the circuit configuration can be simplified compared to the conventional one, and in the same size circuit, the roughness of the waveform of the frequency-converted output signal is greatly improved compared to the conventional one. it can.

Further, according to the present invention, by connecting the first and second switch circuits in cascade and providing the first and second switching signal generating means, an adding circuit for obtaining an output signal is unnecessary. Therefore, it is possible to prevent the characteristic deterioration due to the mixing error of the signal levels in the adding circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of FIG.

FIG. 3 is a diagram showing a frequency spectrum of the output signal of FIG.

FIG. 4 is a circuit configuration diagram of a second embodiment of the present invention.

5 is a diagram showing a frequency spectrum of the output signal of FIG.

FIG. 6 is a circuit configuration diagram of a third embodiment of the present invention.

7 is a signal waveform diagram for explaining the operation of FIG.

8 is a diagram showing a frequency spectrum of the output signal of FIG.

9 is a block diagram of each example of the phase division circuit of FIG.

10 is a circuit configuration diagram of an example of the switching signal generation circuit of FIG.

FIG. 11 is a circuit configuration diagram of an example of a conventional frequency conversion circuit.

FIG. 12 is a circuit configuration diagram of another example of a conventional frequency conversion circuit.

13 is a signal waveform diagram for explaining the operation of FIG.

14 is a diagram showing a frequency spectrum of the output signal of FIG.

[Explanation of symbols]

1, 15, 41 First input signal input terminal 2, 4, 6, 16, 21, 22, 23, 24 Switch circuit 3, 5, 17, 18, 19, 20 Phase shift circuit (phase dividing means) 7, 25, 46 Second input signal input terminal 8, 9, 26, 27, 28, 29 Phase shift circuit (switching signal generating means) 10, 30 Adder circuit 11, 31, 52 Output terminal 42 Phase division circuit (first Phase dividing means) 43, 44, 45 Switch circuit (first switch circuit) 47 Switching signal generating circuit (first switching signal generating means) 48, 50 Switch circuit (second switching circuit) 49 Inverting amplifier (second) Phase inversion means) 51 Inverter (second switching signal generating means) 56, 57, 61, 66, 67 Phase shift circuit

Claims (5)

[Claims] 1. A phase dividing means for phase-dividing a first input signal into a plurality of channel signals having mutually different phases, and switching based on the second input signal, the same number as the channel signals but different from each other in phase. Switching signal generating means for generating a signal, and a plurality of switch circuits provided in a one-to-one correspondence with the plurality of channel signals and selectively outputting the input channel signals according to the switching signals from the switching signal generating means. And an adder circuit that combines and outputs the output signals of the plurality of switch circuits, and the adder circuit outputs the first signal from the adder circuit.
A frequency conversion circuit which outputs a signal having a frequency component of a sum or a difference between the frequency of the input signal and the frequency of the second input signal. 2. The phase dividing means excludes an integer represented by 2 ⁿ (where n is a natural number) in a phase range of 2π (rad.) Of the first input signal at equal phase intervals. The first input signal is phase-divided into an arbitrary number of channel signals among a plurality of channel signals, and the switching signal generating means outputs the second input signal of 2π.
(Rad.) Phase range is generated at equal phase intervals and the same number of phase divisions as the channel signals are generated to generate a switching signal from the second input signal, and the plurality of switch circuits are provided from the phase division means. As many channel signals as the number of the channel signals are provided, the channel signals are switched based on the switching signal having the same phase shift amount as the channel signals to selectively output the input channel signals, and the frequency of the first input signal is output from the adder circuit. The frequency conversion circuit according to claim 1, wherein the frequency conversion circuit outputs a signal whose fundamental frequency is the sum or difference of the frequency of the second input signal and the frequency of the second input signal. 3. A first phase dividing means for phase-dividing a first input signal into a plurality of first channel signals having mutually different phases, and the same number as the first channel signals based on the second input signal. And a plurality of first switching signal generating means for generating switching signals having mutually different phases, and a plurality of input first channel signals provided in a one-to-one correspondence with the plurality of first channel signals. With a plurality of first switch circuits for selectively outputting the signal according to the switching signal from the first switching signal generating means, and a plurality of first switch circuits having different phases from each other after combining the output signals of the plurality of first switch circuits. Second phase dividing means for outputting two channel signals, and second switching means for generating switching signals having the same number as the second channel signals but different phases based on the second input signal. A plurality of signal generating means are provided in a one-to-one correspondence with the plurality of second channel signals, and the input second channel signals are selectively output by a switching signal from the second switching signal generating means. A plurality of second switch circuits, and combining the output signals of the second switch circuits to obtain a sum or difference frequency between the frequency of the first input signal and the frequency of the second input signal. A frequency conversion circuit, which outputs a signal having a component. 4. The first phase dividing means sets the phase range of π (rad.) Of the first input signal at equal phase intervals,
And, the first input signal is phase-divided into an arbitrary number of first channel signals among a plurality of numbers except an integer represented by 2 ⁿ (where n is a natural number), and the first switching signal generation is performed. The means generates, from the second input signal, a switching signal obtained by dividing the phase range of π (rad.) Of the second input signal at equal phase intervals by the same number of phases as the first channel signal. The second phase dividing means divides a signal obtained by combining the output signals of the first switch circuit into two phases of 0 degree and −180 degrees, and the second switching signal generating means is configured to generate the second switching signal generating means. The two input signals are divided into two phases of 0 degree and -180 degrees to generate two switching signals, and the plurality of first channel signals are switched by the switching signal from the first switching signal generating means. The frequency of the first input signal according to the order of Serial signals having a frequency component of the sum or difference between the frequency of the second input signal, the frequency converting circuit of claim 3, wherein the outputting by synthesizing the output signal of the second switch circuit. 5. The number of phase divisions by the first phase division means and the number of switching signals generated by the first switching signal generation means are odd numbers, respectively. Frequency conversion circuit.