JPH0936739A - Reference divider value setting method for PLL tuner - Google Patents

Abstract

(57) Abstract: Even if a signal of a reference oscillator connected to a voice QPSK demodulation circuit of BS is used as a crystal oscillation signal input to a PLL circuit for U / V channel selection, a local signal is received from a reception channel. An object of the present invention is to provide a reference divider value setting method that can reduce the error of the oscillation frequency. SOLUTION: For each reception channel, reference divider values # 1 to # 1 that minimize the difference between the local oscillation frequency required for each reception channel and each programmable divider value calculated from each reference divider value are set. Calculate in # 9 and set this as the reference divider value for each receive channel. Therefore, even if the crystal oscillation signal of the BS QPSK demodulation circuit is divided by the reference divider value and used as the reference signal for phase comparison, the frequency error can be reduced for each reception channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer type tuner used for frequency conversion of high frequency signals in television receivers and the like.

[0002]

2. Description of the Related Art In recent years, frequency synthesizer type tuners have become popular in television tuners. Due to advances in high-frequency PLL circuit technology, terrestrial to satellite broadcasting (hereinafter abbreviated as BS) and communication satellites (hereinafter abbreviated as CS)
The appearance of a PLL circuit that supports up to the frequency band of, which allows satellite broadcasting / terrestrial wave integrated tuner (hereinafter, referred to as "U / V tuner")
BS / U / V integrated tuner, satellite broadcasting / communication satellite / terrestrial integrated tuner (hereinafter BS / CS / U)
/ V integrated tuner) is generalized.

The periphery of the conventional PLL circuit is constructed as shown in FIG. The local oscillation signal (local oscillation frequency f _LO ) from the local oscillator 115 is divided by the prescaler 116 by N and divided by the programmable divider 117 by M. The crystal oscillation signal (crystal oscillation frequency f _X ) from the crystal oscillator 121 is divided by the reference divider 120 into L.

The output of the programmable divider 117 and the output of the reference divider 120 are the phase comparator 119.
After being compared with, the data is output from the charge pump 122 and converted into an oscillation frequency control voltage (hereinafter abbreviated as BT voltage) 127 through the low pass filter 123.
As the programmable divider value M of the programmable divider 117, different values are sent from the microcomputer 118 for each reception channel, and the local oscillator frequency f _LO is determined by the programmable divider value M. The relational expression among the programmable divider value M, the local oscillation frequency f _LO , the reference divider value L, the crystal oscillation frequency f _X, and the prescaler value N can be expressed by the following equation.

M = (f _LO · L) / (f _X · N) (1) However, M is rounded off to the right of the decimal point. In a general U / V tuner, the error of the local oscillation frequency f _LO is reduced, so that the programmable divider value The crystal oscillation frequency f _X is 4 MHz so that M can always be set to an integer value.
In many cases, the PLL circuit 124 having several kinds of reference divider values L also changes the reference divider value L in order to change the frequency resolution (f _X · N / L). A fixed reference divider value is used for all channels.

[0006]

In such a conventional configuration, it is necessary to provide the 4 MHz crystal oscillator 121 for selecting the U / V channel, and there is a problem that the number of parts is increased.

B without the 4 MHz crystal oscillator 121
It is conceivable that the oscillation frequency of the crystal oscillator connected to the S voice QPSK demodulation circuit is replaced by 5.7272 MHz, but in this case, there is a problem that the error of the local oscillation frequency increases depending on the reception channel.

The present invention provides a U / V type integrated tuner.
The voice Q of BS without crystal oscillator of 4MHz is provided for the crystal oscillation signal input to the PLL circuit for channel tuning.
Oscillation signal 5.7 of the reference oscillator connected to the PSK demodulation circuit
An object of the present invention is to provide a reference divider value setting method capable of reducing an error of a local oscillation frequency with respect to a reception channel even when 272 MHz is used as a crystal oscillation signal input to a PLL circuit.

[0009]

According to a reference divider value setting method of the present invention, for each reception channel, a local oscillation frequency f _L2 required in each reception channel and each programmable divider value calculated from each reference divider value are calculated. A reference divider value that minimizes the difference from the local oscillation frequency f _L1 is calculated, and this is set as the reference divider value for each reception channel.

Therefore, even if the 5.7272 MHz crystal oscillation signal connected to the QPSK demodulation circuit of the BS is divided by the reference divider value and used as the reference signal for phase comparison, the local oscillation frequency for each reception channel is obtained. A reference divider value that reduces the error can be set for each reception channel.

Further, for each receiving channel, the difference between the local oscillation frequency f _L1 is controlled by the programmable divider value calculated from a specific reference divider value, the local oscillation frequency f _L2 required by each receiving channel ,
Counts the number of channels within a specific frequency, calculates the number of channels for all reference divider values, and uses the reference divider value with the highest channel count number as the first reference divider value. For the channel whose local oscillation frequency error (f _L1 −f _L2 ) at the divider value is not within the specified frequency and the reference divider value other than the first reference divider value, the second and subsequent reference divider values are the same as above. Is set, and the local oscillation frequency error (f _L1 −f _L2 ) is set within a specific frequency on all channels, the second and subsequent reference divider values are set, and among the several types of set reference divider values, Local oscillation frequency error of each receiving channel (f _L1 −f
_The feature is that the reference divider value that minimizes _L2 ) is set to the reference divider value of each reception channel.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The reference divider setting method of the present invention will be described below with reference to the flowchart.

FIG. 1 shows a first embodiment. In the subroutine # 1, the maximum possible reference divider value L _max of the reference divider values is calculated from the maximum local oscillation frequency f _LOmax of the reception channel by the following second equation obtained by _{modifying the above first equation} .

L _max = f _X · N · M / f _LOmax (2) However, the fractional part is rounded down. Next, in subroutines # 4 to # 8, the number of reception channels J
_In the channel J in the _ch , the local oscillation frequency f _L1 controlled by the programmable divider value M sent from the microcomputer 118 is obtained by the following third equation obtained by modifying the first equation, and f _{L1 = f X · N · M} / L (3) obtaining a fourth type by a local oscillator frequency error f of the local oscillation frequency f _L2 and the local oscillation frequency f _L1 required by channel J _err (L) below.

F _err (L) = | f _L1 − f _L2 | (4) Then, in subroutines # 2 to # 9, the reference divider value L is changed so that the local oscillation frequency error f _err (L) is minimized. Determine the reference divider value L.
It is calculated for each reception channel, and the reference divider REF (J) that minimizes the local oscillation frequency error f _err (L) of channel J is determined.

The reference divider value L for each reception frequency calculated in this way is used as the reference divider 120.
And to change the reference divider value L of the reference divider 120 to the previously written reference divider value L according to the reception frequency in synchronization with the switching of the programmable divider value M according to the reception frequency from the microcomputer 118. By BS Q
Even when the number of components is reduced by using the 5.7272 MHz crystal oscillation signal connected to the PSK demodulation circuit as the signal source of the reference divider 120, the error of the local oscillation frequency with respect to the reception channel can be reduced.

FIG. 2 shows a second embodiment. In this embodiment, similarly to the subroutine # 1 shown in a subroutine # 10 in FIG. 1, to calculate the maximum reference divider value L _{ma x} possible reference divider value L. Then, in Subroutine # 11, the minimum reference divider value L _min is determined so that the frequency resolution Δf shown in the following formula 5 falls within a specific frequency, and the range of L is determined as in the formula 7 below.

[0018] _{Δf = N · f x / L} min (5) L min = N · f x / △ f (6) L min <L <L max (7) Next, a subroutine # 2 shown in FIG. 1 Similar to # 8,
In the subroutines # 12 to # 18, the local oscillation frequency f _L1 and the local oscillation frequency error f are calculated from the third and fourth equations.
_err (L) is obtained, and the reference divider value L is changed to determine the reference divider value L that minimizes the local oscillation frequency error f _err (L). It is calculated for each reception channel, and the reference divider RE that minimizes the local oscillation frequency error f _err (L) of the reception channel J is obtained.
Determine F (J).

The reference divider value L for each reception channel calculated in this manner is used as the reference divider 1
20. The reference divider value L of the reference divider 120 is changed to the previously written reference divider value L according to the reception channel in synchronization with the switching of the programmable divider value M according to the reception frequency from the microcomputer 118. By B
5.7272MH connected to the S QPSK demodulation circuit
Even when the number of components is reduced by using the z crystal oscillation signal as the signal source of the reference divider 120, the error of the local oscillation frequency can be reduced with respect to the reception channel.

FIG. 3 shows a third embodiment. In this embodiment, similarly to the embodiment shown in FIG. 1, first, in the subroutines # 20 to # 30, the maximum reference divider value L _max is obtained from the above-mentioned second equation, and for a certain reference divider value L, , J local oscillation frequency errors f _eer (L) of each channel are obtained from the above equation 4 and the number of channels C _O (L) within a certain frequency ER is checked. Find it for each reference divider value L,
The reference divider value L having the largest number of channels is set as the first reference divider value L _OK (1). Next, in subroutines # 31 to # 41, the channel CH (J) for which the first reference divider value L _OK (1) satisfies the local oscillation frequency error f _err (L) ≧ ER of the above equation 4,
With the channel of CH (J) and the reference divider value L other than the first reference divider value L _OK (1),
The local oscillation frequency error f _err (L) is obtained again, and the local oscillation frequency error f _{err is} obtained at each reference divider value L.
The reference divider value L with the largest number of channels (L) <ER is set to the second reference divider L.
Setting _OK (2), the above calculation is repeated, and I type reference dividers L _OK (I) are obtained until the local oscillation frequency error of all channels becomes smaller than ER. Then, in subroutine # 42, a reference divider value that minimizes the local oscillation frequency error ER of each reception channel is set in the reference divider 120 from the I types of reference dividers in correspondence with each reception channel.

The reference divider value L calculated for each reception channel is determined and the microcomputer 118
From the QPSK demodulation circuit of the BS by changing the reference divider value L of the reference divider 120 to the reference divider value L written in advance according to the receiving channel in conjunction with the switching of the programmable divider value M according to the receiving frequency. Even when the crystal oscillation signal of 5.7272 MHz connected to is used as the signal source of the reference divider 120 to reduce the number of parts, it is possible to reduce the error of the local oscillation frequency with respect to the reception channel.

FIG. 4 shows a fourth embodiment. In the subroutines # 43 and # 44, the set number P of the reference divider values L to be set is determined, and the maximum reference divider value L is set.
_{Find max} . Next, as in the embodiment shown in FIG.
In subroutines # 45 to # 65, P types of reference divider values are determined. Then, in subroutine # 66, the reference divider 12 of each reception channel is selected from among the P types of reference dividers so that the local oscillation frequency error ER of each reception channel is minimized.
Set to 0. It is shown in FIG. 3 that the reference divider value L of the reference divider 120 is changed to the reference divider value L written in advance in accordance with the receiving channel and received in conjunction with the switching of the programmable divider value M according to the receiving frequency. It is similar to the embodiment described above.

FIG. 5 shows a fifth embodiment. In subroutines # 66 and # 67, the maximum reference divider value L _max is obtained from the second equation, and the frequency resolution Δf shown in the fifth equation is within a specific frequency as in the embodiment shown in FIG. Minimum reference divider value L to enter
_min is determined, and the range of the reference divider value L is determined by the above-mentioned formula 7. Next, as in the embodiment shown in FIG. 3, subroutines # 68 to # 88 determine I type reference divider values L _OK (I). Then, in subroutine # 89, the reference divider value that minimizes the local oscillation frequency error ER of each reception channel is set to the reference divider value of each reception channel from the I types of reference divider values. The reference divider value L of the reference divider 120 is interlocked with the switching of the programmable divider value M according to the reception frequency.
Is changed to the reference divider value L written in advance in accordance with the reception channel and the reception is performed as in the embodiment shown in FIG.

FIG. 6 shows a sixth embodiment. Subroutine
Chin # 90 to # 92, similar to the embodiment shown in FIG.
Then, the P type of reference divider value is determined, and the second
From the formula, the maximum reference divider value L _max Figure 2
As in the embodiment shown in FIG.
The minimum reference is set so that the numerical resolution Δf falls within a specific frequency.
Lens divider value L_min And the riff of equation 7 above
Determine the range of the value of the divider value L. Next shown in FIG.
Similar to the embodiment described above, subroutines # 93 to # 11
3 types of P reference divider values L_OKFind (P)
You. Then, in subroutine # 114, referencing of P types is performed.
Local oscillation of each reception channel from the divider value L
Reference divider value L that minimizes frequency error ER
To the reference divider value L of each receiving channel
I do. Programmable divider value M according to the reception frequency
Of the reference divider 120
The reference divider value L is predicted according to the receiving channel.
Change to the reference divider value L written for
Receiving is similar to that of the embodiment shown in FIG.

The flow chart of each of the above-described embodiments is executed by a microprocessor built in the television receiver, or a microprocessor prepared separately from the television receiver is used in each adjustment step. It can also be configured to write a reference divider value for each reception channel.

[0026]

As described above, according to the present invention, the crystal image of the PLL circuit uses the crystal oscillation signal of 5.7272 MHz connected to the QPSK demodulation circuit of the BS, and the television image is received in the satellite receiver. On-board frequency synthesizer U / V tuner, BS / U / V integrated tuner, and BS / CS / U / V integrated tuner PLL
It is possible to reduce the local oscillation frequency error by setting several types of reference divider values for the circuit and setting reference divider values for each receiving channel. Therefore, a 4 MHz crystal oscillator is not provided for the U / V tuner. In addition, a local oscillator with a small local oscillation frequency error can be realized.

[Brief description of drawings]

FIG. 1 is a flow chart showing a first embodiment.

FIG. 2 is a flow chart showing a second embodiment.

FIG. 3 is a flow chart diagram showing a third embodiment.

FIG. 4 is a flow chart showing a fourth embodiment.

FIG. 5 is a flow chart showing a fifth embodiment.

FIG. 6 is a flow chart showing a sixth embodiment.

FIG. 7 is a configuration diagram around a conventional PLL circuit.

[Explanation of symbols]

 1 to 114 Subroutine 115 Local Oscillator 116 Prescaler 117 Programmable Divider 118 Microcomputer 119 Phase Comparator 120 Reference Divider 121 Crystal Oscillator 122 Charge Pump 123 Low Pass Filter 124 PLL Circuit

Claims (6)

[Claims] 1. A sample frequency signal obtained by dividing an output frequency of a voltage-controlled local oscillator by a prescaler by N and further dividing by a program divider value M according to a receiving channel, a reference signal by a reference divider value L. In a frequency synthesizer / tuner that compares the phase with a reference frequency and controls the oscillation frequency of the voltage-controlled local oscillator so that the phase difference becomes smaller, for each reception channel, the local oscillation frequency f _L2 required for each reception channel and A reference divider value setting method of calculating a reference divider value having the smallest difference from the local oscillation frequency f _L1 with respect to each programmable divider value calculated from each reference divider value and setting this to the reference divider value for each reception channel. 2. The reference divider value setting method according to claim 1, wherein the frequency resolution of the local oscillator sets the reference divider value within a reference divider value range within a specific frequency. 3. A sample frequency signal obtained by dividing the output frequency of the voltage-controlled local oscillator by N by a prescaler and further dividing by a program divider value M according to a receiving channel, and dividing a reference signal by a reference divider value L. A frequency synthesizer / tuner that compares the phase with the reference frequency and controls the oscillation frequency of the voltage-controlled local oscillator so that the phase difference becomes smaller.Controls the programmable divider value calculated from a specific reference divider value for each receive channel. Local oscillation frequency f
And _L1, the difference between the local oscillation frequency f _L2 required by each receiving channel, counting the number of channels that are within a specific frequency, to calculate the number of channels with respect to all reference divider value, most channels A reference divider value having a large number of counts is set as a first reference divider value, and a local oscillation frequency error (f _L1 −f _L2 ) at the first reference divider value is not within a specific frequency and the first reference divider. For the reference divider values other than the above values, the second
Subsequent reference divider values are set, and for all channels, the local oscillation frequency error (f _L1 −f _L2 ) is set to the second and subsequent reference divider values until the frequency falls within a certain frequency, and several reference types are set. A reference divider value setting method for setting the reference divider value that minimizes the local oscillation frequency error (f _L1 −f _L2 ) of each reception channel from the divider values to the reference divider value of each reception channel. 4. The reference divider value setting method according to claim 3, wherein the number of reference divider values to be set is limited and the reference divider value of each reception channel is set. 5. The reference divider value setting method according to claim 3, wherein the reference divider value of each reception channel is set within a reference divider value range within which the frequency resolution of the local oscillator is within a specific frequency. 6. The reference divider according to claim 3, wherein the number of reference divider values to be set is limited, and the reference divider value of each reception channel is set within the reference divider value range within which the frequency resolution of the local oscillator is within a specific frequency. Value setting method.