JPH0945087A - Semiconductor memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispose backing wirings without enlarging the width and spacing of word lines, to reduce the area of a chip and also to shorten a time for transfer of a signal from a word line selecting circuit to a memory cell. SOLUTION: A plurality of word lines W1-Wm are divided into groups each comprising adjacent lines in the number of N, and a first drive circuit 3 encoding the state of distribution of a level in the word lines in the number of N in each group, which is driven by a word, line selecting circuit 2, into a coded signal according to unit signals in a smaller number of signals than N is provided. Backing wirings SW1 and SW2 corresponding to the unit signals respectively are disposed in parallel to the word lines, and a second drive circuit 4 driving the other ends of the corresponding word lines is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly, to a semiconductor memory circuit having means for shortening a signal transmission time of a word line.

[0002]

2. Description of the Related Art As an example of a conventional semiconductor memory circuit,
FIG. 6 shows a mask ROM type semiconductor memory circuit in which memory cells are arranged vertically.

This semiconductor memory circuit (first example) includes a plurality of memory cells MC11 to MCm arranged in a matrix in a row direction and a column direction and arranged vertically in a column direction.
cell array 1 having a plurality of memory cells M
A plurality of word lines W1 to Wm which are provided corresponding to the respective rows of C11 to MCmn and select a memory cell of the corresponding row at a selected level, and a plurality of memory cells MC
A plurality of digit lines which are provided corresponding to the respective columns of 11 to Mmn and transmit the storage information of the memory cells in the selected state of the corresponding column, and one ends of the plurality of word lines W1 to Wm are connected to an address signal ( (Not shown) and a word line selection circuit 2 for setting a predetermined word line to a selection level.

In such a semiconductor memory circuit,
A memory cell (M) connected to one digit line (Di)
C1i to MC6i) and the word lines (W1 to W6) for selecting these memory cells are arranged as shown in FIG. 7, and the width and interval of the word lines (W1 to W6) are determined according to the manufacturing technology. We make it as small as possible.

Next, the operation of the semiconductor memory circuit will be described.

When one memory cell (for example, MC11) is selected, first, one word line (W1) is set to a low selection level by the word line selection circuit 2,
The other word lines (W2 to Wm) are set to the non-selected high level. One digit line (D1) is selected by a digit line selection circuit (not shown). As a result, all the memory cells (MC21 to MCm1) other than the selected memory cell (MC11) become conductive, and a signal of a level corresponding to the storage content of the selected memory cell (MC11) is applied to the digit line (Di). Is read.

In such a semiconductor memory circuit,
Since the word lines W1 to Wm are usually formed of polycrystalline silicon or the like, their resistance values are relatively large, and since many memory cells are connected, the parasitic capacitance also becomes large. Therefore, the transmission time of the signal from the word line selection circuit 2 to the memory cell becomes longer, and this word line selection circuit 2
The longer the memory cell is, the longer the transmission time becomes.

In order to shorten the signal transmission time from the word line selection circuit, word line selection circuits 2a and 2b are provided at both ends of the word line as shown in FIG. There is also an example (second example) of driving a word line. Further, although not shown in the figure, there is also an example (third example) in which a word line selection circuit is provided at an intermediate point between word lines.

However, in these examples, the word line selection circuit is increased or the word line is divided and driven, so that the signal transmission time of the word line becomes shorter, but conversely the chip area becomes larger. Become.

As shown in FIG. 9, lining wirings SW1x to SW6x made of low resistance material aluminum are arranged in parallel with each of a plurality of word lines W1 to W6, and connected at a plurality of locations to form word lines. There is also an example (fourth example) in which the resistance is reduced (for example,
No. 145862).

[0011]

In the first example, the conventional semiconductor memory circuit described above has a plurality of word lines W1 to W
m are driven from one end, and since these word lines have relatively large resistance values and parasitic capacitances, there is a problem that the signal transmission time from the word line selection circuit becomes longer. In the second and third examples, since the word line is driven from both ends or the word line is divided and driven, the transmission time is correspondingly reduced, but the chip area is increased. Yes, fourth
In the example, although the transmission time can be sufficiently reduced by the backing wirings SW1x to SW6x made of aluminum of a low resistance material arranged in parallel, the width and spacing of the wiring made of aluminum of a low resistance material are polycrystalline. It is necessary to increase the width and the interval of the word lines made of silicon, so that there is a problem that the chip area increases or a region for arranging the backing wiring cannot be obtained.

An object of the present invention is to provide a backing wiring without increasing the width and spacing of word lines,
It is another object of the present invention to provide a semiconductor memory circuit capable of reducing a chip area and a transmission time of a signal from a word line selection circuit to each memory cell.

[0013]

A semiconductor memory circuit according to the present invention has a memory cell array having a plurality of memory cells arranged in a matrix in a row direction and a column direction, and a memory cell array corresponding to each row of the plurality of memory cells. A plurality of word lines for selecting a memory cell in a corresponding row when the memory cell is at a selected level, and a memory cell in a selected state corresponding to each column of the plurality of memory cells. A plurality of digit lines for transmitting storage information; a word line selection circuit connected to one end of each of the plurality of word lines for setting a predetermined word line of the plurality of word lines to a selection level according to an address signal; The plurality of word lines which are arranged close to a line selection circuit are divided into adjacent N (N is an integer of 2 or more) groups, and each of the divided groups is A first driving circuit for encoding information on the distribution state of the levels of the N word lines into a coded signal having a predetermined coded level and comprising unit signals having a smaller number of signals than the N, and outputting the coded signal; Corresponding to each of the unit signals constituting the coded signals of each of the divided sets, and formed of a low-resistance material in parallel with the N word lines of the corresponding set, and the corresponding units from the first driving circuit. A plurality of backing wirings for transmitting signals; and a coded signal of each of the divided sets arranged on the other end side of each of the plurality of word lines, and a corresponding set of N
A second drive circuit for driving the other end of each of the word lines at the same level as that of the word line selection circuit. Further, the coding level of each unit signal constituting the coded signal is configured as at least two potential levels.

Further, the coding level of the unit signal constituting the coded signal is set to three potential states, N is set to 2 and 2
The information on the level distribution state of one set of word lines is transmitted by one backing wiring, and the level distribution state of one set of two word lines is changed by one of the two word lines. There are three distribution states: a distribution state at the selection level, a distribution state when the other is at the selection level, and a distribution state when both are at the non-selection level. And an intermediate potential generating circuit for generating a potential of
A first inverter receiving one level of a corresponding pair of two word lines at an input terminal; and a gate receiving the other level of the two word lines at a gate and connecting the source to the first level.
An N-channel transistor whose drain is connected to the output terminal of the inverter and whose drain is connected to one end of a corresponding set of backing wiring, whose gate receives the other level of the two word lines and whose source has the intermediate potential And a P-channel transistor that connects the drain to one end of the backing wiring, and a second drive circuit is provided corresponding to each of the two sets of word lines. And the output terminal is connected to the other end of one of the two word lines of the corresponding set and has an intermediate threshold voltage between the intermediate potential and the power supply potential. Second
And a first input terminal connected to the other end of the backing wiring, a second input terminal connected to an output terminal of the second inverter, and an output terminal connected to the other of the two word lines. A NAND connected to the other end and having at least the first input terminal having an intermediate threshold voltage between the intermediate potential and the ground potential
It is configured as a circuit having a gate.

Further, each unit signal of the coded signal is of a binary type having two potential levels, the first and second driving circuits are circuits of binary type logic gates,
The level distribution state of a set of N word lines includes a distribution state when one of the N word lines is at a selected level and a distribution state when all of the N word lines are at a non-selected level. And N is configured as a number greater than two.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The first embodiment is different from the conventional semiconductor memory circuit shown in FIG. 6 in that a plurality of word lines W1 to Wn arranged close to a word line selection circuit 2 are connected to each other.
2 for each group
A first drive circuit 3 for coding information on the distribution state of the levels of the word lines into a coded signal composed of one unit signal having three coded levels and outputting the coded signal; A first drive circuit 3 which is formed of aluminum of low resistance material and is arranged in parallel with two word lines of a set corresponding to the unit signal constituting the coded signal, and
, And a plurality of lined lines (SW1, W2,...) For transmitting corresponding unit signals, and the coded signals of each of the divided groups arranged at the other end of each of the plurality of word lines W1 to Wm. A second drive circuit 4 for driving the other end of each of the two word lines of the corresponding set at the same level as the level by the word line selection circuit is provided.

In the first embodiment, the coding level of the unit signal constituting the coded signal has three potentials: a power supply potential level, a ground potential level, and an intermediate potential level intermediate between the power supply potential and the ground potential. Level.
The distribution state of the levels of the two word lines is represented by the distribution state when one of the two word lines is at the selected level, the distribution state when the other is at the selected level, and the distribution state when both are at the non-selected level. Of three distribution states.

The first drive circuit 3 includes an intermediate potential generating circuit 31 for generating an intermediate potential Vm intermediate between the power supply potential and the ground potential, and a corresponding pair of two word lines (W1, W2
/ W3, W4 /...) At the input terminal.
IV32 / ...) and two word lines (W1, W
2 / W3, W4 / ...) (W2 / W4 / ...)
And the source is switched to the first inverter (IV31 /
IV32 / ...) and an N-channel transistor (MT31 / MT33 /) having a drain connected to one end of a corresponding set of backing wires (SW1 / SW2 / ...).
…) And two word lines (W1, W2 / W3,
, W4 /...), The source receives the intermediate potential Vm, and the drain is the corresponding backing wiring (SW1 /.
SW2 / ...) and a P-channel transistor (MT32 / MT34 / ...) connected to one end of the switch.

The second drive circuit 4 connects the input terminal to the other end of the corresponding set of backing wires (SW1 / SW2 / ...) and connects the output terminal to the corresponding two word lines (W1, W1, W2
/ W3, W4 / ...) and a second inverter (IV41 / IV42) connected to the other end of one (W1 / W3 / ...) and having an intermediate potential Vm and an intermediate threshold voltage between the power supply potentials.
/.) And a backing wiring (SW1) corresponding to the first input terminal.
/ SW2 / ...), the second input terminal is connected to the output terminal of the second inverter (IV41 / IV42 / ...), and the output terminal is connected to two word lines (W1, W2 / W3, W4). /
..) Connected to the other end of the other (W2 / W4 /...) And having a HAND gate (G41 / G42 /...) Having a threshold voltage between the intermediate potential Vm and the ground potential. Has become.

Next, the operation of the first embodiment will be described.

The intermediate potential Vm is, for example, 5 to 6 of the power source potential.
3V as V, inverter (IV41 / IV42 / ...)
Has a threshold voltage of 4 V and a NAND gate (G41 / G4
2 / ...) is 2V.

In the level distribution state when one of the two word lines W1 and W2 is at a low selected level and the other is at a nonselected high level, the inverter IV
Since the output terminal 31 is at a high level (power supply potential level), the transistor MT31 is on, and the MT32 is off, one end of the lining SW1 is driven by a high-level signal and transmitted to the other end. Since the level (high level, power supply potential level) of the transmitted signal is higher than the threshold voltage of the inverter IV41, the output signal of the inverter IV41 becomes low level and drives the other end of the word line W1. That is, the word line W1 by the word line selection circuit 2
Drive at the same level as In addition, inverter I
Since the output signal of V41 is at a low level, the output signal of NAND gate G41 is at a high level and drives the other end of word line W2. This level is also the same as the level of the word line W2 by the word line selection circuit 2.

Next, when the word line W2 is at the selected level and W1 is at the non-selected level, the transistor MT31 is turned off,
Since the transistor MT32 is turned on, the backing wiring S
One end of W1 is driven at the intermediate potential Vm. Inverter IV41 receiving this intermediate potential at the other end of backing wiring SW1
Has its threshold voltage higher than the intermediate potential Vm, its output signal becomes high level, and the other end of the word line W1 is driven at the same level as the level of the word line W1 by the word line selection circuit 2. The two input terminals of the NAND gate G41 are at the high level and the intermediate potential Vm level, and the output signal of the NAND gate G41 having the lower threshold voltage is at the low level, and the other end of the word line W2 is connected. The word lines are driven at the same level as the levels of the word lines W1 and W2 by the word line selection circuit 2.

FIG. 2 shows the state of the potential level of each part due to these operations. In FIG. 2, "H" is a high level of the power supply potential level, "L" is a low level of the ground potential level, and M is a level of the intermediate potential Vm.

FIG. 3 is a schematic view showing the arrangement of word lines and backing wirings according to the first embodiment.

As shown in FIG. 3, the backing wirings SW1 to SW
Since each of W3 is arranged at a ratio of one word line to two word lines, the backing lines SW1 to SW
3 is larger than the width and spacing of the word lines W1 to W6 due to manufacturing technology.
6 can be arranged without affecting the width and spacing. That is, the backing wiring can be arranged without increasing the chip area.

As described above, in the first embodiment,
The backing wiring can be arranged without increasing the width and spacing of the word lines, and the number of circuit elements of the first and second driving circuits 3 and 4 is much smaller than that of the word line selecting circuit 2. The chip area can be reduced as compared with the second to fourth examples, and the coded signal from the first drive circuit 3 is transmitted at high speed by the backing wiring made of a low-resistance material, and the second drive circuit 4 Since decoding is performed and each word line is driven from both ends, it is possible to shorten a signal transmission time from the word line selection circuit 2 to each memory cell.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, each unit signal of the coded signal by the first drive circuit 3a is a binary type having two potential levels, and the first and second drive circuits 3a
a and 4a are circuits constituted by NAND gates G31, G32, G43 to G46 of binary logic gates.

If each unit signal of the coded signal is of a binary type, if one set is composed of two word lines, two distribution states when one of these two word lines is at the selected level are: And 3 of the distribution state when both are at the non-selection level
If two distribution states are coded, two bits are required, two backing wirings are required, and the number of word lines and backing wirings becomes the same. Therefore, N is set to a number larger than 2, that is, 3 or more. .

In the second embodiment, four word lines are connected.
One set is provided, and three backing wirings are provided for this set. Therefore, the backing wiring (SW11 to SW11
Even if the width and spacing of SW13) are 33% larger than the width and spacing of word lines (W1 to W4), the backing wiring does not increase the chip area.

In the second embodiment, the level distribution state of the four word lines W1 to W4 and the backing wiring SW
FIG. 5 shows the distribution state of the levels of 1 to SW13, that is, the distribution state of the level of each unit signal of the coded signal. In the second embodiment, all (four) when one of the four word lines W1 to W4 is at the selection level (L).
, The level distribution state when all the word lines W1 to W4 are at the non-selection level (H), and the level distribution state when the word lines W1 to W4 are at the standby state (all at the L level). Therefore, a 3-bit coded signal, that is, three backing wirings are required.

It is apparent that the same effects as those of the first embodiment can be obtained in the second embodiment.

Since the number of distribution states of the level that can be transmitted by the 3-bit coded signal is "8", all the word lines are at H level.
Assuming that two distribution states of level and L level are included, up to six word lines can be set as one set. That is, three backing wirings may be used for six word lines.

When the number of backing wirings per set is "4", all word lines have H level and L level of 2 lines.
Up to 14 word lines can be associated with one distribution state.

Further, assuming that the coding level of each unit signal constituting the coded signal is, for example, 3 potential levels in the same manner as in the first embodiment, a distribution state of 9 levels can be represented by two unit signals. Therefore, assuming that all the word lines include the distribution states of the H level and the L level, up to seven word lines can be made to correspond by two backing wirings. That is, the number of backing wirings can be reduced with respect to the number of word lines in one set.

In these embodiments, the first drive circuits 3 and 3a are provided close to the word line selection circuit 2. However, depending on the circuit configuration of the word line selection circuit 2, one set of the first drive circuits 3 and 3a may be provided. Word line selection circuits 2 with less number than word lines
Can be used to represent the level distribution of a set of word lines, in which case the first drive circuit is not required.

[0040]

As described above, according to the present invention, a plurality of word lines are divided into adjacent N pairs, and the divided groups are divided by the first driving circuit disposed close to the word line selection circuit. The distribution state of the level of each of the N word lines is coded into a coded signal using unit signals having a smaller number of signals than the N, and a backing wiring made of a low-resistance material corresponding to each unit signal of the coded signal is supported. A set of N word lines is arranged in parallel, driven by these unit signals, and the coded signal transmitted to the other end of the backing wiring is decoded by a second drive circuit to be used for each of the N word lines. By driving the other end,
Since the backing wiring can be arranged without increasing the width and interval of the word lines, and the first and second driving circuits can be configured with a smaller number of circuit elements than the word line selection circuit, the chip area can be reduced. In addition, since the coded signal is transmitted at high speed through the backing wiring to drive each of the N word lines, the time required for transmitting the signal from the word line selection circuit to each memory cell can be reduced. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a distribution state of a level of a pair of word lines and a backing wiring for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a layout schematic diagram showing a layout state of word lines and backing wires according to the embodiment shown in FIG. 1;

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a level distribution state of a pair of word lines and backing wirings for explaining the operation of the embodiment shown in FIG. 4;

FIG. 6 is a circuit diagram showing a first example of a conventional semiconductor memory circuit.

FIG. 7 is a layout schematic diagram mainly showing a layout state of word lines in the semiconductor memory circuit shown in FIG. 6;

FIG. 8 is a block diagram showing a second example of a conventional semiconductor memory circuit.

FIG. 9 is a layout schematic diagram showing a layout state of word lines and backing wirings in a fourth example of a conventional semiconductor memory circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell array 2, 2a, 2b word line selection circuit 3, 3a, 4, 4a drive circuit 31 intermediate potential generation circuit D1 to Dn digit lines G31, G32, G41 to G46 logic gates IV31, IV32, IV41, IV42 inverter MC11 MCmn Memory cells MT31, MT32 Transistors SW1 to SW3, SW11 to SW13, SW1x to SW
6x Backing wiring W1-Wm Word line

Claims (7)

[Claims] 1. A memory cell array including a plurality of memory cells arranged in a matrix in a row direction and a column direction, and a memory cell array provided corresponding to each row of the plurality of memory cells and corresponding to a row at a selection level. A plurality of word lines for selecting a memory cell, a plurality of digit lines provided corresponding to each column of the plurality of memory cells and transmitting storage information of a selected memory cell in the corresponding column; A word line selection circuit that is connected to one end of each of the plurality of word lines and sets a predetermined word line among the plurality of word lines to a selection level in accordance with an address signal; The word lines are divided into sets of adjacent N lines (N is an integer of 2 or more), and information on the level distribution state of the N word lines in each of the divided groups is obtained. A first drive circuit having a fixed coding level and coding and outputting a coded signal composed of unit signals having a number of signals less than N, and each unit constituting the coded signal of each of the divided sets; A plurality of backing wirings formed of a low resistance material in parallel with a corresponding set of N word lines corresponding to each signal and transmitting a corresponding unit signal from the first drive circuit; The coded signal of each of the divided sets is arranged at the other end of each word line, and the other end of each of the N word lines of the corresponding set is driven at the same level as the level by the word line selection circuit. And a second drive circuit. 2. The semiconductor memory circuit according to claim 1, wherein the coding level of each unit signal constituting the coded signal is at least two potential levels. 3. The coding level of a unit signal constituting a coded signal is set to three potential states, N is set to 2 and 2
2. The semiconductor memory circuit according to claim 1, wherein the information on the level distribution state of the set of word lines is transmitted by one backing wiring. 4. A distribution state of levels of a pair of word lines, a distribution state when one of the two word lines is at a selected level, and a distribution state when the other is at a selected level. 4. The semiconductor memory circuit according to claim 3, wherein there are three distribution states of the selection level. 5. A first drive circuit is provided corresponding to each of a set of an intermediate potential generating circuit for generating an intermediate potential between a power supply potential and a ground potential, and two word lines, and a second set of corresponding sets is provided. A first inverter receiving one level of the two word lines at an input terminal, and a gate receiving the other level of the two word lines at a gate and connecting a source to an output terminal of the first inverter; An N-channel transistor having a drain connected to one end of a corresponding set of backing wirings; a gate receiving the other level of the two word lines; a source receiving the intermediate potential; A circuit including a P-channel transistor connected to one end, a second drive circuit provided corresponding to each of the two sets of word lines, and an input end connected to the other end of the backing wiring of the corresponding set. Contact with A second inverter having an output terminal connected to the other end of one of the two word lines of the corresponding set and having a threshold voltage intermediate between the intermediate potential and the power supply potential; At least an input terminal is connected to the other end of the backing wiring, a second input terminal is connected to the output terminal of the second inverter, and an output terminal is connected to the other end of the two word lines. 5. The semiconductor memory circuit according to claim 4, wherein the first input terminal includes a NAND gate having a threshold voltage between the intermediate potential and the ground potential. 6. The semiconductor memory circuit according to claim 1, wherein each unit signal of the coded signal is of a binary type having two potential levels, and the first and second driving circuits are circuits of binary type logic gates. 7. The level distribution state of a set of N word lines is such that all of the distribution states when one of the N word lines is at a selected level and all of the N word lines are unselected. 7. The semiconductor memory circuit according to claim 6, wherein N is a number greater than 2 including a distribution state at a level.