JPH0945918A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: To improve the withstand voltage of the gate insulating film of a three-dimensional MOS transistor such as SGT. SOLUTION: A concave portion 33 is formed in a silicon substrate 31 by a first plasma treatment with a gas containing carbon,
4 using high frequency excitation down-flow type plasma processing equipment
With a gas containing 0% or more and less than 100% oxygen, the processing pressure (in Torr display) is set to a high frequency power density (W / cm).
^{The second} plasma treatment is performed under the condition that the value divided by ² ) is 0.07 or more and 0.27 or less and the treatment temperature is 200 ° C. or less,
The concave portion 3 of the silicon substrate 31 is formed by the first plasma treatment.
3 The SiC layer 34 formed on the surface is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a three-dimensional insulated gate type semiconductor device.

[0002]

2. Description of the Related Art FIG. 6 (a) shows a MOS transistor which has been generally used conventionally. This MOS
In order to manufacture a transistor, the well 12 is formed in the silicon substrate 11, and then the gate insulating film 13 is formed on the surface of the element active region of the silicon substrate 11. Then, the gate electrode 14 and its sidewall 15 are formed on the gate insulating film 13, and the source 16 and the drain 17 which are a pair of high-concentration impurity diffusion layers are formed in the well 12.

By the way, in order to improve the degree of integration of a semiconductor integrated circuit device composed of MOS transistors and the like, the constituent elements such as MOS transistors may be miniaturized, but there is a limit to microfabrication. On the other hand, in the MOS transistor shown in FIG.
4 extends parallel to the surface of the silicon substrate 11, and this MOS transistor is planar. Therefore, this M
There is a limit to the improvement in the degree of integration of semiconductor integrated circuit devices using OS transistors.

Therefore, the SGT as shown in FIG.
MO called (Surrounding Gate Transistor)
An S-transistor has been proposed (for example, Shigeyoshi Watanabe “Technical Perspective of Large-Capacity Memory” Proceedings of SEMI Technology Symposium 93, p. 11-17, December 1993).

In order to manufacture this MOS transistor, the well 12 is formed in the silicon substrate 11, and then the silicon substrate 1 is subjected to plasma treatment using a gas containing carbon.
1 to form a recess. Then, after forming the gate insulating film 13 around the convex portion surrounded by the concave portion, the source 16 and the drain 17 are formed at the bottom portion of the concave portion and the top portion of the convex portion by ion implantation, respectively. Then, a polycrystalline silicon film is patterned on the gate insulating film 13 to form a gate electrode 14
To form

In the MOS transistor shown in FIG. 6B, the gate electrode 14 extends vertically to the surface of the silicon substrate 11, and this MOS transistor is three-dimensional.
Therefore, if this MOS transistor is used, as shown in FIG.
The integration degree of the semiconductor integrated circuit device can be improved as compared with the case of using the MOS transistor shown in (a).

[0007] FIG. 7 is a Weibull statistical diagram showing the cumulative failure rate of the dielectric strength when a silicon oxide film is used as the gate insulating film of a MOS transistor. The horizontal axis represents the total amount of charge (hereinafter referred to as oxide film breakdown charge Q _BD ) that could be conducted before the gate oxide film caused dielectric breakdown, and Q _BD
Means that the larger the value, the better the quality of the gate oxide film. The vertical axis is the cumulative defective rate, and this cumulative defective rate is 5
The size of the physical quantity (Q _{BD in} this case) when it reaches 0% serves as a guide for performance comparison.

The data 22 in FIG. 7 is the data of the planar MOS transistor shown in FIG.
The Q _BD at the time when the cumulative defective rate is reached is about 22 C / cm ² . On the other hand, the data 21 in FIG.
In the three-dimensional MOS transistor shown in (b), data is obtained when the gate insulating film 13 is immediately formed in the recess formed by plasma processing, and Q _BD at the time when the cumulative defective rate of 50% is reached is about 0. It is 3 C / cm ² .

Although the detailed mechanism of the breakdown voltage inferior in the three-dimensional MOS transistor shown in FIG. 6 (b) is not clear, when the plasma treatment using the gas containing carbon is performed on the silicon substrate 11, the plasma treatment is performed. When Si and C react with each other, the silicon substrate 11
Since the SiC layer, which is a semiconductor, is formed on the exposed surface, it is considered that if the gate insulating film 13 is formed while the SiC layer is left, the withstand voltage of the gate insulating film 13 is affected.

Therefore, when forming a three-dimensional MOS transistor as shown in FIG. 6B, in order to make the withstand voltage of the gate insulating film 13 high enough for practical use, the silicon substrate is used. The SiC layer formed on the exposed surface of 11 must be removed by plasma treatment. Then, in order to remove this SiC layer, O ₂ or O ₃
It is known that the silicon substrate 11 may be processed using oxygen plasma such as (for example, Norihiro Ikeda et al., "Damage to Si Surface of Fluorocarbon Plasma", Proc. 45th Semiconductor / Integrated Circuit Technology Symposium ,
p76-81, December 1993).

[0011]

However, if the plasma treatment with oxygen is simply added to the plasma treatment for forming the recesses, fine surface roughness of the surface of the silicon substrate 11, which is called microroughness, increases. When this microroughness increases, the dielectric strength of the gate insulating film 13 is rather deteriorated (for example, Koji Makihara "Surface Microroughness and Device Characteristics", Ultra Clean Technology Workshop Proceedings, p73-9).
1, September 1992). Such deterioration of the withstand voltage of the gate insulating film 13 significantly reduces the reliability of the semiconductor device having the MOS transistor.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the withstand voltage of a gate insulating film such as a MOS transistor three-dimensionally formed in a recess.

[0013]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of subjecting a silicon substrate to a first plasma treatment using a gas containing carbon, and the first step. 40% or more 10 after plasma treatment
Under the condition that the value obtained by dividing the second plasma treatment with a gas containing less than 0% oxygen by the high-frequency power density (W / cm ² ) of the treatment pressure (in Torr display) is 0.07 or more and 0.27 or less. The step of applying the silicon substrate, and the second step
And the step of forming a gate insulating film on the exposed surface of the silicon substrate.

In one aspect of the present invention, a recess is formed in the silicon substrate by the first plasma treatment,
The gate insulating film is formed on the side surface of the recess.

In one aspect of the present invention, the second plasma processing is performed by a high frequency excitation downflow type plasma processing apparatus.

In one aspect of the present invention, the processing temperature of the second plasma processing is 200 ° C. or lower.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to manufacture of a MOS transistor will be described below with reference to the drawings. 1A to 1C are cross-sectional views showing the method of the present embodiment in the order of manufacturing steps.

First, as shown in FIG. 1A, a photoresist 32 having a pattern having a side length of 1 μm is formed on a silicon substrate 31 after a well (not shown) is formed by a lithography technique. .

Next, as shown in FIG. 1 (b), a parallel plate type plasma processing apparatus is used and the processing pressure is 1.0 Torr.
Under the condition of high frequency power of 300 W, for example, CF ₄ : CH
Dry etching using the photoresist 32 as a mask is performed on the silicon substrate 31 with a mixed gas of F ₃ : Ar = 3: 3: 40. By this plasma treatment (first plasma treatment), a recess 33 having a depth of 1 μm is formed in the silicon substrate 31. At the same time, Si is formed on the exposed surface of the silicon substrate 31 due to the combination of carbon and silicon.
The C layer 34 is formed. As the etching gas, HBr or another halogen-based gas may be used instead of CF ₄ or CHF ₃ under the condition that at least carbon is contained.

Next, as shown in FIG. 1 (c), a microwave-excited downflow-type plasma processing apparatus, which is a kind of high-frequency excitation downflow-type plasma processing apparatus, is used and the processing pressure is 0.8 Torr and the microwave power is 800 W Under the condition of the processing temperature of 150 ° C., the silicon substrate 31 is plasma-processed by the mixed gas of O ₂ : CF ₄ = 20: 1 (second
Plasma treatment). By this plasma treatment, Si
The C layer 34 is oxidized by a large amount of oxygen to become a SiO ₂ film,
Then, since this SiO ₂ film is removed by CF ₄ , the SiC layer 34 is eventually removed by the plasma treatment.

Next, as shown in FIG. 1D, the photoresist 32 is ashed and removed by plasma treatment under an arbitrary condition using O ₂ gas. Then, after a washing process,
As shown in FIG. 6B, the gate insulating film 13 and the gate electrode 14 are formed on the side surfaces of the recess 33 to form a three-dimensional S
A GT type MOS transistor is manufactured.

The subsequent manufacturing process of the MOS transistor will be described with reference to FIG.

First, the gate insulating film 13 is formed around the convex portion surrounded by the concave portion by a thermal oxidation method, and then the source 16 and the drain 17 are formed at the bottom of the concave portion and the top of the convex portion by ion implantation. To do.

Then, a polycrystalline silicon film is formed on the entire surface of the gate insulating film 13, and the polycrystalline silicon film is etched back to form the gate electrode 14 made of the polycrystalline silicon film only on the side surface of the recess. . Note that the gate insulating film 13 on the upper surface of the convex portion is simultaneously removed by this etch back process. After that, the high-concentration impurity diffusion layer may be formed on the surface of the silicon substrate 12 by further implanting ions into the concave portion using the convex portion and the gate electrode 14 as a mask.

In the above embodiment, the plasma treatment shown in FIG. 1 (b) was performed by the parallel plate type plasma treatment apparatus. However, like the plasma treatment shown in FIG. 1 (c), the microwave excitation downflow type plasma treatment apparatus is used. You may perform with a plasma processing apparatus.

As the high frequency excitation downflow type plasma processing apparatus, an ECR type plasma processing apparatus or the like may be used in addition to the microwave excitation downflow type plasma processing apparatus.

In this embodiment, a three-dimensional SGT type MOS transistor as shown in FIG. 6B is manufactured, but the present invention is a planar MO transistor as shown in FIG. 6A.
It can also be applied to the manufacture of S-transistors.

[0028]

EXAMPLES Next, examples in which the conditions of the second plasma treatment are changed variously in the above embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 2 shows the model of the plasma processing apparatus used to remove the SiC layer 34 when the gate insulating film is a silicon oxide film, and Q at the time when the cumulative withstand voltage failure rate reaches 50%. The relationship with _BD is shown. From FIG. 2, if the person in the case of using the high-frequency excitation down-flow type plasma processing apparatus (Q _BD = 24C / cm ² or so) has a parallel plate type plasma processing apparatus (Q _BD = 22C /
It is clear that Q _BD is larger than (cm ² ).
That is, in order to remove the SiC layer 34, the high frequency excitation downflow type plasma processing apparatus is superior.

As described above, the high frequency excitation downflow type plasma processing apparatus is excellent as an apparatus for performing the second plasma processing, by using this apparatus.
It is considered that the damage given to the silicon substrate 31 can be suppressed to the minimum.

Here, the structure of an ECR type plasma processing apparatus which is a kind of high frequency excitation downflow type plasma processing apparatus will be described.

In the ECR type plasma processing apparatus, as shown in FIG. 3, the gas used for etching is the gas inlet 41.
Is introduced into the ion generation chamber 42, and the high frequency introduced from the waveguide 43 interacts with the magnet coil 44 that surrounds the ion generation chamber 42, resulting in highly ionized plasma.

This plasma is supplied to the external bias circuit 45.
After the kinetic energy is controlled by the action of the mesh ring 46, which is controlled to an arbitrary electric potential, the wafer 48 placed in the processing chamber 47 is plasma-processed. Further, in order to constantly supply fresh plasma to the surface of the wafer 48, the inside of the processing chamber 47 is exhausted by a pump through the exhaust port 49.

In FIG. 4, the gate insulating film is a silicon oxide film, a microwave-excited downflow type plasma processing apparatus is used, and a mixed gas of O ₂ and CF ₄ is used to remove the SiC layer 34 for 10 seconds. When the plasma treatment is performed, the concentration of O ₂ and the cumulative failure rate of withstand voltage are 50%.
It shows the relationship with Q _BD when it reaches. The plasma processing conditions are a processing pressure of 0.8 Torr, a microwave power of 800 W, and a processing temperature of 150 ° C.

As is clear from FIG. 4, when the oxygen concentration is extremely low, Q _BD is hardly improved even when the plasma treatment is performed. This is because even if plasma treatment is applied, SiC
This is because the layer 34 has not been removed. The oxygen concentration of Q _BD is remarkably improved from about 40%, but in order to stabilize Q _{BD at} about 22 C / cm ² , an oxygen concentration of 90% or more is required for plasma treatment. I know there is.

As described above, in order to always obtain a stable Q _BD of 22 C / cm ² or more, it is preferable that the oxygen concentration is 90% or more. However, when oxygen alone cannot completely oxidize SiC, Since there is no CF ₄ that remains and etches SiO ₂ , the oxygen concentration is preferably less than 100%.

In FIG. 5, the gate insulating film is a silicon oxide film, a microwave excitation downflow type plasma processing apparatus is used, and O ₂ : CF ₄ = 20: 1, processing time is 8 seconds, and processing temperature is 200 ° C. In the case where the second plasma treatment for removing the SiC layer 34 is performed, the plasma treatment pressure (in Torr display) is set to the microwave power density (W).
/ Cm ² ) (hereinafter referred to as P / P ratio) and the defect density of the silicon oxide film.

From FIG. 5, the defect density of the silicon oxide film is P
It can be seen that there is a correlation with the / P ratio. Since the defect density of a practical silicon oxide film is 1.0 / cm ² or less,
When the plasma treatment is performed in the P / P ratio range of 0.07 or more and 0.27 or less, a practical silicon oxide film can be obtained, but in other ranges, the defect density of the silicon oxide film remarkably increases. Manufacturing yield is reduced. Therefore, SiC
Optimal P in plasma processing for removing layer 34
It can be seen that the / P ratio is in the range of 0.07 or more and 0.27 or less.

Table 1 below shows O ₂ : CF ₄ = 20: 1,
When the plasma treatment for removing the SiC layer 34 is performed under the conditions of the treatment time of 8 seconds, the treatment pressure of 0.8 Torr, and the microwave power of 800 W, the cumulative treatment defect rate of the plasma treatment temperature and the withstand voltage reaches 50%. Q _BD at the time
Shows the range of the processing time and the range of the optimum processing time at which the value becomes 22 C / cm ² or more.

[0040]

[Table 1]

When a processing time other than the optimum processing time in Table 1 is used, the SiC layer 34 is not completely removed when the processing time is short, and when the processing time is long, the silicon substrate 31 is exposed. In any case, Q _BD is 22 C / cm ² because the microroughness on the surface increases.
Therefore, the withstand voltage of the gate insulating film 13 is not improved.

As is clear from Table 1, as the plasma processing temperature rises, the optimum processing time becomes shorter.
It is about 2 seconds at 0 ° C and less than 1 second at 250 ° C. Also,
When the plasma processing temperature rises, Q _BD increases to 22 C / cm ²
The processing time as described above is also shortened, and is about 6 seconds at 200 ° C. and about 3 seconds at 250 ° C. On the other hand, in the plasma processing apparatus, it takes about 2 seconds from the start of processing to the stabilization of plasma. Therefore, when removing the SiC layer 34, it is preferable to set the plasma treatment temperature to 200 ° C. or lower in view of the inability to perform stable treatment when the plasma treatment temperature exceeds 200 ° C.

[0043]

In the method of manufacturing a semiconductor device according to the present invention, the first plasma treatment is applied to the silicon substrate, and the SiC layer which is the semiconductor layer formed on the exposed surface of the silicon substrate in association with the first plasma treatment. Are removed by the second plasma treatment. In the first plasma treatment, a recess may be formed on the surface of the silicon substrate.

Since the oxygen concentration of the gas used in the second plasma treatment is 40% or more and less than 100%, the SiC layer is effectively removed without increasing the microroughness, and the gate insulation having a large Q _BD is obtained. A film can be formed. Further, the processing pressure (T
Since the value obtained by dividing (orr display) by the high frequency power density (W / cm ² ) is 0.07 or more and 0.27 or less, the defect density is small and a practical gate insulating film can be formed.

When the second plasma processing is performed by using the high frequency excitation downflow type plasma processing apparatus,
It is possible to suppress the damage given to the silicon substrate to the minimum, and it is possible to form a gate insulating film having a large total charge amount Q _BD that can be energized before dielectric breakdown occurs.

When the processing temperature in the second plasma processing is 200 ° C. or lower, the plasma processing time for obtaining the gate insulating film having a large Q _BD can be sufficiently secured. A gate insulating film having a large Q _BD can be stably formed.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, when forming a three-dimensionally arranged element such as a MOS transistor, it is possible to form a high-quality gate insulating film having an excellent withstand voltage. A highly reliable semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a graph showing the relationship between the type of plasma processing apparatus used to remove the SiC layer and the withstand voltage of the gate insulating film in the present invention.

FIG. 3 is a schematic diagram of an ECR type plasma processing apparatus which is a kind of high frequency excitation downflow type plasma processing apparatus used in the present invention.

FIG. 4 is a graph showing the relationship between the oxygen concentration in the gas used to remove the SiC layer and the breakdown voltage of the gate insulating film in the present invention.

FIG. 5 is a graph showing the relationship between the processing pressure and power density when removing the SiC layer and the defect density of the gate insulating film in the present invention.

FIG. 6 shows a planar MOS transistor and a three-dimensional M.
FIG. 6 is a cross-sectional view illustrating an OS transistor.

FIG. 7 is a graph for explaining the deterioration of the withstand voltage of the gate oxide film by plasma-treating a silicon substrate with a gas containing carbon.

[Explanation of symbols]

 31 Silicon Substrate 32 Photoresist 33 Recesses 34 SiC Layer

Claims (4)

[Claims] 1. A step of subjecting a silicon substrate to a first plasma treatment with a gas containing carbon, and a second plasma with a gas containing 40% or more and less than 100% oxygen after the first plasma treatment. Processing
High-frequency power density (W / c)
m ² ), a step of applying the silicon substrate under the condition that the value divided by m ² ) is 0.07 or more and 0.27 or less, and a gate insulating film is formed on the exposed surface of the silicon substrate after the second plasma treatment. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein a recess is formed in the silicon substrate by the first plasma treatment, and the gate insulating film is formed on a side surface of the recess. . 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second plasma processing is performed by a high frequency excitation downflow type plasma processing apparatus. 4. The processing temperature of the second plasma processing is 2
The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is 00 ° C. or lower.