JPH0951267A - Phase synchronization circuit - Google Patents

Abstract

(57) Abstract: A phase locked loop circuit is prevented from malfunctioning due to disconnection of a reference clock. A missing tooth clock detection circuit (5) detects a detection clock (DE) having a frequency higher than that of the reference clock (Rin) during a high level period (hereinafter referred to as "H").
The number of pulses of TCK is counted, and when the count reaches a count set for a period longer than the steady-state period of “H” of the reference clock Rin, or the reference clock Rin is at a low level ( (Hereinafter referred to as “L”), the number of pulses of the detection clock DETCK is counted, and the count number is set to correspond to a period longer than the “L” steady state period of the reference clock Rin. When it reaches, the phase comparator 1 is fixed to the reset state, and when the level of the reference clock Rin transits thereafter, the reset state of the phase comparator 1 is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked L (Phase-Locked L) used for a clock supply device of a digital transmission device such as an intra-station line termination board in a telephone office.
oop (hereinafter referred to as PLL) circuit.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional PLL circuit. This PLL circuit uses the reference clock Ri
It has an input terminal IN for inputting n, and the input terminal IN is connected to the reference clock input terminal RIN of the phase comparator 1. Output terminal Uou of lead information S1u of phase comparator 1
The output terminal Dout of t and the delay information S1d is connected to the lead information input terminal and the delay information input terminal of the charge pump 2, respectively. The output terminal of the charge pump 2 is connected to the input terminal of the loop filter 3, and the output terminal of the loop filter 3 has a voltage controlled oscillator (Voltage Cont.
It is connected to the input terminal of a roled oscillator (hereinafter referred to as VCO) 4. The output terminal of VCO4 is output terminal O
It is connected to the UT and also to the feedback clock input terminal VIN of the phase comparator 1. FIG. 3 is a circuit diagram showing a configuration example of the phase comparator 1 in FIG.

The reference clock input terminal RIN is connected to the clock input terminal CK of the delay flip-flop (hereinafter referred to as D-FF) 1a, and the feedback clock input terminal VIN is connected to the clock input terminal CK of the D-FF 1b. The data input terminal D and the set input terminal PRN of the D-FF 1a are connected to the power supply potential Vcc, and similarly the D-FF 1a.
The data input terminal D and the set input terminal PRN of 1b are connected to the power supply potential Vcc. The output terminal Q of the D-FF 1a is connected to the input terminal of the inverter 1c and the first input terminal of the 2-input NAND circuit 1d. The output terminal of the inverter 1c is a 2-input NOR
It is connected to the first input terminal of the circuit 1e. D-FF
The output terminal Q of 1b is connected to the input terminal of the inverter 1f and is also connected to the first input terminal of the 2-input NAND circuit 1g. The output terminal of the inverter 1f is 2
It is connected to the first input terminal of the input NOR circuit 1h. The output terminal of the NAND circuit 1d is a 3-input AND circuit 1
i is connected to the first input terminal of the NAND circuit 1g, and the output terminal of the NAND circuit 1g is connected to the second input terminal of the AND circuit 1i. The reset input terminal DRST is connected to the third input terminal of the AND circuit 1i.

The output terminal of the AND circuit 1i is D-FF1.
The reset input terminals CLRN of a and 1b are connected. The output terminal of the NOR circuit 1e is connected to the second input terminal of the NOR circuit 1h and the second input terminal of the NAND circuit 1g, and is also connected to the advance information output terminal UOUT. The output terminal of the NOR circuit 1h is the NOR circuit 1
It is connected to the second input terminal of e and the second input terminal of the NAND circuit 1d, and is also connected to the delay information output terminal DOUT via the inverter 1j. The NOR circuits 1e and 1h connected in a stack form a set / reset type flip-flop (hereinafter referred to as SR-FF). Next, the operation of FIG. 2 will be described. The phase comparator 1 compares the phase of the reference clock Rin with the phase of the feedback clock S4 from the VCO 4, and outputs the advance information S1u when the phase of the feedback clock S4 is behind the phase of the reference clock Rin, Delay information S1 when the phase of the feedback clock is ahead of the phase of the reference clock
Output d. The charge pump 2 inputs the advance information S1u or the delay information S1d, converts them into a DC voltage level, and outputs an output signal S2. The loop filter 3 removes a high frequency component included in the output signal S2 and outputs a DC voltage output signal S3. The VCO 4 outputs the feedback clock S4 which is an output signal having a frequency based on the output signal S3 from the loop filter 3.

[0005]

However, the PLL circuit of FIG. 2 has the following problems. That is, FIG.
In the case where the internal phase comparator 1 has the configuration shown in FIG. 3, when the reference clock Rin has a frequency lower than the frequency of the reference clock Rin, that is, a toothless clock is input, the phase comparator 1 malfunctions. There was a possibility of causing. FIG. 4 is a time chart for explaining the operation of FIG. 3, in which the vertical axis represents the logic level and the horizontal axis represents time. The operation of the conventional phase comparator when the reference clock Rin has a missing tooth (that is, a state where the clock is disconnected) will be described with reference to this figure. Period T1
In SR, the advance information S1u is generated by setting the SR-FF based on the rising edge of the reference clock Rin and resetting based on the rising edge of the feedback clock S4 which is delayed from the phase of the reference clock Rin. In the period TB, missing teeth occur in the reference clock Rin.

In the period T2, the SR-FF is set based on the rising edge of the feedback clock S4 and is reset based on the rising edge of the reference clock Rin input after the feedback clock S4, thereby delay information S1.
An inverted signal of d is generated. That is, since the reference clock Rin is missing in the period TB, the delay information S1d is generated in the period T2 in which the advance information S1u should be generated.
Since the inversion signal is generated, the control direction of the frequency of the output signal S4 is inverted and the phase shift occurs. This is essentially what should not happen in a PLL circuit. In order for this phase comparator to operate normally, it is necessary to change the edge of the feedback clock S4 after the rising edge or the falling edge of the reference clock Rin, and the rising edge or the falling edge of the feedback clock S4 must be changed. After that, it is necessary to change the edge of the reference clock Rin.

[0007]

According to the present invention, in order to solve the above-mentioned problems, when the phase of the feedback clock is behind the phase of the reference clock, the feedback clock is set based on the edge of the reference clock and the feedback is set. Advance information is generated by resetting based on the edge of the clock, and when the phase of the feedback clock is ahead of the phase of the reference clock, set based on the edge of the feedback clock, and set to the edge of the reference clock. A phase comparison circuit having an SR-FF that generates delay information by resetting based on the charge information, a charge pump that inputs the advance information or the delay information, and outputs a DC voltage corresponding to the advance information or the delay information, A filter for removing high frequency components contained in the output signal of the charge pump, and a frequency corresponding to the output signal of the filter. VC to output of the feedback clock
The following means is provided in the phase synchronization circuit including O and. That is, while the reference clock is at a high level (hereinafter referred to as "H"), the number of pulses of the detection clock having a frequency higher than that of the reference clock is counted, and the count number is set to "H" of the reference clock. When the count number set for a period longer than the normal period is reached, or the reference clock is at a low level (hereinafter, "L").
During the period), the number of pulses of the detection clock is counted, and when the count number reaches the count number set corresponding to the period longer than the steady state period of “L” of the reference clock, A missing tooth clock detection circuit is provided that fixes the SR-FF in the reset state and then releases the reset state when the level of the reference clock changes.

According to the present invention, since the phase locked loop circuit is constructed as described above, in the steady state, the SR-FF in the phase comparison circuit is used when the phase of the feedback clock is delayed from the phase of the reference clock. , Advance information is generated by setting based on the edge of the reference clock and resetting based on the edge of the feedback clock, and if the phase of the feedback clock leads the phase of the reference clock, the feedback clock The delay information is generated by setting the delay information based on the edge of the reference clock and resetting based on the edge of the reference clock. Next, when a missing tooth occurs in the reference clock, the missing tooth clock detection circuit counts the number of pulses of the detection clock during the period when the reference clock is "H", and the counted number is "H" of the reference clock. When the count number set for a period longer than the steady state period of is reached, the SR-FF is fixed to the reset state,
After that, when the level of the reference clock changes from "H" to "L", the reset state is released. Then, S
The R-FF performs the same operation as in the steady state. Similarly, the missing clock detection circuit counts the pulses of the detection clock during the period when the reference clock is "L", and the count number is longer than the steady state period when the reference clock is "L". The SR-FF is fixed in the reset state when the count number set corresponding to the above is reached, and then the reset state is released when the level of the reference clock transits from "L" to "H". Then, the SR-FF
The same operation as the regular operation is performed, and lead information or delay information is output. The charge pump inputs advance information or delay information, converts them into a DC voltage level, and outputs them to the filter. The filter removes a high frequency component contained in the output signal of the charge pump and outputs a DC voltage output signal. The VCO outputs the feedback clock, which is an output signal having a frequency based on the output signal of the filter. Therefore, in this phase locked loop, even if the reference clock has a missing tooth, the conventional phase shift does not occur. Therefore, the above problem can be solved.

[0009]

1 is a block diagram of a phase comparator showing an embodiment of the present invention. In this phase comparator, a missing clock detection circuit 5 is connected to the conventional phase comparator 1 shown in FIG. The tooth drop clock detection circuit 5 includes an input terminal RIN for the reference clock Rin and an input terminal DIN for the detection clock DETCK which is a clock faster than the reference clock Rin. Further, in FIG. 1, when the phase comparator 1 receives the output signal S5 of the missing clock detection circuit 5 from the reset input terminal DRST, it is in an initial state (that is, the advance information S1u is “L” and the delay information S1d is The configuration returns to the "H" state). Further, although not shown, similarly to FIG. 2, the output terminal Uout of the advance information S1u and the output terminal Dout of the delay information S1d of the phase comparator 1 are connected to the advance information input terminal and the delay information input terminal of the charge pump 2, respectively. ing. The output terminal of the charge pump 2 is connected to the input terminal of the loop filter 3, and the output terminal of the loop filter 3 is VCO.
4 input terminals. The output terminal of the VCO 4 is connected to the output terminal OUT, and the phase comparator 1
Is connected to the feedback clock input terminal VIN.

FIG. 5 is a circuit diagram showing a configuration example of the missing tooth clock detection circuit in FIG. Input terminal RIN is D
-D-FF connected in common to each reset terminal CLRN of FFs 5A1 to 5A8 and via the inverter 5c
The reset terminals CLRN of 5B1 to 5B8 are commonly connected. The input terminal DETCK is D-FF5A1 ~
The clock input terminals ck of 5A8 and 5B1 to 5B8 are commonly connected. Data input terminal D of D-FF5A1 and each set input terminal PR of D-FF5A1-5A8
N is connected to the power supply potential Vcc. D-FF5A
The output terminal Q of 1 is the data input terminal D of D-FF5A2.
It is connected to the. The output terminal Q of the D-FF5A2 is D
-Connected to the data input terminal D of FF5A3. D
The output terminal Q of -FF5A3 is connected to the data input terminal D of D-FF5A4. The output terminal Q of the D-FF 5A4 is connected to the data input terminal D of the D-FF 5A5. The output terminal Q of the D-FF5A5 is the D-FF5A
6 data input terminals D. D-FF5A
The output terminal Q of 6 is the data input terminal D of D-FF5A7.
It is connected to the. The output terminal Q of the D-FF5A7 is D
-It is connected to the data input terminal D of FF5A8. D
The output terminal Q of the -FF5A8 is connected to the first input terminal of the 2-input NOR circuit 5D. In addition, D-FF5A1
5A8, the shift register 5A is configured to count the number of pulses of the detection clock DETCK while the reference clock Rin is "H".

Similarly, the data input terminal D of the D-FF 5B1 and each set input terminal PR of the D-FFs 5B1 to 5B8.
N is connected to the power supply potential Vcc. D-FF5B
The output terminal Q of 1 is the data input terminal D of the D-FF5B2.
It is connected to the. The output terminal Q of the D-FF5B2 is D
-Connected to the data input terminal D of FF5B3. D
The output terminal Q of -FF5B3 is connected to the data input terminal D of D-FF5B4. The output terminal Q of the D-FF 5B4 is connected to the data input terminal D of the D-FF 5B5. The output terminal Q of the D-FF5B5 is the D-FF5B
6 data input terminals D. D-FF5B
The output terminal Q of 6 is the data input terminal D of D-FF5B7.
It is connected to the. The output terminal Q of the D-FF5B7 is D
-Connected to the data input terminal D of FF5B8. D
The output terminal Q of the -FF5B8 is connected to the second input terminal of the NOR circuit 5D. In addition, D-FF5B1-5B
8 and the inverter 5C, the reference clock Rin is "L"
The shift register 5B is configured to count the number of pulses of the detection clock DETCK during the period. NOR circuit 5
The output terminal of D is connected to the output terminal DRST.

FIG. 6 is a time chart for explaining the operation of FIG. 1, in which the vertical axis represents the logic level and the horizontal axis represents time. The operation of FIG. 1 will be described with reference to FIG. In the period T1, as in the case of FIG.
The -FF is set based on the rising edge of the reference clock Rin, and is reset based on the rising edge of the feedback clock S4 that is delayed from the phase of the reference clock Rin to generate advance information S1u. In the period TA, the missing clock detection circuit 5 determines that the reference clock R
The number of pulses of the detection clock DETCK having a frequency higher than that of the reference clock Rin is counted while in is “H”, and the counted number is “H” of the reference clock Rin.
When the count number (8 in this embodiment) set for a period longer than the steady-state period is reached, that is,
When a missing tooth Tb occurs in the reference clock Rin,
The output signal S5 of "L" is output.

The phase comparator 1 has a reset input terminal DRS.
When the output signal S5 is input from T, it returns to the initial state,
Lead information S1u is “L” and delay information S1d is “H”
State. The frequency fh (H of the detection clock DETCK
Z) and the frequency fR (HZ) of the reference clock Rin, fh
= M · fR (m is generally selected from 8 to 16, but need not be an integer.) If the count number n of the detection clock DETCK is set as m / 2 <n <m Good. In the period T2, when the reference clock Rin transits from "H" to "L", the output signal S5 becomes "H", and the SR-FF is set again based on the rising edge of the reference clock Rin as in the period T1. Then
The advance information S1u is generated by resetting based on the rising edge of the feedback clock S4 which is delayed from the phase of the reference clock Rin. Then, the charge pump 2 inputs the advance information S1u, converts it into a DC voltage level, and outputs an output signal S2. The loop filter 3 removes a high frequency component included in the output signal S2 and outputs a DC voltage output signal S3. The VCO 4 outputs the feedback clock S4 which is an output signal having a frequency based on the output signal S3 from the loop filter 3.

As described above, in this embodiment, the period TA
When the missing tooth TB occurs in the reference clock Rin, the missing tooth clock detection circuit 5 outputs the output signal S of "L".
5 is output. The phase comparator 1 has a reset input terminal DR
The output signal S5 of "L" is input from ST to return to the initial state, and the advance information S1u becomes "L" and the delay information S1d becomes "H". Therefore, in the period T2, even if the reference clock Rin changes from “H” to “L”, the phase comparator 1 operates normally without malfunctioning.
The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the following modifications.

(A) In the embodiment, the reference clock Ri
Although the example in which tooth loss TB occurs during the period when n is “H” has been described, the present invention is similarly applied even when the tooth loss occurs during the period when the reference clock Rin is “L”. (B) The present invention provides a high-speed clock (a (Hz)) that may be used in a digital transmission device, and a low-speed clock (b (Hz)) that is slower than the high-speed clock (a and b).
Requires a relationship of a = n · b to be established, where n is an integer) and only the high-speed clock component is extracted from the multiplexed signal, and the PLL circuit is synchronized with the high-speed clock. It is possible to let

[0016]

As described above in detail, according to the present invention, when the phase of the feedback clock lags behind the phase of the reference clock, it is set based on the edge of the reference clock and the edge of the feedback clock is set. When the phase of the feedback clock is ahead of the phase of the reference clock, the lead information is generated by resetting the feedback clock based on the edge of the feedback clock, and reset based on the edge of the reference clock. When a phase comparison circuit having a set / reset type flip-flop that generates delay information is used, the phase comparison circuit is reset even if a missing clock (ie, disconnection) occurs in the reference clock. Since the missing tooth clock detection circuit for returning to the initial state is provided, it is possible to prevent the phase comparison circuit from malfunctioning. Further, by providing this missing tooth clock detection circuit, the PLL circuit using the phase comparison circuit can operate stably without being disturbed by missing teeth of the reference clock.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a phase comparator according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional PLL circuit.

FIG. 3 is a circuit diagram of the phase comparator in FIG.

FIG. 4 is a time chart of FIG. 3;

5 is a circuit diagram of a missing tooth clock detection circuit in FIG.

FIG. 6 is a time chart of FIG. 1;

[Explanation of symbols]

1 phase comparison circuit 2 charge pump 3 loop filter 4 voltage controlled oscillator 5 missing clock detection circuit 1e, 1h NOR circuit

Claims (1)

[Claims] 1. When the phase of the feedback clock is behind the phase of the reference clock, the advance information is generated by setting based on the edge of the reference clock and resetting based on the edge of the feedback clock. A set / reset flip-flop that generates delay information by setting based on the edge of the feedback clock and resetting based on the edge of the reference clock when the phase of the feedback clock leads the phase of the reference clock. A phase comparison circuit having: a charge pump that inputs the advance information or the delay information and outputs a DC voltage corresponding to the advance information or the delay information; and a high frequency component included in the output signal of the charge pump. And a feedback clock having a frequency corresponding to the output signal of the filter A phase-locked loop circuit including a voltage-controlled oscillator that counts the number of pulses of a detection clock having a frequency higher than that of the reference clock during a period when the reference clock is at a high level, and the count number is higher than that of the reference clock. When the count number set corresponding to a period longer than the steady-state period of the level is reached or the reference clock is at a low level period, the pulses of the detection clock are counted, and the count number is the reference number. The set / reset type flip-flop is fixed to the reset state when the count number set for a period longer than the steady state of the low level of the clock is reached, and then the level of the reference clock transits. A phase-locked loop circuit, characterized in that a missing tooth clock detection circuit for releasing the reset state is provided.