JPH0954698A - Data processing device and interrupt processing method thereof - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To shorten the response period to an interrupt requested immediately after an exception event occurs. A micro sequencer (14a) that evaluates during execution of a micro program whether or not an interrupt generated during execution of the micro program for obtaining information necessary for execution of a processing program for an exceptional event is permitted. If, as a result of the evaluation of the microsequencer 14a, the interrupt is permitted, the microprogram of the exception event branches to the interrupt processing program, and also works together with the microsequencer 14a to end the execution of the processing program at the branch destination. After that, the instruction execution unit 16 for returning to the branch source is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device such as a microprocessor and a microcontroller and an interrupt processing method thereof, and more particularly to a data processing device having improved responsiveness to an interrupt request and an interrupt processing method thereof.

[0002]

2. Description of the Related Art A data processing device used for controlling equipment is required to have higher performance in accordance with the sophistication and complexity of control objects and the speeding up of control operations. In high performance, not only the calculation speed of the data processing device but also the speed of interrupt response are important factors.In particular, in real-time control, it is necessary to start the interrupt processing within a certain time from the interrupt request. In particular, there is a problem to speed up the interrupt response in the machine check interrupt which is urgent in its response and which is caused by the failure of the CPU, the memory and the like.

The interrupt response time is the processing time of the data processing device from the generation of the interrupt request to the activation of the interrupt processing program (interrupt handler). Usually, the evaluation of whether to accept an exceptional event including an interrupt is performed at the break of the instruction processed by the data processing device. Therefore, the interrupt response time is the time from the interrupt request until the data processor evaluates and accepts the exception event at the break of the instruction, and after the exception is accepted, the interrupted program context is saved in the stack and the interrupt handler It is classified into the time until the control information for processing is loaded and it jumps to the interrupt handler.

FIG. 8 is a block diagram of an example of a conventional data processing device. This data processor is a microprocessor that executes instructions under microprogram control. In the figure, reference numeral 11 denotes a bus interface, and the bus interface 11 exchanges signals with an external circuit. The bus interface 11 is provided with an interrupt acceptance unit 18 that accepts interrupt signals IRL0 to IRL2 input from the outside and generates interrupt level information described below from these three inputs and outputs it to the microsequencer 14b. The instruction fetch unit 12 uses the bus interface 11
From the inside to the inside or from the inside to the bus interface 11.

The instruction decoding unit 13 is an instruction fetch unit 12
Decodes the instruction fetched from the bus interface 11, and outputs the address and the like of the micro ROM 15 to the micro sequencer 14b and the operand data and the like to the instruction execution unit 16 among the decoded results. The micro sequencer 14b receives the decoding result of the instruction decoding unit 13 and generates an access address of the micro ROM 15 to access the micro ROM 15. Micro ROM 15
Outputs an instruction execution control signal from the address generated by the microsequencer 14b to the microsequencer 14b, the interrupt acceptance unit 18, or the instruction execution unit 16. The instruction execution unit 16 processes the operand information and the like output from the instruction decoding unit 13 based on the execution control signal given from the micro ROM 15. The instruction execution unit 16 includes a data path 17 having an arithmetic unit such as an ALU and a register file such as a working register. Reference numeral 18 denotes an interrupt acceptance unit that receives an interrupt signal input from the outside of the present data processing device, and is present in the bus interface 11.

The bus interface 11 controls the output of addresses to the address bus A, the input / output control of data to the data bus D, and the input / output control of a control signal group for system control and bus control. Here, as the system control signal, when the data is not correctly read / written, the bus error signal BERR input from the external circuit due to the time-out process and the three interrupt signals IRL0 input from the external circuit such as the interrupt controller. , I
RL1 and IRL2 are illustrated. The three interrupt signals are directly input to the interrupt accepting unit 18 in the bus interface 11. Interrupts have levels from 0 to 7, and the smaller the number, the higher the priority. Level 7 indicates no interrupt request, and level 0 indicates a non-maskable interrupt request (NMI) in which interrupts cannot be disabled.
If IRL0, IRL1, and IRL2 are [0, 0, 0], level 0; if [0, 0, 1], level 1, [1,
1, 1] indicates level 7.

FIG. 9 shows the microsequencer 14 shown in FIG.
It is a block diagram which shows the detailed structure of b. The next micro address register UNAR21 stores the start address of the micro program to be executed next, which is given from the instruction decoding unit 13 via the signal line 102. The jump destination micro address register UJAR23 stores a branch destination micro address given from the micro ROM 15 through the signal line 108 when branching is performed by a micro program. Micro stack register USTR2
Reference numeral 4 is a micro program, and stores a return micro address when the subroutine jumps. The micro address register UAR25 is a register for storing a micro address, which latches a micro address transmitted from the UNAR 21, an exception handling address generation circuit 22, which will be described later, UJAR 23 and USTR 24 via the micro address bus UABS, and also has an address increment function. To have. Micro sequencer 14b is UAB
The micro address loaded from S is sequentially fed to the signal line 103
To the micro ROM 15 via.

The exception determination circuit 26d is included in the instruction decoding unit 1
3, bus interface 11, interrupt acceptance unit 1
8. Signal lines 102 and 10 from the instruction execution unit 16 respectively
Whether or not an exception has occurred and its priority are determined from the exception occurrence information transmitted via 9, 110, and 111, and when an exception to be processed is detected, the detected exception is handled as an exception processing address generation circuit 22. Tell. The exception processing address generation circuit 22 generates the start micro address of the exception processing micro program of the corresponding exception and outputs it to the UABS.

Next, the operation of the conventional data processing apparatus will be described. First, the normal command processing will be described. The instruction fetch unit 12 manages the instruction fetch address and controls the instruction fetch request to the bus interface 11 based on the value of the program counter (PC) in the instruction execution unit 16. The instruction fetch request and the instruction fetch address are transmitted from the instruction fetch unit 12 to the bus interface 11 via the signal line 100. The instruction fetch address is output to the address bus A of the bus interface 11, and an instruction code is output to the data bus D from an external circuit such as a main memory or an external cache according to this address. The instruction code fetched by the bus interface 11 from the data bus D is sent to the instruction fetch unit 12 via the signal line 100, and sent to the instruction decode unit 13 via the signal line 101 to be decoded. Among the decoding results, the control information used for instruction execution such as the instruction execution micro ROM address is transmitted via the signal line 102 to the micro sequencer 1
4b, and operand information such as operand data, operand address for indirect reference, and register number used is sent to the instruction execution unit 16 via the signal line 105.

The micro sequencer 14b uses the micro ROM 1 based on the control information sent from the instruction decoding unit 13 and the like.
Read control from 5 is performed. Micro sequencer 14
The micro address output from b is sent to the micro ROM 15 via the signal line 103. Micro ROM 1
5 from the instruction execution unit 16, the micro sequencer 14b, or the interrupt acceptance unit 18 according to the micro address.
Control information is output to. The control signal for command execution is sent to the command execution unit 16 via the signal line 104. The instruction execution unit 16 processes the operand information received from the signal line 105 based on the control information received from the signal line 104. When the indirect reference of the operand is required, the operand address is transmitted to the bus interface 11 via the signal line 107, the bus interface 11 outputs the operand address to the address bus A, and the read bus cycle is activated. The data fetched from the external memory is taken into the bus interface 11 from the data bus D and transferred to the instruction execution unit 16 via the signal line 107.
Used for calculation.

When it is necessary to write the operand to the external memory, the operand address and the operand data are transmitted to the bus interface 11 via the signal line 107, and the bus interface 11 outputs the operand address to the address bus A and the data bus D, respectively. And the operand data are output, and the write bus cycle is activated to write the operand in the external memory.

In the microsequencer 14b, the UNAR2 signal is transmitted from the instruction decoding unit 13 via the signal line 102.
1 is loaded with the micro address for instruction processing, and UAB
The signal is transmitted to the UAR 25 via S and output from the signal line 103. While reading the micro ROM 15 from this address, the UAR 25 increments the micro address and the micro sequencer 14b
Every time reading from 5 is completed, the incremented micro address is output to the signal line 103. Less than,
Similarly, the micro addresses are sequentially incremented and the micro programs are sequentially executed.

Next, the exception processing will be described. Exceptions include traps that are software interrupts that are activated by trap instructions, reserved instruction exceptions that are detected when an instruction such as an undefined instruction or an illegal addressing mode is decoded, debug traps that are activated for debugging, external memory, etc. Instruction, a bus access exception that occurs when a timeout occurs in operand access, a zero division trap that occurs when division by zero is detected in the processing of an arithmetic instruction, an external interrupt requested by interrupt signals IRL0 to IRL2, and the like.

The trap instruction includes an unconditional trap instruction and a conditional trap instruction. The unconditional trap is detected by the instruction decoding unit 13 and the conditional trap is detected by the instruction execution unit 16, and the signal lines 102 and 111 are used respectively. The microsequencer 14b is informed. The reserved instruction exception is detected by the instruction decoding unit 13 and notified to the micro sequencer 14b via the signal line 102. The bus access exception is notified to the bus interface 11 by the bus error signal BERR, but the bus access exception accompanying the instruction fetch is transmitted to the micro sequencer 14b via the instruction fetch unit 12 and the instruction decoding unit 13 by the signal line 102, and the operand A bus access exception associated with fetch and operand write is sent from the instruction execution unit 16 to the signal line 111.
Is transmitted to the micro sequencer 14b via. The zero division trap is detected by the instruction execution unit 16 and detected by the signal line 111.
The microsequencer 14b is notified via the. The external interrupt is detected by the interrupt acceptance unit 18, and the interrupt level is transmitted via the signal line 110 to the microsequencer 1
4b is transmitted.

These exceptions are accepted and evaluated by the microsequencer 14b when the microsequencer 14b receives the signal on the signal line 108 output from the microROM 15 in the final step of instruction execution.

Exception processing is performed on the exception received here. Exception processing is performed by the micro sequencer 14b
From the signal line 10
It is activated by outputting the data to the micro ROM 15 via 3. FIG. 10 shows a processing flow of the exception processing microprogram.

First, the processor state word (PSW) at the time of executing the instruction that caused the exception is saved in the working register existing in the data path 17 of the instruction executing section 16 (S10).
1). Next, the vector number of the exception that occurred is calculated (S1
02), the PC value indicating the start address of the handler, which is the information necessary for transferring control to the exception handling handler existing in the external memory, and the address of the exception vector table in which the PSW at the time of handler execution is stored in advance. Obtain (S103). According to this address, the entry of the corresponding exception in the exception vector table is read from the external memory (S104), this information is compared with the PSW saved in the working register, and the contents of the PSW are updated (S1).
06). Next, the PC value, PSW, etc. before the exception occurs are saved in the stack arranged in the external memory (S107 / S10).
8), PC value indicating the start address of the exception handler is PC
And branch to the corresponding exception handler (S10).
9).

The exception processing operation will be described by taking a bus access exception at the time of instruction fetch as an example. The instruction fetch request from the instruction fetch unit 12 and the instruction fetch address are sent to the signal line 100.
Is transmitted to the bus interface 11 via. The instruction fetch address is output to the address bus A of the bus interface 11 to access the external memory. If a timeout error occurs during this access,
The BERR signal is sent back to the bus interface 11. This bus error information is sent to the instruction fetch unit 12 via the signal line 100, sent to the instruction decode unit 13 via the signal line 101, and further sent to the micro sequencer 14b via the signal line 102. Due to the completion of the preceding instruction processing, the exception judgment circuit 2 of the microsequencer 14b
The exception is evaluated in 6d and the bus access exception is accepted. This information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 sets the start address of the microprogram for bus access exception processing to UAB.
Output from S. This micro address is latched by the UAR 25 and is sent to the micro ROM 15 via the signal line 103.
Is output to The micro ROM 15 sequentially outputs control signals to the micro instruction executing section 16 from the entry for bus access exception processing.

The instruction execution unit 16 saves the PSW at the time of execution of the instruction sequence causing the bus error in the working register in response to the control signal from the microprogram for bus access exception processing sequentially output from the micro ROM 15, and the bus access exception is generated. Is generated to calculate the entry address of the bus access exception in the exception vector table of the external memory, and the first P of the handler for the bus access exception stored in that address is stored in advance.
The C value and the PSW value at the time of executing the handler are read through the bus interface 11, and the PSW at the time of executing the instruction sequence causing the bus error in the working register is executed.
Interrupt mask value and P when the loaded handler is executed
The value of PSW is updated by comparing with the interrupt mask value of SW and adopting the interrupt mask value of high priority.

The instruction execution unit 16 uses the PC value of the instruction in which the bus error has occurred, the PC value of the instruction following this instruction, and the data indicating the state at the time of the bus error, such as the value of PSW in the working register, to the bus interface. It is pushed to the stack in the external memory via 11, the PC value at the head of the handler for bus access exception processing is set in PC, and the instruction fetch unit 12 is instructed to start fetching. As a result, the bus access exception handling microprogram for activating the exception handling handler ends.
Interrupt evaluation is not performed during execution of this exception handling microprogram. Thereafter, the instruction fetch request from the instruction fetch unit 12 sequentially reads out and executes the bus access exception handler program. The interrupt is evaluated at the first instruction break after the processing is transferred to the handler.

[0021]

FIG. 11 is a timing chart showing the acceptance timing of an interrupt request at the time of exception processing of the conventional data processing apparatus as described above. As is apparent from the figure, in a conventional microprogram-controlled data processing device that makes an exception acceptance decision only at an instruction break, an exception is accepted at an instruction break, and a microprogram for exception processing is activated. Since the microprogram is executed without interruption due to the automatic increment of the address and the address, the interrupt that occurs during this time is evaluated and the interrupt request is accepted because the exception handler that jumps after the execution of the exception processing microprogram is completed. The time point is the last step of the first instruction processing of.

Therefore, as shown in FIG. 11, when an interrupt request is generated immediately after the exception is accepted, the time from the generation of the request to the evaluation of whether or not to accept the interrupt request, that is, the interrupt response time is lengthened. It may take several tens of times the microprogram execution time for one step. In particular, prolonging the response period for an interrupt request having a high priority places a great constraint on the construction of a real-time system.

The present invention has been made in order to solve such a problem, and it may be generated during the execution of a microprogram for saving the PSW and PC in response to the occurrence of an exceptional event including an interrupt. Evaluate whether or not the interrupt is a permitted interrupt during execution of the microprogram, and if it is a permitted interrupt, execute its processing program prior to the processing program of the exception event that occurred earlier. Accordingly, it is an object of the present invention to provide a data processing device having a short response period for an interrupt requested immediately after an exception event occurs, and an interrupt processing method thereof.

[0024]

A data processing device according to a first aspect of the present invention and an interrupt processing method according to a fifth aspect of the present invention provide an exception event processing program before executing an exception event processing program that occurs during execution of data processing. During execution of a microprogram that includes a procedure for saving information used for execution of data processing that is returned from and restarting, and a procedure for reading information used for execution of the processing program together with the storage address of the processing program, that is, an exceptional event Is evaluated during the execution of the microprogram to determine whether or not the interrupt generated immediately after the processing of is accepted is permitted.

The data processing apparatus according to the first aspect of the invention and the interrupt processing method according to the fifth aspect of the invention are data that are executed before executing the processing program for an exceptional event that occurred during the execution of data processing, and that are restored from the processing program and restarted. Whether the interrupt occurred during the execution of the microprogram that includes the procedure for saving the information used for executing the process and the procedure for reading the information used for executing the processing program together with the storage address of the processing program is enabled or not. Is evaluated during execution of the micro program, and if interrupts are enabled, the exception event micro program branches to the interrupt processing program, and after the execution of the processing program at the branch destination ends, the branch source returns. To do. As a result, the response period for the interrupt requested immediately after the processing for the exception event is accepted is shortened.

A data processing device according to the second and third inventions,
In addition to the first invention, the interrupt processing method of the sixth invention and the seventh invention ends the execution of the exception event or the previous interrupt processing program when branching from the exception event microprogram to the interrupt processing program. The first information indicating whether or not the exception event is stored in the first register provided for each type of exception event or each interrupt priority level, and the exception event is generated by returning from the processing program of the interrupt at the branch destination. Alternatively, the second information used when resuming the execution of the previous interrupt processing program is stored in the second register,
Alternatively, when the exception event is an interrupt, the exception event is stored in the corresponding register of the second register provided for each interrupt priority level.

As a result, the interrupt processing or the exception processing that should be processed before returning to the normal data processing because the processing is not completed by another interrupt is promptly restarted after the processing of the other interrupt is completed, The response period for interrupts is shortened.

In the data processing device of the fourth invention and the interrupt processing method of the eighth invention, it is highly likely that other interrupts must be processed preferentially among the priority levels of the interrupts. Only in the case of interrupts with a limited predetermined priority level, such as low interrupts, whether or not an interrupt generated during the execution of the microprogram is enabled during the execution of the microprogram is evaluated, and the interrupt of the previous interrupt is evaluated. First information indicating whether or not the execution of the processing program is completed is stored in a corresponding register of the first registers provided for each limited predetermined priority level, and an interrupt processing program for the branch destination is stored. Second information, which is used when returning from the above and restarting the execution of the previous interrupt processing program, is provided for each predetermined priority level. And storing, in the second register corresponding register.

As a result, when there is another interrupt, it is considered that there are many cases where the processing should be prioritized. Therefore, other interrupts can be promptly issued only when the interrupt has a limited priority level such as a relatively low priority level. In addition, the interrupt processing to be processed before returning to the normal data processing is promptly restarted, and the response period to the interrupt is shortened with a small number of parts.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram of an example of a data processing apparatus of the present invention. In the figure, reference numeral 11 denotes a bus interface, and the bus interface 11 exchanges signals with an external circuit. The bus interface 11 is
A micro sequencer 14a that receives interrupt signals IRL0 to 2 inputted from the outside, generates interrupt level information described later from these three inputs, and constitutes the branching means together with the judging means and the instruction executing section 16 described later.
And an interrupt acceptance unit 18 for outputting to. The instruction fetch unit 12 fetches an instruction from the bus interface 11 to the inside or from the inside to the bus interface 11.

The instruction decoding unit 13 is an instruction fetch unit 12
Decodes the instruction fetched from the bus interface 11, and outputs the address and the like of the micro ROM 15 to the micro sequencer 14a and the operand data and the like to the instruction execution unit 16 among the decoded results. The micro sequencer 14a receives the decoding result of the instruction decoding unit 13 and generates an access address of the micro ROM 15 to access the micro ROM 15. Micro ROM 15
Outputs an instruction execution control signal from the address generated by the microsequencer 14a to the microsequencer 14a, the interrupt acceptance section 18, or the instruction execution section 16. The instruction execution unit 16 processes the operand information and the like output from the instruction decoding unit 13 based on the execution control signal given from the micro ROM 15. The instruction execution unit 16 includes a data path 17 having an arithmetic unit such as an ALU and a register file such as a working register. Reference numeral 18 denotes an interrupt acceptance unit that receives an interrupt signal input from the outside of the present data processing device, and is present in the bus interface 11.

The bus interface 11 controls the output of an address to the address bus A, the input / output control of data to the data bus D, and the input / output control of a control signal group for system control and bus control. Here, as the system control signal, when the data is not correctly read / written, the bus error signal BERR input from the external circuit due to the time-out process and the three interrupt signals IRL0 input from the external circuit such as the interrupt controller. , I
RL1 and IRL2 are illustrated. The three interrupt signals are directly input to the interrupt accepting unit 18 in the bus interface 11. Interrupts have levels from 0 to 7, and the smaller the number, the higher the priority. Level 7 indicates no interrupt request, and level 0 indicates a non-maskable interrupt request (NMI) in which interrupts cannot be disabled.
If IRL0, IRL1, and IRL2 are [0, 0, 0], level 0; if [0, 0, 1], level 1, [1,
1, 1] indicates level 7.

FIG. 2A is a block diagram showing the configuration of the microsequencer 14a shown in FIG. 1, and FIG. 2B is a block diagram showing the configuration of the instruction execution unit 16. Next micro address register UNA
R21 stores the start address of the microprogram to be executed next, which is given from the instruction decoding unit 13 via the signal line 102. The jump destination micro address register UJAR23 stores a branch destination micro address given from the micro ROM 15 through the signal line 108 when branching is performed by a micro program. The micro stack register USTR24 stores the return destination micro address when the subroutine jumps in the micro program. Micro address register UA
R25 is a register for storing a micro address, which is UN
AR21, exception processing address generation circuit 22 described later, UJ
The micro address transmitted from the AR 23 and the USTR 24 via the micro address bus UABS is latched and also has an address increment function. The micro sequencer 14a sequentially receives the micro address loaded from the UABS via the signal line 103 to the micro RO.
Output to M15.

The exception judging circuit 26a is the instruction decoding unit 1
3, bus interface 11, interrupt acceptance unit 1
8. Signal lines 102 and 10 from the instruction execution unit 16 respectively
Whether or not an exception has occurred and its priority are determined from the exception occurrence information transmitted via 9, 110, and 111, and when an exception to be processed is detected, the detected exception is handled as an exception processing address generation circuit 22. Tell. The exception processing address generation circuit 22 generates the start micro address of the exception processing micro program of the corresponding exception and outputs it to the UABS.

Further, the exception judgment circuit 26a is connected to the signal line 10
It has a plurality of flag registers 27, which are connected to Nos. 2, 109, and 111 and which indicate with flags whether or not there is an exception process to be processed after returning from the interrupt processing program and before returning to a normal instruction fetch. Reserved register exception R, bus error B, and unconditional trap T flag register are connected to the signal line 102, bus error B flag register is connected to the signal line 109, and division by zero Z and condition are connected to the signal line 111. The flag registers of the trap T are connected to each other. The type of the flag register 27 is not limited to this,
A flag register corresponding to another exception handled by the data processing device may be connected. As shown in FIG. 2 (b), the instruction execution unit 16 holds data such as PC value and PSW value which are in the middle of exception processing, that is, data required when returning to the exception processing after the interruption processing. Register 28 for
Are connected to the signal line 107.

Next, the operation of the first embodiment of the data processing apparatus of the present invention will be described. First, the normal command processing will be described. Based on the PC value in the instruction execution unit 16, the instruction fetch unit 12 manages the instruction fetch address and controls the instruction fetch request to the bus interface 11. The instruction fetch request and the instruction fetch address are transmitted from the instruction fetch unit 12 to the bus interface 11 via the signal line 100. The instruction fetch address is output to the address bus A of the bus interface 11, and an instruction code is output to the data bus D from an external circuit such as a main memory or an external cache according to this address. The instruction code fetched by the bus interface 11 from the data bus D is sent to the instruction fetch unit 12 via the signal line 100, and sent to the instruction decode unit 13 via the signal line 101 to be decoded. Among the decoding results, the control information used for executing the instruction such as the instruction executing micro ROM address is transmitted via the signal line 102 to the micro sequencer 14a.
And the operand information such as operand data, operand address of indirect reference, and register number used is sent to the instruction execution unit 16 via the signal line 105.

The micro sequencer 14a uses the micro ROM 1 based on the control information sent from the instruction decoding unit 13 or the like.
Read control from 5 is performed. Micro sequencer 14
The micro address output from a is sent to the micro ROM 15 via the signal line 103. Micro ROM 1
5 from the instruction execution unit 16, the micro sequencer 14a, or the interrupt acceptance unit 18 according to the micro address.
Control information is output to. The control signal for command execution is sent to the command execution unit 16 via the signal line 104. The instruction execution unit 16 processes the operand information received from the signal line 105 based on the control information received from the signal line 104. When the indirect reference of the operand is required, the operand address is transmitted to the bus interface 11 via the signal line 107, the bus interface 11 outputs the operand address to the address bus A, and the read bus cycle is activated. The data fetched from the external memory is taken into the bus interface 11 from the data bus D and transferred to the instruction execution unit 16 via the signal line 107.
Used for calculation.

When it is necessary to write the operand to the external memory, the operand address and the operand data are transmitted to the bus interface 11 via the signal line 107, and the bus interface 11 outputs the operand address to the address bus A and the data bus D, respectively. And the operand data are output, and the write bus cycle is activated to write the operand in the external memory.

In the microsequencer 14a, the UNAR2 signal is transmitted from the instruction decoding unit 13 via the signal line 102.
1 is loaded with the micro address for instruction processing, and UAB
The signal is transmitted to the UAR 25 via S and output from the signal line 103. While reading from this address of the micro ROM 15, the UAR 25 increments the micro address and the micro sequencer 14a
Every time reading from 5 is completed, the incremented micro address is output to the signal line 103. Less than,
Similarly, the micro addresses are sequentially incremented and the micro programs are sequentially executed.

Next, the exception processing will be described. Exceptions include traps that are software interrupts that are activated by trap instructions, reserved instruction exceptions that are detected when an instruction such as an undefined instruction or an illegal addressing mode is decoded, debug traps that are activated for debugging, external memory, etc. Instruction, a bus access exception that occurs when a timeout occurs in operand access, a zero division trap that occurs when division by zero is detected in the processing of an arithmetic instruction, an external interrupt requested by interrupt signals IRL0 to IRL2, and the like.

The trap instruction includes an unconditional trap instruction and a conditional trap instruction. The unconditional trap is detected by the instruction decoding unit 13 and the conditional trap is detected by the instruction execution unit 16, and the signal lines 102 and 111 are used respectively. The microsequencer 14a is informed. The reserved instruction exception is detected by the instruction decoding unit 13 and notified to the microsequencer 14a via the signal line 102. The bus access exception is notified to the bus interface 11 by the bus error signal BERR, but the bus access exception accompanying the instruction fetch is transmitted to the micro sequencer 14a through the instruction fetch unit 12 and the instruction decode unit 13 by the signal line 102, and the operand A bus access exception associated with fetch and operand write is sent from the instruction execution unit 16 to the signal line 111.
Is transmitted to the micro sequencer 14a via the. The zero division trap is detected by the instruction execution unit 16 and detected by the signal line 111.
The microsequencer 14a is notified via the. The external interrupt is detected by the interrupt acceptance unit 18, and the interrupt level is transmitted via the signal line 110 to the microsequencer 1
4a is transmitted.

These exceptions are accepted and evaluated by the microsequencer 14a when the microsequencer 14a receives the signal on the signal line 108 output from the microROM 15 in the final step of instruction execution. Exception processing is performed on the exception accepted here. The exception processing is activated by outputting a specific exception processing micro address from the micro sequencer 14 a to the micro ROM 15 via the signal line 103. FIG. 5 shows a processing flow of the exception processing microprogram.

The exception processing operation of the present embodiment will be described by taking as an example the case where a level 0 interrupt occurs immediately after the bus access exception is accepted at the time of instruction fetch. The instruction fetch request and the instruction fetch address are transmitted from the instruction fetch unit 12 to the bus interface 11 via the signal line 100. The instruction fetch address is the bus interface 1
1 is output to the address bus A to access the external memory. When a time-out error occurs in this access, the BERR signal is returned to the bus interface 11. This bus error information is sent to the instruction fetch unit 12 via the signal line 100, sent to the instruction decode unit 13 via the signal line 101, and further sent to the micro sequencer 14a via the signal line 102. Upon completion of the instruction processing preceding the occurrence of the bus error, the exception determination circuit 26a of the microsequencer 14a evaluates the exception and accepts the bus access exception. This information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 outputs the start address of the microprogram for bus access exception processing from the UABS. This micro address is latched by the UAR 25 and output to the micro ROM 15 via the signal line 103. Micro RO
At M15, a control signal is sequentially output from the entry for bus access exception processing to the microinstruction executing unit 16.

The instruction execution unit 16 saves the PSW at the time of executing the instruction sequence causing the bus error in the working register according to the control signal from the bus access exception processing microprogram sequentially output from the micro ROM 15 (S1). At this time, IRL0, IRL1, IR
Assuming that an interrupt signal of [0, 0, 0] is input to L2, this signal is transmitted from the interrupt acceptance unit 18 to the signal line 1
It is sent to the micro sequencer 14a via 10. The instruction execution unit 16 generates a bus access exception vector (S
2) The entry address of the bus access exception handling handler in the exception vector table of the external memory is calculated (S3), and the top PC value of the bus access exception handling handler stored in advance at that address is stored. The value of PSW when the handler is executed is set to the bus interface 11
Read through (S4), P in the working register
The interrupt mask value of SW is compared with the interrupt mask value of PSW when the loaded handler is executed (S5), and the interrupt mask value of the higher level is used by the microsequencer 1
4a. The micro-sequencer 14a re-evaluates the interrupt (S6), detects that the interrupt level given from the signal line 110, that is, level 0, is a valid interrupt in which the interrupt is permitted, and shifts the processing to the interrupt. Of the flag registers 27 of the determination circuit 26a, a flag is set in the flag register (B) corresponding to the bus access exception currently being executed, and an exception process to be processed after the interrupt process is completed and before returning to the normal instruction fetch. Information that was obtained during processing of the bus access exception microprogram, that is, the interrupt mask value with a higher priority as a result of comparison before interrupt re-evaluation, the address when the interrupt occurred, and the address of the instruction that follows. That is, the return address from the interrupt processing and the interrupt generation data are stored in the register 28 of the instruction execution unit 16. To hold.

Here, the interrupt is accepted, this information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 outputs the start address of the microprogram for bus access exception processing from the UABS. This micro address is latched by UAR25,
It is output to the micro ROM 15 via the signal line 103. In the micro-ROM 15, the micro-instruction execution unit 1 sequentially outputs control signals from the entry for bus access exception processing.
6 is output. That is, the exception processing microprogram is re-executed to obtain the entry address of the handler for interrupt processing, the PSW value at the time of handler execution, and the like. The instruction execution unit 16 saves the PSW at the time of executing the instruction sequence that generated the interrupt in the working register existing in the data path 17 (S1). Instruction execution unit 16
Generates an interrupt vector or reads it from the data bus D via the bus interface 11 (S2), calculates the entry address of the interrupt in the interrupt vector table of the external memory (S3), and stores it in advance at that address. The PC value at the beginning of the handler for interrupt processing and the value of PSW at the time of handler execution are read via the bus interface 11 (S4), and the interrupt mask value of PSW in the working register is read.
The interrupt mask value of PSW at the time of executing the handler for interrupt processing is compared (S5). Here, it is reevaluated again whether or not there is an interrupt (S6). In this case, since the level of the first interrupt is 0, no other interrupts are enabled and no valid interrupts exist. Therefore, the interrupt mask value with a high priority is used as a result of comparison before interrupt reevaluation. , P when the handler for interrupt processing is executed
The SW value is updated (S7), and the PC value indicating the start address of the bus error exception handler and the PSW value in the working register are saved in the stack in the external memory via the bus interface 11 (S8, S9). , Set the PC value at the beginning of the handler for interrupt processing to PC,
The instruction fetch unit 12 is instructed to start fetching.
After that, the program of the interrupt handler is sequentially read and executed by the instruction fetch request of the instruction fetch unit 12 (S10).

When the interrupt processing is completed, data such as PSW and PC are popped from the stack, and the flag register 2
7, it is determined whether or not there is an exception process to be processed before returning to the normal instruction fetch. In the present embodiment, the handler of the bus error exception is unprocessed, and therefore, it is held in the register 28. The contents of the PSW popped from the stack are updated with the existing PSW value, and other data held in the register 28 is saved in the stack. The PC value returned from the stack, that is, the start address of the handler for the bus access exception, is set in the PC to branch to the exception handler.

[Second Embodiment] The configuration of the data processing apparatus according to the present embodiment is the same as that of the first embodiment shown in FIGS. 1 and 2. Further, since the normal instruction processing is the same as that of the first embodiment, the description will be omitted. Next, the operation of the exception processing of the data processing apparatus according to the present embodiment will be described by taking as an example the case where a level 0 interrupt occurs immediately after the bus access exception is accepted at the time of instruction fetch. FIG. 6 shows a processing flow of the exception processing microprogram, and FIG. 7 shows a timing chart of interrupt request acceptance timing during exception processing.

The instruction fetch request and the instruction fetch address are transmitted from the instruction fetch unit 12 to the bus interface 11 via the signal line 100. The instruction fetch address is output to the address bus A of the bus interface 11 to access the external memory. When a time-out error occurs in this access, the BERR signal is returned to the bus interface 11. This bus error information is sent to the instruction fetch unit 12 via the signal line 100, to the instruction decode unit 13 via the signal line 101, and further via the signal line 102.
4a. Upon completion of the preceding instruction processing, the exception determination circuit 26a of the microsequencer 14a evaluates the exception and accepts the bus access exception. This information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 outputs the start address of the microprogram for bus access exception processing from the UABS. This micro address is latched by UAR25,
It is output to the micro ROM 15 via the signal line 103. In the micro-ROM 15, the micro-instruction execution unit 1 sequentially outputs control signals from the entry for bus access exception processing.
6 is output.

The instruction execution unit 16 saves the PSW at the time of executing the instruction sequence causing the bus error in the working register according to the control signal from the bus access exception processing microprogram sequentially output from the micro ROM 15 (S21). At this time, IRL0, IRL1, I
If an interrupt signal of [0,0,0] is input to RL2, this signal is sent from the interrupt accepting unit 18 to the microsequencer 14a via the signal line 110.
The instruction execution unit 16 generates a bus access exception vector (S22), calculates the entry address of the bus access exception processing handler in the exception vector table of the external memory (S23), and stores the bus stored in advance at that address. The top PC value of the handler for access exception handling and the PSW value at the time of handler execution are read via the bus interface 11 (S24), the interrupt mask value of the PSW in the working register, and the read PSW at handler execution time. The interrupt mask value of (S2
5) The interrupt mask value with the higher level is output to the microsequencer 14a. Micro sequencer 14a
Re-evaluates the interrupt (S26), detects that the interrupt level given from the signal line 110, that is, level 0, is a valid interrupt in which the interrupt is permitted, and shifts the processing to the interrupt, but the exception determination circuit 26a Among the flag registers 27, the flag register (B) corresponding to the bus access exception currently being executed is flagged, and there is an exception process to be processed after the interrupt process is completed and before returning to the normal instruction fetch. The information obtained during the processing of the bus access exception microprogram, that is, the interrupt mask value with a high priority based on the result of comparison before interrupt re-evaluation and the address at the time of the interrupt, the address of the instruction following that, that is, the interrupt The return address from the process and the interrupt generation data are held in the register 28 of the instruction execution unit 16.

Although an interrupt is accepted here, in the present embodiment, the exception-handling microprogram is not re-executed, but a jump is made to the vector generation step (S2).
2), the entry address of the handler for interrupt processing,
Get the value of PSW when the handler is executed. Instruction execution unit 16
Generates an interrupt vector or reads it from the data bus D via the bus interface 11 (S22),
The entry address of the interrupt in the exception vector table of the external memory is calculated (S23), and the start PC value of the handler for interrupt processing and the PSW value at the time of handler execution stored in advance at that address are calculated by the bus interface 11 (S24), and the PSW interrupt mask value in the working register is compared with the read PSW interrupt mask value at the time of executing the handler for interrupt processing (S25). Here, it is reevaluated again whether or not there is an interrupt (S26). In this case, since the level of the first interrupt is 0, no other interrupts are enabled and no valid interrupts exist. Therefore, the interrupt mask value with a high priority is used as a result of comparison before interrupt reevaluation. , The PSW value at the time of executing the handler for interrupt processing is updated (S27), and the PC value indicating the start address of the bus error exception handler and the PSW value in the working register are set to the bus interface 1
1 to save to the stack in the external memory (S28,
S29), P at the head of the handler for interrupt processing is sent to the PC
The C value is set, and the instruction fetch unit 12 is instructed to start fetching. Thereafter, the program of the interrupt handler is sequentially read and executed by the instruction fetch request of the instruction fetch unit 12 (S30).

When the interrupt processing is completed, data such as PSW and PC are popped from the stack, and the flag register 2
7, it is determined whether or not there is an exception process to be processed before returning to the normal instruction fetch. In the present embodiment, the handler of the bus error exception is unprocessed, and therefore, it is held in the register 28. The contents of the PSW popped from the stack are updated with the existing PSW value, and other data held in the register 28 is saved in the stack. The PC value returned from the stack, that is, the start address of the handler for the bus access exception, is set in the PC to branch to the exception handler.

As described above, in the present embodiment, the flag register 27 and the register 28 are provided so that the data processed at the time of exception acceptance can be held, and immediately after the completion of the interrupt handling accepted later, the data is processed first. Exception handling of can be continued.

[Third Embodiment] FIG. 3 shows the configuration of a micro sequencer 14a (FIG. 3 (a)) and an instruction execution unit 16 (FIG. 3 (b)) according to a third embodiment of the data processing apparatus of the present invention. It is a block diagram shown. The rest of the configuration is similar to that of the first embodiment shown in FIG.

As shown in FIG. 3A, the exception judgment circuit 26b of this embodiment determines whether or not there is an interrupt process to be processed after returning from the interrupt processing program and before returning to the normal instruction fetch. A plurality of flag registers 29 for each level, which are indicated by flags, are connected to the signal line 110.
Further, as shown in FIG. 3B, the instruction executing unit 16 of the present embodiment terminates the data during the first interrupt processing such as the PC value and the PSW value, that is, the subsequent interrupt processing. A plurality of registers 30 for each level for holding data required when returning to the previous interrupt processing are connected to the signal line 107. In this embodiment, the register 3 is classified by level.
The reason why 0 is provided is to make it possible to handle multiple interrupts. Further, it is not necessary to provide the level 0 flag register 29 and the register 30 because no level interrupt is permitted with respect to the level 0 interrupt.

Since the ordinary instruction processing is the same as that of the first embodiment, the description thereof is omitted, and only the interrupt processing will be described below by taking the interrupts of level 6 and level 4 as an example.

IRL0, IRL1 and IRL2 are [1,
The level 6 interrupt signal of [1, 0] is transmitted to the interrupt acceptance unit 18 in the bus interface 11. This interrupt information is sent to the micro sequencer 14a via the signal line 110. When the microsequencer 14a receives the signal on the signal line 108 indicating the end of the preceding instruction processing, the exception judgment circuit 26 of the microsequencer 14a.
The exception is evaluated in b and the level 6 interrupt is accepted. This information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 sets the start address of the microprogram for level 6 interrupt processing to UA.
Output from BS. This micro address is UAR25
Latched by the micro ROM 1 via the signal line 103.
5 is output. The micro ROM 15 sequentially outputs control signals to the micro instruction executing section 16 from the level 6 interrupt processing entry.

The instruction execution unit 16 saves the PSW at the time of executing the instruction sequence that caused the interrupt in the working register in response to a control signal from the interrupt processing microprogram sequentially output from the micro ROM 15. At this time, IRL0, IRL1, and IRL2 are [1,
If an interrupt signal of [0, 0] is input, this signal is sent from the interrupt accepting unit 18 to the microsequencer 14a via the signal line 110. Instruction execution unit 16
Generates a vector for the first interrupt, calculates the entry address in the interrupt vector table of the external memory, and stores the PC value at the beginning of the handler for level 6 interrupt processing stored in advance at that address and the handler execution The PSW value at the time of reading is read through the bus interface 11, the PSW interrupt mask value in the working register is compared with the read PSW interrupt mask value at the time of executing the handler, and the interrupt mask value of the higher level is determined. Output to the micro sequencer 14a. The micro-sequencer 14a re-evaluates the interrupt, detects that the interrupt level given from the signal line 110, that is, level 4, is a valid interrupt having a higher level than the interrupt currently being executed, and processes the second interrupt. However, in the flag register 29 of the exception determination circuit 26b, a flag is set in the flag register 29 corresponding to the level 6 currently being executed, and after the interrupt processing is completed, the level to be processed before returning to the normal instruction fetch. 6 indicates that there is an interrupt process, and information obtained during the first interrupt process, that is, an interrupt mask value and a return address having a high priority as a result of comparison before interrupt re-evaluation, is executed by the instruction execution unit. It is held in 16 level 6 registers 30.

At this time, the second interrupt is accepted, and the instruction execution unit 16 generates a level 4 interrupt vector or reads it from the data bus D via the bus interface unit 11, and the entry address in the interrupt vector table of the external memory. Is calculated, and the PC value at the beginning of the handler for level 4 interrupt processing and the PSW value at the time of handler execution stored in that address are read through the bus interface 11, and the PSW interrupt in the working register is read. The mask value is compared with the read interrupt mask value of the PSW when the handler for interrupt processing is executed. Re-evaluate whether there is no interruption here. If there is no valid interrupt for which interrupts are permitted, the value of PSW at the time of execution of the handler for interrupt processing is updated by adopting the interrupt mask value of higher priority as a result of comparison before interrupt reevaluation. The start address of the interrupt handler of the first interrupt read from the interrupt vector table during the interrupt processing of P and the value of PSW in the working register are saved in the stack in the external memory via the bus interface 11, and P
The first PC value of the handler for the second interrupt processing is set in C, and the instruction fetch unit 12 is instructed to start fetching. After that, in response to an instruction fetch request from the instruction fetch unit 12, the interrupt handler program is sequentially read and executed.

When the second interrupt processing is completed, the data saved in the stack is popped and the flag register 2
9, it is determined whether there is an interrupt process to be processed before returning to the normal instruction fetch. In the present embodiment, since the handler of the first interrupt of level 6 is unprocessed, the value of PSW is updated using the data held in the register 30. PSW in working register
Then, the PC held in the register 30 is saved in the stack, the start address of the handler for the first interrupt processing returned from the stack is set in the PC, and the first interrupt processing is continued.

As described above, in the present embodiment, by providing the flag register 29 and the register 30, the first register is provided.
The processed data can be held at the time of accepting the interrupt, and the first interrupt process can be continued immediately after the end of the second interrupt process accepted later.

[Fourth Embodiment] FIG. 4 shows the configuration of a microsequencer 14a (FIG. 4 (a)) and an instruction execution unit 16 (FIG. 4 (b)) according to a fourth embodiment of the data processing apparatus of the present invention. It is a block diagram shown. The rest of the configuration is similar to that of the first embodiment shown in FIG.

In the present embodiment, the interrupt is re-evaluated only when the microprogram for interrupt processing of the limited specific level is executed, and the interrupt is re-evaluated when the microprogram for interrupt processing of a level other than the specific level is executed. Not performed. In the exception judgment circuit 26c of the present embodiment, as shown in FIG. 4 (a), after the interrupt processing program is completed, the presence or absence of interrupt processing to be processed before returning to the normal instruction fetch is flagged. A plurality of flag registers 31 for specific levels shown are connected to the signal line 110. In addition, in the instruction execution unit 16 of the present embodiment, as shown in FIG.
A plurality of registers 32 for each specific level for holding the data being processed by the interrupt, that is, the data required when returning to the first interrupt processing after the subsequent interrupt processing is connected to the signal line 107. Has been done. In this embodiment, the specific level is set to 4 or less, and flag registers 31 and 32 for level 4, level 5 and level 6 are provided respectively.

Since ordinary instruction processing is the same as that of the first embodiment, the description thereof will be omitted, and only the interrupt processing will be described below by taking interrupts of level 6, level 4 and level 2 as an example. Specific level is Level 4 as described above
The following is assumed.

IRL0, IRL1 and IRL2 are [1,
The level 6 interrupt signal of [1, 0] is transmitted to the interrupt acceptance unit 18 in the bus interface 11. This interrupt information is sent to the micro sequencer 14a via the signal line 110. When the microsequencer 14a receives the signal on the signal line 108 indicating the end of the instruction processing preceding the interrupt in the normal instruction fetch, the exception determination circuit 26c of the microsequencer 14a evaluates the interrupt and accepts the level 6 interrupt. To be This information is transmitted to the exception processing address generation circuit 22, and the exception processing address generation circuit 22 outputs the start address of the microprogram for level 6 interrupt processing from the UABS. This micro address is latched by the UAR 25 and output to the micro ROM 15 via the signal line 103. Control signals are sequentially output from the micro ROM 15 to the micro instruction executing section 16 from the entry for level 6 interrupt processing.

The instruction execution unit 16 saves the PSW at the time of executing the instruction sequence that caused the interrupt in the working register in response to a control signal from the interrupt processing microprogram sequentially output from the micro ROM 15. At this time, IRL0, IRL1, and IRL2 are [0,
If an interrupt signal of [1, 0] is input, this signal is sent from the interrupt receiving unit 18 to the microsequencer 14 a via the signal line 110. Instruction execution unit 16
Generates the first interrupt vector or reads it from the data bus D via the bus interface unit 11, calculates the entry address in the interrupt vector table of the external memory, and handles the level 6 interrupt processing stored in advance at that address. PC value at the beginning of the handler for
The value of PSW when the handler is executed is the bus interface 1
Read through 1 and the interrupt mask value of PSW in the working register and the PS when the read handler is executed
The interrupt mask value of W is compared, and the interrupt mask value of the higher level is output to the microsequencer 14a. Since the level of the first interrupt is 6, which is lower in priority than the specific level, the interrupt re-evaluation is performed by the microprogram for interrupt processing. Micro sequencer 14a
Detects that the interrupt level given from the signal line 110, that is, level 2 is a valid interrupt having a higher level than the interrupt currently being executed, and shifts the processing to the second interrupt. Flag register 31
Among them, a flag is set in the flag register 31 corresponding to the level 6 currently being executed to indicate that there is a level 6 interrupt process to be processed after the interrupt process is completed and before returning to the normal instruction fetch, The information obtained during the first interrupt processing, that is, the interrupt mask value and the return address having a high priority as a result of comparison before the interrupt reevaluation are held in the level 6 register 32 of the instruction execution unit 16.

At this time, the second interrupt is accepted, and the instruction execution unit 16 generates a vector of the level 2 interrupt or reads it from the data bus D via the bus interface unit 11, and enters the entry address in the interrupt vector table of the external memory. Is calculated, and the PC value at the beginning of the handler for interrupt processing of level 2 and the PSW value at the time of handler execution stored in that address are read through the bus interface 11, and the PSW interrupt in the working register is read. The mask value is compared with the read interrupt mask value of the PSW when the handler for interrupt processing is executed.

Here, further, IRL0, IRL1, IR
It is assumed that the third interrupt of level 1 with L2 of [0, 0, 1] is input. Since the second interrupt level is level 2 and is higher than a specific level, the interrupt re-evaluation is not performed in the interrupt processing microprogram. As a result of comparing PSW, the interrupt mask with high priority is adopted,
The PSW value is updated, and the PC value indicating the start address of the handler for the level 2 interrupt processing read from the interrupt vector table during the first interrupt processing and the PSW value in the working register are set to the bus interface 11
To the stack in the external memory via the
The leading PC value of the interrupt processing handler is set, and the instruction fetch unit 12 is instructed to start fetching. Thereafter, the program of the second interrupt handler is read and executed by the instruction fetch request of the instruction fetch unit 12.

At the break of the first instruction of the second interrupt handler, the third interrupt is evaluated, and the level 1 with high priority is evaluated.
The third interrupt is accepted because there is an interrupt of
The value of SW is saved in the working register. The third interrupt vector is generated or read from the data bus D via the bus interface 11, the entry address of the level 1 interrupt processing handler in the interrupt vector table of the external memory is calculated, and stored in advance at that address. The PC value at the beginning of the handler for the third interrupt processing and the PSW value at the time of handler execution are read via the bus interface 11, and the interrupt mask value of the PSW in the working register and the read PS
Compare with the interrupt mask value of W. As a result, the PSW is updated with the value of the PSW having the higher priority, the return destination PC and the PSW in the working register are saved in the stack in the external memory via the bus interface 11, and the third interrupt processing is performed by the PC. A PC value indicating the head of the handler for is set, and the instruction fetch unit 12 is instructed to start fetching. After that, in response to an instruction fetch request from the instruction fetch unit 12, the program of the third interrupt processing handler is sequentially read and executed.

When the third interrupt processing is completed, the PSW and the return destination PC value are returned from the stack, and the address is returned to the PC.
, And the second interrupt process is continued.

When the second interrupt process is completed, the PSW and PC values are returned from the stack, and the flag register 31 is referred to determine whether or not there is an interrupt process to be processed before returning to the normal instruction fetch. However, in this embodiment, since the handler of the first interrupt of level 6 is unprocessed, the PSW is used by using the data held in the register 32.
Update the value of and return from the stack to PSW and register 3
Push the PC held in 2 to the stack,
The start address of the first interrupt processing handler returned from the stack is set to and the first interrupt processing is performed.

As described above, in the present embodiment, the interrupt level at which the interrupt is re-evaluated during execution of the interrupt processing microprogram is limited, and the exception judgment circuit 26c
Flag register 31 for each limited specific interrupt level
Since only the register 32 for each specific interrupt level needs to be provided in the instruction execution unit 16, the number of hardware points is smaller than that in the third embodiment.

[0072]

The data processing device and the interrupt processing method of the present invention provide a PS for the occurrence of an exception event including an interrupt.
Evaluate during the execution of the microprogram whether other interrupts that occurred during the execution of the microprogram for saving W, PC, etc. are permitted interrupts, and if they are, the processing is performed. Since the program is executed prior to the exception event processing program that occurred earlier, the response period for the requested interrupt is shortened immediately after the processing for the exception event is accepted, which improves the responsiveness in real-time control. Produce an effect.

Further, the data processing device and the interrupt processing method of the present invention, which have not completed the processing due to other interrupts, and which have interrupt processing or exception processing to be processed before returning to the normal data processing, After the interrupt processing is completed,
Since the restart is promptly performed, the response period to the interrupt is shortened, and the excellent effect of improving the responsiveness in the real-time control is exerted.

Further, the data processing apparatus and the interrupt processing method of the present invention have a limited priority level such as a relatively low priority level in which it is considered that the processing should be prioritized when another interrupt occurs. Only for level interrupts, other interrupts are evaluated immediately, and the processing is not completed by other interrupts, so interrupt processing that should be processed before returning to normal data processing is restarted promptly, so it is less This has an excellent effect that the response period to the interrupt is shortened depending on the number of parts and the response in the real-time control is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a data processing device of the present invention.

FIG. 2 is a block diagram of a main part of the first and second embodiments of the data processing device of the present invention.

FIG. 3 is a block diagram of a main part of a third embodiment of a data processing device of the invention.

FIG. 4 is a block diagram of a main part of a fourth embodiment of a data processing device of the invention.

FIG. 5 is a flowchart of interrupt processing according to the first embodiment of the data processing apparatus of the present invention.

FIG. 6 is a flowchart of interrupt processing according to the second embodiment of the data processing apparatus of the present invention.

FIG. 7 is a timing chart of interrupt processing according to the second embodiment of the data processing apparatus of the present invention.

FIG. 8 is a block diagram of a conventional data processing device.

FIG. 9 is a block diagram of a main part of a conventional data processing device.

FIG. 10 is a flowchart of an interrupt process of a conventional data processing device.

FIG. 11 is a timing chart of interrupt processing of a conventional data processing device.

[Explanation of symbols]

11 bus interface, 12 instruction fetch section,
13 instruction decoding unit, 14a micro sequencer,
15 micro ROM, 16 instruction execution part, 17 data path, 21st micro address register (UNA
R), 22 exception processing address generation circuit, 23 jump destination micro address register (UJAR), 24 micro stack register (USTR), 25 micro address register (UAR), 26a, 26b, 26c
Exception judgment circuit, 27, 29, 31 flag register,
28, 30, 32 registers.

Claims (8)

[Claims] 1. A procedure for saving information used for executing the data processing, which is restored from the processing program and restarted, before the processing program for the exceptional event that occurs during the data processing is executed, and the processing. In a data processing device that executes a microprogram that includes a procedure for reading information used for executing the processing program together with the storage address of the program, it is determined whether or not an interrupt generated during execution of the microprogram is enabled. Evaluation means for evaluating during execution of the microprogram, branching means for branching from the exception event microprogram to the interrupt processing program if the interrupt is enabled as a result of the evaluation by the evaluation means, and branch destination After the execution of the processing program in A data processing device comprising: 2. A first register, which is provided for each type of exception event and holds first information indicating whether or not the execution of the exception event processing program is completed, and an interrupt processing program at the branch destination. A second register that holds second information used when returning and restarting the execution of the exception event processing program, and a first register and a first register when branching from the exception event microprogram to the interrupt processing program. The data processing device according to claim 1, further comprising means for storing the first information and the second information in the second register. 3. The exception event is an interrupt having a priority level for permitting the interrupt and is provided for each interrupt priority level, and indicates whether or not the execution of the interrupt processing program is completed. A first register that holds the first information and a second register that is provided for each interrupt priority level and that is used when returning from the branch target interrupt processing program and restarting the execution of the branch source interrupt processing program And a second register for holding information of the first interrupt, and first and second information are respectively stored in the first and second registers when branching from the first interrupt processing program to the second interrupt processing program. The data processing apparatus according to claim 1, further comprising: 4. The evaluation means determines whether or not an interrupt generated during execution of an interrupt processing program having a predetermined priority level among the interrupt priority levels is enabled. A first register, which is provided for each of the predetermined priority levels and holds first information indicating whether or not the execution of the interrupt processing program is completed, and the predetermined priority level. A second register, which is provided separately, holds second information used when returning from the interrupt target interrupt target program and restarting the execution of the branch source interrupt target program, and the predetermined priority level. When branching from the processing program for the first interrupt to the processing program for the second interrupt, the first and second registers are stored in the first and second registers. 2. The data processing device according to claim 1, further comprising means for storing each of the information in FIG. 5. A procedure for saving information used for executing the data processing, which is restored from the processing program and restarted, before executing the processing program for the exceptional event that occurred during the execution of the data processing, and the processing. In an interrupt processing method of a data processing device that executes a microprogram including a procedure for reading information used for executing the processing program together with a program storage address, is an interrupt generated during execution of the microprogram enabled? Whether or not the interrupt is permitted is evaluated during the execution of the microprogram, and the microprogram of the exception event branches to the interrupt processing program, and the execution of the processing program at the branch destination is completed. An interrupt processing method characterized by returning to the branch source later. 6. When branching from an exception event microprogram to an interrupt processing program, first information indicating whether or not execution of the exception event processing program is completed is provided for each type of exception event. The second information is stored in the corresponding register of the first register, and the second information used when the execution process of the exception event processing program is resumed after returning from the branch destination interrupt processing program is stored in the second register. The interrupt processing method according to claim 5. 7. The exception event is an interrupt in which a priority level is set for permission of the interrupt, and when the first interrupt processing program branches to the second interrupt processing program, The first information indicating whether or not the execution of the interrupt processing program of
A second register which is stored in a corresponding register of the first register provided for each interrupt priority level and is used when returning from the branch target interrupt processing program and restarting the execution of the branch source interrupt processing program 6. The interrupt processing method according to claim 5, wherein the information of 1 is stored in a corresponding register of the second register provided for each interrupt priority level. 8. A method for evaluating whether an interrupt generated during execution of an interrupt processing program having a predetermined priority level among the interrupt priority levels is interrupt-enabled, and having the predetermined priority level When branching from the first interrupt processing program to the second interrupt processing program, first information indicating whether or not the execution of the first interrupt processing program is completed is provided for each of the predetermined priority levels. The second information, which is stored in the provided first register and is used when returning from the interrupt processing program of the branch destination and restarting the execution of the processing program of the branch source interrupt, is set to the predetermined priority level. The interrupt processing method according to claim 5, wherein the interrupt is stored in a corresponding register of a second register provided separately.