JPH0961853A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a liquid crystal display device having a high aperture ratio while preventing a short circuit between a pixel electrode and a scanning line or a signal line and generation of parasitic capacitance, and a manufacturing method thereof. . SOLUTION: A fluorine cyclic polymer having a repeating unit derived from perfluoroanyl vinyl ether or perfluorobutenyl vinyl ether having a small relative dielectric constant is deposited as an interlayer insulating film on an array substrate including a thin film transistor. By providing the pixel electrode, the region surrounded by the scanning line and the signal line can be covered with the pixel electrode 3 without waste.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for improving the aperture ratio and a manufacturing method thereof.

[0002]

2. Description of the Related Art At present, improvement of the aperture ratio is mentioned as a problem of liquid crystal display devices. As a conventional technique, for example, Japanese Patent Laid-Open No. 6-130416 discloses a structure in which a pixel electrode can be overlapped with a gate line and a signal line by providing an interlayer insulating film covering a source electrode and a drain electrode of a transistor. It is shown.

With this structure, the pixel electrode can be formed in the entire area surrounded by the scanning line and the signal line, and the aperture ratio can be improved. However, the conventional interlayer insulating film has a high relative permittivity, and when a voltage is applied to the scanning line and the signal line, a parasitic capacitance is generated between the interlayer insulating film and the pixel electrode, which causes display failure.

[0004]

As described above,
An interlayer insulating film was provided in the lower layer of the pixel electrode to improve the aperture ratio, and the pixel electrode was overlapped with the scanning line and the signal line to create a structure with no wasted space, but due to the parasitic capacitance with the pixel electrode at that time There was a display defect problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device which improves the aperture ratio and does not generate a parasitic capacitance between a pixel electrode and a wiring which affects display. To do.

[0006]

The present invention comprises a first substrate,
A plurality of scanning lines formed on the first substrate, a plurality of signal lines formed so as to be orthogonal to the scanning lines, a thin film transistor formed at the intersection of the scanning lines and the signal lines, An interlayer insulating film having an acrylic resin as a main component formed so as to cover the thin film transistor on the entire surface of the first substrate, and a pixel electrode electrically connected to the thin film transistor and formed on the interlayer insulating film. An array substrate having: a second substrate; a counter substrate having a counter electrode formed on the second substrate; and a liquid crystal sandwiched between the array substrate and the counter substrate. Is a liquid crystal display device.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. Example 1 A sectional view of a liquid crystal display device in this example is shown in FIG.
In the array substrate in the liquid crystal display device of the present invention, the gate electrode 1 is formed on the glass substrate 8 as the first substrate, the first gate insulating film 9 is formed on the entire surface, and the thin film transistor (TFT) is formed in the region on the gate electrode. : Thin Film
Transistor 4 is disposed, an interlayer insulating film of acrylic resin is deposited on the first gate insulating film to a height covering TFT 4, and the pixel electrode 3 is formed on the interlayer insulating film in a state of being in contact with a part of the TFT. Thus, the alignment film 20a is formed on the entire surface of the uppermost layer.

Next, as a counter substrate, red, green, and blue color filters 22 are formed on a glass substrate 21, which is a second substrate, counter electrodes are formed on the entire surface, and an alignment film 20b is further formed on the entire surface. ing.

The array substrate and the counter substrate sandwich the liquid crystal 24 with the alignment films 20a and 20b inside with the spacer 25 and the sealing material 27 interposed therebetween.

Next, a more detailed description will be given with reference to the plan view of the array substrate shown in FIG. Scanning lines 1 for transmitting a gate voltage and signal lines 2 for transmitting a signal voltage are arranged on the glass substrate 8 so as to intersect with each other in a three-dimensional manner, and in a region surrounded by these scanning lines 1 and signal lines 2. A pixel electrode 3 is formed, and a TFT 4 for selectively supplying a signal voltage to the pixel electrode 3 at a position where the scanning line 1 and the signal line 2 intersect.
Is arranged. The drain electrode 5 of the TFT 4 is integrated with the signal line 2, and the source electrode 6 is connected to a part of the pixel electrode 3. As the gate electrode, in this embodiment, the scanning line 1 directly serves as the gate electrode of the TFT 4.
In addition, an electrode 7 serving as an auxiliary capacitance is provided below the pixel electrode 3 in a portion where the pixel electrode 3 and the scanning line 1 overlap with each other,
An auxiliary capacitance is formed between the electrode 7 and the scanning line 1.

Next, the manufacturing process of the liquid crystal display device in this embodiment will be described. FIG. 3A shows the TFT in FIG.
4 is an enlarged view of FIG. 4, showing the array substrate in FIG.
It is also a cross-sectional view when cut by. 2B is the same as FIG.
3 is a partially enlarged view of the TFT 4 in FIG. First, a Mo.W (molybdenum.tungsten) alloy or a Mo.Ta (molybdenum.tantalum) alloy to be the scanning line 1 is deposited on the glass substrate 8 by a sputtering method to a thickness of 1000 to 3000 angstroms, and then etched. Form a pattern.

Next, as the first gate insulating film 9, SiO
x is a plasma CVD (Chemical Vapor)
Deposition method is used to deposit a thickness of 4000 angstroms. Second gate insulating film 1
0 is similarly deposited by the plasma CVD method to a thickness of 500 angstroms, and amorphous silicon (hereinafter referred to as a-Si) to be the semiconductor layer 11 is deposited thereon by the plasma CVD method to a thickness of 500 angstroms. Deposit on. Then, the second gate insulating film 10 and a-Si are simultaneously etched to form a pattern. At this time, as shown in FIG. 2B, the width d ₁ of the semiconductor layer 11 with respect to the direction in which the source electrode 6 and the drain electrode 5 which will be described later are opposed to each other (hereinafter, referred to as the X direction) is as follows. Patterning is performed so as to be narrower than the width of 5.

Subsequently, SiNx is deposited as the etching stopper layer 12 by the plasma CVD method to a thickness of 3000 angstroms, and when the etching stopper layer 12 is etched, the resist is formed by a so-called self-alignment method. That is, by applying a positive type resist to the entire surface and exposing from the back surface of the glass substrate, the scanning line 1 among the resists applied on the etching stopper layer 12 using the scanning line 1 as a mask.
The resist except for the upper part is softened. Further, regarding the patterning of the scanning line 1 in the longitudinal direction, exposure is performed from the upper surface through a mask. By performing development in this state, the position and size of the etching stopper layer 12 can be made precise, and desired transistor characteristics can be obtained.

Next, as the ohmic contact layer 13, n ⁺ a-Si is deposited to a thickness of 500 angstroms by the plasma CVD method, and n ⁺ a-S of the gate electrode pad portion and the transfer portion for supplying the opposite potential is formed.
The openings of i and SiOx are removed by CF ₄ , O ₂ or HF, NH ₄ F or the like by a method such as chemical dry etching or wet etching.

Further, Mo / Al / Mo to be the source electrode 6 and the drain electrode 5 are deposited to a thickness of 300 Å, 3500 Å, and 700 Å, respectively, and patterned by etching. In this state, since the source electrode 6 and the drain electrode 5 are short-circuited via n ⁺ a-Si, either chemical dry etching, reactive ion etching or plasma etching is used, and the gas used is SF ₆ , An interval of 14 using CF ₄ , O ₂ , Cl _2, etc.
The TFT 4 is formed by removing the n ⁺ a-Si in the region to be formed. Further, in this step, a Mo / Al / Mo layer is also formed in a region where an electrode for carrying the auxiliary capacitance is formed.

At this time, as shown in FIG. 3A, the source electrode 6 and the drain electrode 5 face each other with a gap 14 therebetween, and the end portion 6a of the source electrode 6 and the drain electrode 5 on the gap 14 side. 5a to the end portion 12a of the etching stopper layer 12 in the X direction, the horizontal distance d ₂ is about 2
Design to be μm. In the present embodiment, this horizontal distance d ₂ is the shortest distance from the region of the interval 14 to the region where the source electrode 6 or the drain electrode 5 is in contact with the semiconductor layer 11 via the ohmic contact layer 13. Further, as shown in FIG. 6B, the source electrode 6 and the drain electrode 5 are in a state of being covered by the source electrode 6 and the drain electrode 5, except for the space 14 formed therebetween.

Next, as the interlayer insulating film 15, an organic solvent made of perfluoroanyl vinyl ether or a fluorine-containing cyclic polymer having a repeating unit derived from perfluorobutenyl vinyl ether, trade name CYTOP (Asahi Glass Co., Ltd.), Deposit to a thickness of 1 μm or more. The relative permittivity of CYTOP is about 2.1 and the intrinsic viscosity is about 0.1 Ns / m ² (Newton second per square meter). As a method of forming the interlayer insulating film 15, first, a silane coupling agent is formed by using any one of a spin coating method, a dipping method, and a spraying method, and baking is performed at 230 ° C. or lower.
Then, after applying Cytop in the same manner, for example, in the case of the spin coating method, after rotating for 1 minute or more at a rotation speed of 4000 rpm, when the through hole is opened in the subsequent step, the edge portion becomes curved. As described above, the heat treatment is performed at a temperature lower than the boiling point of the interlayer insulating film 15 and for a short time. In this embodiment, the temperature is 170 ° C. and the time is about 7 minutes. Next, as a method of opening the through hole, down-flow type dry etching with Ar + CF ₄ + O ₂ gas or reactive etching is performed, and then, light ashing is performed with O ₂ . In this way, the interlayer insulating film 15 deposited on the upper portion of the source electrode 6 and the region where the electrode 7 serving as the auxiliary capacitance is formed is partially etched to form the pixel electrode 3 to be deposited in the next step. Be ready to contact. Further, heat treatment is performed at a temperature at which the semiconductor layer is not deteriorated, for example, at 270 ° C. or lower for at least 1 hour or more. Thus, the heat treatment before and after the opening of the through hole makes the edge portion of the through hole into a curved surface, improves the coverage of the pixel electrode 3, and prevents the disconnection.
Note that FIG. 4 is a cross-sectional view taken along the line BB ′ in FIG. 1 and shows an electrode that serves as an auxiliary capacitance.

Next, as the pixel electrode 3, ITO (Indium Tin Oxide), which is a transparent conductive film, is sputter-deposited to a thickness of 1000 to 2000 angstroms. Here, before etching the ITO, the ITO is processed.
In order to improve the light transmittance of, the heat treatment is performed at 100 to 150 ° C. for about 1 hour. Here, the pixel electrode 3 is in contact with a part of the source electrode 6 exposed in the previous step and the electrode 7 on the first gate insulating film corresponding to the upper part of the scanning line 1 and serving as an auxiliary capacitance.

Then, pattern formation is performed using the negative resist by the self-alignment described above. At that time, the scanning line 1 and the signal line 2 serve as a mask. By such a method, the pixel electrode 3 has a size with no gap between the scanning line 1 and the signal line 2 when the substrate is viewed from above in the vertical direction.

Further, an alignment film 20a made of polyimide is provided on the uppermost layer. As a pretreatment for the alignment film 20a, a silane coupling agent is used, for example, by a spin coating method.
Apply at a speed of 000 rpm and bake at a temperature of 180 ° C. within 15 minutes.

Next, polyimide is applied as an alignment film 20a on the substrate subjected to the above-mentioned pretreatment, and 100 to 180 is applied.
It is fired at an appropriate temperature of ° C and subjected to a rubbing treatment. At this time, the alignment film 20a is applied using a jig larger than the area of a normal pixel region, and the alignment film 20 is applied to a region to which the sealant 27 is adhered in a bonding step with a sealant 27 described later.
a is covered. In this way, an array substrate is obtained.

Next, the method of manufacturing the counter substrate and the bonding of the array substrate and the counter substrate will be described with reference to FIG. The opposite substrate has a thickness of 1.1 m as the second substrate.
A glass substrate 21 having a size of about m is prepared.
The green and blue color filters 22, the counter electrode 23 made of ITO, and the alignment film 20b made of polyimide are sequentially stacked. The alignment film 20b is also subjected to a rubbing treatment, and the rubbing direction is the liquid crystal 24 injected between the array substrate and the counter substrate when they are bonded to each other.
Are twisted 90 degrees and oriented. In addition, the alignment film 20b on the counter substrate is also formed in a large size so that the alignment film 20b covers the region bonded by the sealing material 27.

Next, the array substrate and the counter substrate are attached to each other by using the sealing material 27 except the liquid crystal injection port so that the alignment films 20a and 20b are on the inside. As the sealing material 27, for example, a thermosetting epoxy resin mixed with a filling material for a flow stop is used. At this time, the sealing material 27 is provided on the alignment films 20a and 20b described above.

Next, spacers 25 are sprinkled to keep the distance between the two substrates. Particle size of about 10 made of alumina
The spacer 25 having a particle size of μm is applied by a dry spraying method in which a high voltage is applied and sprayed by a force such as static electricity.

After that, the two substrates are precisely aligned and bonded to each other, and heat is applied while pressing the bonded substrates to cure the sealing material 27. In this way, an empty cell of the liquid crystal display cell is obtained.

Next, the liquid crystal 24 is injected. As an injection method, set the empty cell and the container containing the liquid crystal to a secret, evacuate the whole confidential device, and when the vacuum reaches the inside of the empty cell, immerse the liquid crystal in the injection port of the empty cell, When a nitrogen gas or the like is flown into and the atmospheric pressure is returned to, the empty cell is filled with the liquid crystal. After the injection of the liquid crystal is completed and then the injection is completed, the injection port is sealed with the sealing material 27.

Polarizing plates 26a and 26b coated with an adhesive material in advance are attached to both surfaces of the liquid crystal cell thus obtained while being suppressed by rubber rollers so as not to entrap air bubbles. The optical axes of the polarizing plates 26a and 26b are aligned with the rubbing directions of the alignment films 20a and 20b.

Next, as shown in FIG. 5, a TAB-IC (Tape Automated Bonn) serving as a drive circuit is formed.
ding-Integrated Circuits)
30 and a PC (Printed Circuit) substrate 31 are connected.

Then, a backlight 32 is attached behind the liquid crystal cell to obtain a desired liquid crystal display device. According to the above-described embodiment, by providing the interlayer insulating film 15, the scanning line 1 and the pixel electrode 3, and the signal line 2 and the pixel electrode 3 are provided.
The pixel electrode 3 can be formed in the region surrounded by the scanning line 1 and the signal line 2 with the maximum size while preventing a short circuit between the pixel electrode 3 and the pixel electrode 3 and the aperture ratio of the liquid crystal display device can be improved. In addition, by using a material having a low relative permittivity for the interlayer insulating film 15, the parasitic capacitance that has conventionally been generated between the scanning line 1 or the signal line 2 and the pixel electrode 3 affects the display. It can be reduced to the extent not. According to the experiment, the effect that the interlayer dielectric film having a relative dielectric constant of about 5.0 or less does not affect the display is recognized. When a material having a relative dielectric constant higher than this is used for the interlayer insulating film, it is necessary to increase the film thickness, which lowers the transmittance and makes the brightness unsuitable for practical use.

Furthermore, since the CYTOP that becomes the interlayer insulating film 15 has a low intrinsic viscosity, the surface is flat and the pixel electrode 3
Suitable as a base for. The pixel electrode formed on the flat interlayer insulating film 15 as described above can make the electric field strength applied to the liquid crystal uniform and suppress display unevenness.

Further, the electrode 7 serving as the auxiliary capacitance is arranged above the scanning line 1 to form the auxiliary capacitance with the scanning line 1, so that the auxiliary capacitance is provided in the pixel region. The aperture ratio can be improved more than that of one.

According to the configuration of this embodiment described above, about 80
% Aperture ratio can be obtained. Further, by making the width d ₁ of the semiconductor layer 11 in the X direction narrower than the width of the source electrode 6 and the width of the drain electrode 5, it is possible to prevent characteristic deterioration of the semiconductor layer 11 due to light emitted from the back surface of the substrate.
That is, when the width d ₂ of the semiconductor layer 11 is larger than the widths of the source electrode 6 and the drain electrode 5, the protruding portion is irradiated with light and carriers are generated, whereby the source electrode 6 and the drain electrode 5 are generated. 5 is electrically connected via the ohmic contact layer 13. As shown in FIG. 3B, the width d ₁ of the semiconductor layer 11
Is the same as the width of the source electrode 6 and the drain electrode 5,
Alternatively, if it is narrowed, the region where the light emitted from the back side of the substrate hits the semiconductor layer 11 is only the portion excluding the upper portion of the scanning line 1. Since this region is a portion where the semiconductor layer 11 is in contact with the source electrode 6 and the drain electrode 5, even if minority carriers are generated by light irradiation, the switching characteristics of the semiconductor are not affected.

Further, as shown in FIG.
By setting d ₂ which is the shortest distance from the region of 1 to the region where the source electrode 6 or the drain electrode 5 is in contact with the semiconductor layer 11 through the ohmic contact layer 13 to be longer than the diffusion length of carriers, It is possible to prevent the characteristic deterioration of the semiconductor layer 11 due to the irradiation light. That is, the region of the semiconductor layer 11 to which the light emitted from the substrate surface side is exposed is the source electrode 6 and the drain electrode 5.
The region not covered by the space, that is, the region corresponding to the space 14 below, diffuses the carriers generated in this region to the region in contact with the ohmic contact layer 13, and the source electrode 6 and the drain electrode 5 are electrically connected. Can be prevented from being connected.

Further, by performing a pretreatment on the interlayer insulating film 15, forming the alignment film 20a and heating it, C =
O-bonding is sufficiently advanced to obtain a strong adhesive force. And
In the bonding of the array substrate and the counter substrate, the regions on the substrate to be bonded with the seal material 27 are covered with the alignment films 20a and 20b having a strong adhesive force with the seal material 27, and the adhesive force with the seal material 27 is increased. Higher adhesiveness can be obtained as compared with the case where the sealing material is provided on the weak interlayer insulating film 15.

In the present embodiment, the pixel electrodes 3 are formed without gaps between the scanning lines 1 and the signal lines 2 when viewed from above in the vertical direction, but they may overlap with each other within a range where they do not contact adjacent pixel electrodes. Absent. The width d _{1 of the} semiconductor layer is
The width of the source electrode 6 or the width of the drain electrode 5 may be the same as the narrower width. Furthermore, a layer such as a color filter or a light shielding film may be formed on the array substrate side.

Further, a light-shielding film may be formed in the same layer as the color filter 22 on the counter substrate, if necessary. Furthermore, a protective film or the like may be formed below the alignment films of the array substrate and the counter substrate. Further, it can be applied to a reflective liquid crystal display device that does not use a backlight. Example 2 FIG. 6 shows a sectional view of the liquid crystal display device of this example.

The array substrate 51 is formed on the glass substrate 52 by one.
000 Å thick a-Si light-shielding film 5
3 are formed. An undercoat film 54 made of SiNx having a thickness of 1000 Å is formed on the entire surface. A semiconductor layer 55 is patterned on the undercoat film 54 with a thickness of 500 Å. This semiconductor layer 55 is made of p-Si. A gate insulating film 56 made of SiNx, SiOx or the like is formed on the entire surface so as to cover the semiconductor layer 55. Then, a gate electrode 57 made of molybdenum / tungsten of 2500 angstrom is patterned on a part of the semiconductor layer on the gate insulating film 56. The semiconductor layer 55 is ion-doped using the gate electrode 57 as a mask, and has a source region 55s, a drain region 55d, and a channel region 55c below the gate electrode 57.
It is divided into 250 to cover the gate electrode
Insulating film 58 made of SiOx having a thickness of 0 angstrom
Are formed. The insulating film 58 is formed on the source region 55.
A through hole is formed on the drain region 55d and on the source region 55 through the through hole.
A source electrode 59 and a drain electrode 60 are formed so as to be connected to the drain region 55d.

Then, an acrylic resin HRC (Japan Synthetic Rubber Co., Ltd.) is formed as an interlayer insulating film 61 with a thickness of 4 μm so as to cover these TFTs. And
A through hole is formed in the interlayer insulating film 61 in a region corresponding to the source electrode 59, and the pixel electrode 62 formed on the interlayer insulating film 61 is connected to the source electrode 59 through the through hole. . Further, an alignment film 63a made of polyimide or the like is formed on the entire surface.

On the other hand, in the counter substrate 64, a color filter 66 is formed on a glass substrate 65, a common electrode 67 made of ITO is formed thereon, and an alignment film 63b made of polyimide is further formed on the entire surface.

The liquid crystal 68 is sandwiched between the array substrate 51 and the counter substrate 64. In this embodiment, the interlayer insulating film 61 may use the acrylic resin such as Cytop described above. Further, the manufacturing process such as heat treatment before and after forming the through hole of the interlayer insulating film 61 can apply the method described in the previous embodiment. Further, in the case of this embodiment, a color filter may be formed on the interlayer insulating film 61, or the interlayer insulating film 61 may be directly colored to serve also as a color filter.

[0041]

According to the present invention, an acrylic resin having a small relative dielectric constant is used as an interlayer insulating film of a liquid crystal display device, and a pixel electrode is formed on the acrylic resin, thereby forming a pixel electrode and a scanning line or a pixel electrode. The parasitic capacitance generated between the signal line and the signal line can be suppressed. As a result, it is possible to obtain a liquid crystal display device having a high aperture ratio and no display failure due to parasitic capacitance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a plan view of one pixel of the array substrate according to the first embodiment of the present invention.

3A is a cross-sectional view of the array substrate in FIG. 1 cut along AA ′. (B) is an enlarged view of the thin film transistor in FIG. 1.

FIG. 4 is a cross-sectional view of the array substrate in FIG. 1 taken along the line BB ′.

FIG. 5 is an external view of a liquid crystal display device.

FIG. 6 is a sectional view of a liquid crystal display device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Scan line 2 ... Signal line 3, 62 ... Pixel electrode 4 ... Thin film transistor 5, 60 ... Drain electrode 6, 59 ... Source electrode 7 ... Electrode which bears auxiliary capacity 8, 21, 52, 65 ... Glass substrate 9, 10, 56 ... Gate insulating film 11, 55 ... Semiconductor layer 12 ... Etching stopper layer 13 ... Ohmic contact layer 14 ... Interval 15, 61 ... Interlayer insulating film 20a, 20b, 63a, 63b ... Alignment film 23, 67 ... Counter electrode 24, 68 ... Liquid crystal 25 ... Spacer 27 ... Sealing material

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaichi Fukuda 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Yokohama office (72) Inventor Nobuki Ibaraki Shin-sugita-cho, Isogo-ku, Yokohama, Kanagawa Ceremony Company Toshiba Yokohama Works (72) Inventor Kiyotsugu Mizouchi 50 Kamamibe, Yobu, Himeji-shi, Hyogo Stock Company Toshiba Himeji Factory (72) Inventor Koji Hidaka 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Stock Company Toshiba Yokohama Office

Claims (10)

[Claims] 1. A first substrate, a plurality of scanning lines formed on the first substrate, a plurality of signal lines formed so as to be orthogonal to the scanning lines, and the scanning lines and the signal lines. A thin film transistor formed at an intersection point, an interlayer insulating film containing acrylic resin as a main component formed to cover the thin film transistor on the entire surface of the first substrate, and the interlayer insulating film electrically connected to the thin film transistor. An array substrate having a pixel electrode formed on the second substrate, a second substrate, and a counter electrode formed on the second substrate,
A counter substrate having, and a liquid crystal sandwiched between the array substrate and the counter substrate,
A liquid crystal display device comprising: 2. The liquid crystal display device according to claim 1, wherein the relative dielectric constant of the interlayer insulating film is 5.0 or less. 3. The interlayer insulating film is a fluorine-containing cyclic polymer having a repeating unit derived from perfluoroanyl vinyl ether.
The liquid crystal display device according to any one of the above. 4. The liquid crystal display device according to claim 1, wherein the interlayer insulating film is a fluorocyclic polymer having a repeating unit derived from perfluorobutenyl vinyl ether. 5. The liquid crystal display device according to claim 1, wherein each pixel electrode is formed up to a region on the scanning line or the signal line. 6. The thin film transistor is formed by stacking a gate electrode, a gate insulating film, a semiconductor layer, and an etching stopper layer from the first substrate side, and is formed so as to overlap the etching stopper layer and the semiconductor layer. A source electrode and a drain electrode, and in a region where the source electrode and the drain electrode overlap with the etching stopper layer, a length in a direction in which the source electrode and the drain electrode face each other is determined by light irradiation. 5. The liquid crystal display device according to claim 1, wherein the diffusion length of carriers generated in the semiconductor layer is longer. 7. The thin film transistor is formed by stacking a gate electrode, a gate insulating film, a semiconductor layer, and an etching stopper layer from the first substrate side, and is formed so as to overlap the etching stopper layer and the semiconductor layer. A source electrode and a drain electrode, and a length in a direction in which the source electrode and the drain electrode face each other is 2 μm or more in a region where the source electrode and the drain electrode overlap with the etching stopper layer. 5. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. 8. The through hole formed in the interlayer insulating film is tapered, or the edge portion of the through hole is curved. Liquid crystal display device. 9. The array substrate and the counter substrate are adhered to each other by a sealing material, and the sealing material is formed on a region of the array substrate where an alignment film is formed. 5. The liquid crystal display device according to any one of 1, 2, 3 and 4. 10. A step of forming a scanning line, a signal line, and a thin film transistor on a first substrate, a step of forming an interlayer insulating film on the entire surface of the first substrate including the thin film transistor, and a step of forming the interlayer insulating film on the first substrate. And a step of forming a through hole in the interlayer insulating film, and a step of performing a second heat treatment on the interlayer insulating film after the through hole is formed. A liquid crystal display device comprising: a step of manufacturing a counter substrate having a step of forming a counter electrode on the substrate; and a step of bonding the array substrate and the counter substrate and injecting liquid crystal into a gap between them. Manufacturing method.