JPH0965254A - Image display device - Google Patents

Abstract

(57) [Abstract] (Correction) [Problem] To obtain a video signal for dual-screen image display by performing time-axis compression processing for each line period on two video signals, a non-interlaced signal and an interlaced signal. , Make sure the movement of the playback dual-screen image is not unnatural. SOLUTION: The time axis compression is performed for each of the line memory unit 15 in which the time axis compression is performed for each line period of the first video signal and each line period included in each frame period of the second video signal. Frame memory unit 1 in which
When there is a signal selection unit 25 that forms a display video signal from the output signal from 6, one of the two video signals supplied to the video signal input terminals 10 and 11 is a non-interlaced signal and the other is an interlaced signal. , Signal selection unit 25
In order to form the display video signal obtained from the interlaced signal as a reference at all times, the signal transmission control units 12, 21, 23 for controlling the transmission states of the two video signals are formed. Prepare

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying an image represented by each of two independent video signals as a two-screen image on the display surface of one image display section.

[0002]

2. Description of the Related Art A dual-screen image display system for displaying an image represented by each of two independent video signals on its image display surface using a single image display device is part of the diversification of image information provision. Is proposed as. In such a two-screen image display system, for example, an image display device having an image display surface on which horizontal scanning (line scanning) and vertical scanning (field scanning) are performed is used. A screen of an image represented by each of the two video signals is formed on the surface as being arranged adjacent to each other in the line scanning direction, that is, in the left-right direction.

In this way, when displaying a two-screen image in which two screens are arranged adjacent to each other in the left-right direction on the image display surface of the image display device, for example, the dimension of each of the two screens in the line scanning direction is substantially. Therefore, the image represented by the first video signal, which is one of the two video signals, is displayed on the left half of the image display surface, and the two video signals are displayed on the right half of the image display surface. Assuming that the image represented by the second video signal, which is the other one of the above, is displayed, the display video signal supplied to the image display device includes each line period corresponding to one line period of the first video signal ( 1H) time-axis compressed to approximately 1/2 line period (0.5 H) time-axis compressed 1-line period of the second video signal and time-axis compressed to approximately 1/2 line period Combine with video signal It is required to be formed and formed.

In order to obtain such a video signal for dual-screen image display, for example, a line memory capable of writing and reading for one line period of the video signal is used, and the first video signal By processing so that the line period portion is time-axis compressed to approximately ½ line period, a first time-axis compressed video signal is obtained, and one field period (1V) portion of the video signal is two (odd number). By using a frame memory capable of writing and reading for one frame period (2V) which is continuously formed by the field period and the even field period), the second video signal is supplied for each frame period. A second time-axis compressed video signal is obtained by processing so that each line period is time-axis compressed into approximately 1/2 line period, and the first time-axis compressed video signal and the second time-axis compressed video signal are obtained. Compressed video signal A method of synthesis is taken at the door.

To obtain the first time-axis compressed video signal, the first video signal is sequentially written into the line memory for each one-line period, and the video for each one-line period is written from the line memory. The signal is approximately 1
The read time is set to the first time when the read time corresponds to the / 2 line period.
The video signal is selected so as to coincide with the end time of the writing time for one line period. That is, as indicated by the broken line in FIG. 6 (horizontal axis: time, vertical axis: line memory address), each line period of the first video signal is sequentially written in the line memory, and in FIG. As shown, each written line period is read. The reading for each line period shown by the solid line in FIG. 6 is started at the time when the writing for the line period is completed, and is performed at a speed approximately twice the writing speed, and substantially for the line period. Is completed approximately 1/2 line period after the end of the entire writing of Therefore, the reading of each line period from the line memory is performed at a time corresponding to approximately 1/2 line period at intervals corresponding to approximately 1/2 line period.
It will be performed intermittently. As a result, the first time-base compressed video signal is obtained from the line memory.

To obtain the second time-axis compressed video signal, the odd field period and the even field period forming each frame period of the second video signal are sequentially written in the frame memory. Then, the video signal for each line period included in each frame period of the second video signal written therein is read from the frame memory with a read time corresponding to approximately 1/2 line period. Thereby, from the frame memory, the second
The time-axis compressed video signal for each frame period of the video signal is obtained as the second time-axis compressed video signal.

In this way, the first time-axis compressed video signal obtained from the line memory and the second time-axis compressed video signal obtained from the frame memory are, for example, each of the first time-axis compressed video signal. Second for 1/2 line period
The respective 1/2 line periods in the time-axis compressed video signal of (1) are connected to form the respective line periods. As a result, the first half of each line period is the first time-axis compressed video signal based on the first video signal, and the second half is the second time-axis compressed video signal based on the second video signal. And a video signal for displaying a two-screen image is formed.

Under the circumstances, since the first video signal and the second video signal are independent of each other and are not in the mutually synchronized state, the first video signal and the second video signal are not synchronized with each other. A problem is the synchronization state between the first time-axis compressed video signal and the second time-axis compressed video signal. So, for example, the first
The writing of the video signal of
Is performed according to the timing signal formed based on the synchronization signal included in the second video signal, and the writing of the second video signal to the frame memory is performed based on the synchronization signal included in the second video signal. Read out from the line memory for each line period, and each line included in each frame period of the second video signal from the frame memory. The reading for each period is performed according to the timing signal formed based on the synchronization signal included in the first video signal, and the first time-axis compressed video signal obtained from the line memory is used. The second time-base compressed video signal obtained from the frame memory is placed in mutual synchronization.

In this way, for the second video signal, writing to the memory section is performed according to the timing signal formed based on the synchronization signal included in the second video signal, and the line period from the memory section. Second reading is every minute
The frame signal is used for writing and reading the second video signal because it is performed in accordance with the timing signal formed based on the synchronization signal included in the first video signal which is not in the mutual synchronization state.

[0010]

When the two-screen image display video signal is formed as described above, the writing of the second video signal for each frame period in the frame memory is performed by the second writing. Is performed according to a timing signal formed based on a synchronization signal included in the video signal of the first video signal, and the reading for the line period included in each written frame period is performed in the first writing to the line memory. This is performed according to a timing signal formed based on the synchronization signal included in the video signal. Therefore,
When the first video signal is a non-interlaced signal that is not a video signal (interlaced signal) based on the interlaced system, and the second video signal is an interlaced signal, it is an interlaced signal written in it in the frame memory. The reading for the line period included in each frame period of the second video signal is performed according to the timing signal formed based on the synchronization signal included in the first video signal which is a non-interlaced signal. .

In this case, the first video signal, which is a non-interlaced signal, includes two field periods that form each frame period, and the odd number that forms each frame period of the second video signal, which is an interlaced signal. There is no difference in the synchronization relationship between the field period and the even field period, and the synchronization conditions are the same.
Therefore, in each frame period of the second video signal which is the interlaced signal written from the frame memory, which is formed based on the synchronization signal included in the first video signal which is such a non-interlaced signal. The timing signal for reading the included line period is the same for each field period in the first video signal and is obtained.

As a result, the reading of the line period included in each frame period of the second video signal which is the interlaced signal written from the frame memory is included in the first video signal which is a non-interlaced signal. By the timing signal formed based on the synchronization signal,
The line period included in one of the two field periods forming each frame period of the second video signal written in the frame memory is performed under the condition of being repeatedly read out, The reading is not performed for the line period included in the other of the two field periods forming each frame period of the second video signal written in (1).

That is, writing into the frame memory for each frame period of the second video signal and for each line period included therein is performed, for example, as shown in FIG. 7 (horizontal axis: time, vertical axis: frame memory / line address). ), A memory area corresponding to line addresses 0 to Af (Af corresponds to the number of line periods in one frame period) is used for writing, and at the same time, from the frame memory, Readout for each line period included in each frame period of the second video signal written therein is
As shown by the solid line in FIG. 7, line addresses 0 to Af / 2 (Af is a 1/2 frame period, that is,
The memory area corresponding to the number of line periods in one field period) is read out twice and is repeated. Therefore, in this case, of the line period included in each frame period of the second video signal written in the frame memory, only the one included in the odd field period is repeatedly read twice. The data included in the even field period is not read.

Therefore, the second time-axis compressed video signal obtained from the frame memory has an odd field period and an odd field period of the even field period forming each frame period of the second video signal. The second time axis of the two-screen images displayed by the image display device based on the video signal for displaying a two-screen image including the second time-axis compressed video signal. The image based on the compressed video signal has a lower vertical resolution,
The movement may be unnatural.

In view of the above point, the present invention uses the line memory section to make the first video signal time-compressed for each line period into about 1/2 line period. The first time-axis compressed video signal is obtained and
2) by using the frame memory unit under the condition that the reference timing is set with the synchronization signal included in the video signal of
Of the first time axis by obtaining the second time axis compressed video signal by making the video signal In obtaining the dual-screen image display video signal by synthesizing the compressed video signal and the second time-axis compressed video signal, one of the two video signals, the first video signal and the second video signal, is obtained. Even when a non-interlaced signal and the other is an interlaced signal, a two-screen image display video signal formed based on these two video signals All of them provide an image display device capable of preventing an unnatural image or the like from being generated without causing a reduction in vertical resolution.

[0016]

An image display device according to the present invention includes first and second video signal input ends to which two video signals, which are first and second video signals, are supplied. First
A line memory unit for sequentially and intermittently obtaining a video signal for a first 1/2 line period, which is formed by performing time-axis compression reading for each line period of the video signal of
Formed by performing time-axis compression reading for line periods included in each frame period of the video signal of
, A frame memory unit for sequentially obtaining video signals for 1/2 line period, a video signal for the first 1/2 line period obtained from the line memory unit, and a second video signal obtained from the frame memory unit. A signal selection unit for extracting a video signal for a half line period and forming a display video signal;
According to the display video signal obtained from the signal selection unit, the first
And a two-screen image display section for displaying a two-screen image corresponding to the image represented by each of the second video signals, respectively, and the two video signals supplied to the first and second video signal input ends. When one of the video signals is a non-interlaced signal and the other is an interlaced signal, one of the two video signals, which is the interlaced signal, should always be the first video signal so that the two video signals A signal transmission control unit for controlling the transmission state is provided and configured.

In the image display device according to the present invention configured as described above, the video signal supplied to the first video signal input end by the signal transmission control unit is the interlaced signal, When the video signal supplied to the second video signal input terminal is a non-interlaced signal, the first
The non-interlaced signal supplied to the second video signal input end while the video signal, which is the interlaced signal supplied to the video signal input end, is supplied to the line memory unit as the first video signal. Is supplied to the frame memory unit as a second video signal, and the video signal supplied to the first video signal input end is a non-interlaced signal, and the second video signal When the video signal supplied to the input end is an interlace signal, the video signal which is the interlace signal supplied to the second video signal input end is supplied to the line memory unit as the first video signal. In addition, the video signal which is a non-interlaced signal supplied to the first video signal input end is supplied to the frame memory unit as the second video signal. That, transmission control for the two video signals supplied to the first and second video signal input end is performed.

Accordingly, when one of the two video signals supplied to the first and second video signal input ends is a non-interlaced signal and the other is an interlaced signal, the two video signals are always provided. One of the interlaced signals is the first video signal, and the line memory section performs time-axis compression reading for each line period to generate a video signal for the first 1/2 line period. One of the two video signals, which is the non-interlaced signal, is the second video signal, and the time for the line period included in each frame period in the frame memory unit. Axial compression reading is performed to form a video signal for the second 1/2 line period.

As a result, signal selection in which the video signal for the first 1/2 line period obtained from the line memory unit and the video signal for the second 1/2 line period obtained from the frame memory unit are supplied. The video signal for display (video signal for dual-screen image display) from the unit is a first video signal, that is, an interlaced signal of the two video signals supplied to the first and second video signal input ends. Will be formed as a reference. Therefore, in the two-screen image displayed by the two-screen image display unit according to such a two-screen image display video signal, the image represented by the first video signal, which is the interlaced signal, corresponds to each frame period. Of the odd field period and the even field period that form only one of the odd field period and the even field period, which avoids a situation in which each frame period is formed based on only one of the odd field period and the even field period. Based on both of them, each of the two images forming the two-screen image can be properly obtained without deterioration of the vertical resolution and unnatural movement. Become.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of an image display device according to the present invention.

In the example shown in FIG. 1, two independent video signals S are provided to the video signal input terminals 10 and 11.
V1 and SV2 are supplied. At that time, the video signal SV1
Is supplied to the video signal input terminal 10 and the video signal SV2 is supplied to the video signal input terminal 11, or the video signal SV1 is supplied to the video signal input terminal 11 and the video signal SV2 is supplied to the video signal input terminal. 10 is supplied. Video signals SV1 and SV2
, One of them, for example, the video signal SV1 is an interlaced signal, and the other of them, that is, the video signal SV2 is a non-interlaced signal.

The video signals SV1 and SV2 from the video signal input terminals 10 and 11 are supplied to the video signal selection controller 12. The video signal selection control unit 12 controls the video signal SV1.
The video signal SV1 which is an interlaced signal of S1 and SV2 is analogized as the first video signal when the video signal SV1 is supplied through the video signal input terminal 10 and the video signal input terminal 11. / When the video signal SV2, which is a non-interlaced signal of the video signals SV1 and SV2, is supplied to the digital signal converter (A / D converter) 13 through the video signal input terminal 11, The transmission control is performed for the video signals SV1 and SV2 that are to be supplied to the A / D conversion unit 14 as the second video signal at any time when supplied through the input terminal 10.

Video signal S supplied to A / D converter 13
V1 is digitized in the A / D converter 13,
The line memory unit 15 is used as the digital video signal DV1.
Is supplied to. The video signal SV2 supplied to the A / D conversion unit 14 is digitized in the A / D conversion unit 14 to be a digital video signal DV2 and supplied to the frame memory unit 16. The frame memory unit 16 is composed of a field memory unit 17 and a field memory unit 18.

Further, the video signal SV1 obtained from the video signal selection control unit 12 is supplied to the synchronization signal separation unit 19, and the video signal SV from the video signal selection control unit 12 is supplied.
2 is supplied to the synchronization signal separation unit 20. The sync signal separating unit 19 separates the horizontal sync signal (line sync signal) PH1 and the vertical sync signal (field sync signal) PV1 contained therein from the video signal SV1 and supplies them to the timing signal forming unit 21. Similarly, in the synchronizing signal separating section 20, the horizontal synchronizing signal PH2 and the vertical synchronizing signal PV2 included therein are separated from the video signal SV2 and are supplied to the timing signal forming section 22.

Further, the video signal SV1 from the video signal input terminal 10 and the video signal S from the video signal input terminal 11
Both V2, or both the video signal SV2 from the video signal input terminal 10 and the video signal SV1 from the video signal input terminal 11 are supplied to the interlaced state identifying unit 23. The interlaced state identifying section 23 identifies whether the video signal (video signal SV1 or video signal SV2) from the video signal input terminal 10 is an interlaced signal or a non-interlaced signal, and from the video signal input terminal 11 Video signal (video signal S
It is discriminated whether it is an interlaced signal or a non-interlaced signal for V2 or video signal SV1). And an identification signal CM representing the identification result
Are supplied from the interlaced state identifying section 23 to the timing signal forming section 21.

In the identification signal CM obtained from the interlaced state identifying section 23, the video signal from the video signal input terminal 10 is an interlaced signal, and the video signal input terminal 1
When the video signal from 1 is a non-interlaced signal, that is, when the video signal SV1 is supplied to the video signal input terminal 10 and the video signal SV2 is supplied to the video signal input terminal 11, for example, When the video signal from the video signal input terminal 10 is a non-interlaced signal and the video signal from the video signal input terminal 11 is an interlaced signal, that is, the video signal input terminal 10 is the video signal S
When V2 is supplied and the video signal SV1 is supplied to the video signal input terminal 11, the signal has, for example, a negative polarity.

When both the video signal from the video signal input terminal 10 and the video signal from the video signal input terminal 11 are interlaced signals or non-interlaced signals, that is, for example, the video signal input terminals 10 and 11
In the state where the video signal SV1 is supplied to both of the video signal input terminals 10 and 11
When the state in which V2 is supplied is taken, the identification signal CM from the interlaced state identification unit 23 is assumed to have a positive polarity, for example.

In the timing signal forming section 21, a timing signal WL for writing and a timing signal for reading to and from the line memory section 15 which is supposed to be synchronized with the horizontal synchronizing signal PH1 and the vertical synchronizing signal PV1 from the synchronizing signal separating section 19 are provided. Timing signal RL, read timing signal RF for field memory unit 17, field memory unit 1
The read timing signal RF2 for 8 and the selection control signals SS, SM and SN are formed. At this time, when the identification signal CM from the interlaced state identifying unit 23 has a positive polarity, the read timing signal RL supplied to the line memory unit 15 is the read timing signal RL.
5 is for performing the time-axis compression reading of the signal written in the signal No. 5 in approximately the first half line period in each line period in the video signal SV1,
In addition, the read timing signal RF1 supplied to the field memory unit 17 performs the time-axis compression read of the signal written therein from the field memory unit 17 in the latter half of each line period in the video signal SV1 at approximately 1 / second. The read timing signal RF2 supplied to the field memory unit 18 is used for the two-line period, and time-axis compression reading of the signal written in the field memory unit 18 into the video signal SV1 is performed. In the second half of each line period in the above, approximately half of the line period is performed.

On the other hand, when the identification signal CM from the interlaced state identifying section 23 has a negative polarity, the read timing signal RL supplied to the line memory section 15 is supplied.
However, the time-axis compression reading of the signal written in the line memory unit 15 is performed in the latter half of each line period of the video signal SV1 in the approximately 1/2 line period, and the field memory unit is used. The read timing signal RF1 supplied to the read-out timing signal RF1 is used to perform the time-axis compression read-out of the signal written in the read-out timing signal RF1 from the field memory unit 17 in approximately the first half line period of each line period in the video signal SV1. The read timing signal RF2 supplied to the field memory unit 18 is used for the time-axis compression read of the signal written in the field memory unit 18 within each line period of the video signal SV1. It is intended to be performed in the approximately half line period of the first half.

Further, in the timing signal forming section 21, the identification signal C from the interlaced state identifying section 23 is obtained.
When M has a positive polarity, the selection control signal SS and the selection control signal SM that take a low level are sent out, whereas the identification signal CM from the interlaced state identification unit 23 is sent.
Has a negative polarity, the selection control signal SS and the selection control signal SN which take a high level are transmitted.

The selection control signal SS obtained from the timing signal forming section 21 is supplied to the video signal selection control section 12. When the selection control signal SS has a low level, the video signal selection control unit 12 therefore has the positive polarity of the identification signal CM from the interlaced state identification unit 23, and the video signal SV1 is supplied to the video signal input terminal 10. When the video signal SV2 is being supplied and is being supplied to the video signal input terminal 11, the video signal SV1 from the video signal input terminal 10 is supplied to the A / D converter 13 and the video signal input terminal 11 is supplied. And supplies the video signal SV2 from the A / D converter 14. In addition, the video signal selection control unit 12
When the selection control signal SS has a high level, therefore, the identification signal CM from the interlaced state identification section 23 has a negative polarity, and the video signal SV2 is applied to the video signal input terminal 10.
Is being supplied and the video signal SV1 is being supplied to the video signal input terminal 11, the video signal SV2 from the video signal input terminal 10 is supplied to the A / D converter 14
And the video signal SV1 from the video signal input terminal 11 to the A / D converter 13.

In the timing signal forming section 22, the write timing signal WF1 and the field memory for the field memory section 17 which are supposed to be synchronized with the horizontal synchronizing signal PH2 and the vertical synchronizing signal PV2 from the synchronizing signal separating section 20. A write timing signal WF2 for the section 18 is formed. The write timing signal WF1 supplied to the field memory unit 17 is for writing one of the two field periods forming one frame period of the digital video signal DV2 to the field memory unit 17 sequentially. The write timing signal WF2 supplied to the field memory unit 18 sequentially writes the other of the two field periods forming each frame period of the digital video signal DV2 to the field memory unit 18. It is intended for.

In the line memory section 15 to which the digital video signal DV1 from the A / D conversion section 13 is supplied,
The timing signal WL for writing and the timing signal RL for reading are supplied from the timing signal forming unit 21, the digital video signal DV1 is sequentially written for one line period according to the timing signal WL for writing, and the timing signal for reading is also used. According to RL, the written digital video signal DV1 for each line period is approximately 1
The time axis is compressed and read with a read time corresponding to a / 2 line period.

At this time, when the identification signal CM from the interlaced state identification section 23 has a positive polarity, that is, the video signal SV1 is supplied to the video signal input terminal 10 and the video signal is input to the video signal input terminal 11. When the signal SV2 is being supplied, the read timing signal RL has a read time corresponding to approximately 1/2 line period, and the digital video signal D whose start time is read
It is assumed that the first half of the line period of the video signal SV1 is approximately ½ line period that coincides with the end time of the writing time for one line period of V1. Also,
When the identification signal CM from the interlaced state identification unit 23 has a negative polarity, that is, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal SV1 is supplied to the video signal input terminal 11. In this state, the read timing signal RL causes the read time corresponding to approximately 1/2 line period to coincide with the end point of the write time for the one line period of the digital video signal DV1 to be read. Yes, video signal S
It is assumed that the latter half of each line period in V1 is approximately 1/2 line period.

Therefore, the writing and time-axis compression reading of the digital video signal DV1 in the line memory unit 15 are performed when the identification signal CM from the interlaced state identification unit 23 has a positive polarity, that is, the video signal input terminal. When the video signal SV1 is supplied to 10 and the video signal SV2 is supplied to the video signal input terminal 11, it is indicated by a broken line in FIG. 2 (horizontal axis: time, vertical axis: line memory address). As described above, each line period portion of the digital video signal DV1 is sequentially written, and as shown by the solid line in FIG. 2, each written line period portion is time-axis compressed and read out. Done. That is, the time-axis compression reading for each line period of the digital video signal DV1 is started at the time when the entire line period is written, and is performed at a speed that is about twice the writing speed, and about 1/1 after the start. It is set to end when the two-line period has elapsed.

When the identification signal CM from the interlaced state identifying section 23 has a negative polarity, that is, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal is input to the video signal input terminal 11. When SV1 is being supplied, as shown by a broken line in FIG. 3 (horizontal axis: time, vertical axis: line memory address), each line period of the digital video signal DV1 is sequentially written, and As shown by the solid line in FIG. 3, the writing is performed under the condition that each written line period is time-axis compressed and read.
That is, the time-axis compression reading for each line period of the digital video signal DV1 is started at the time when about 1/2 of the line period is written, and is performed at a speed twice as fast as the writing speed. When approximately ½ line period elapses later, the writing is completed when the writing of all the line period is completed.

As a result, the time-axis compression reading for each line period from the line memory unit 15 is intermittent at intervals corresponding to approximately 1/2 line period, at intervals of approximately 1/2 line period. The line memory unit 15 time-compresses each line period of the digital video signal DV1 into a digital video signal within a time corresponding to approximately 1/2 line period, and is formed 1 /. The digital video signal DX1 for two line periods is sequentially and intermittently obtained.

On the other hand, in the frame memory section 16 to which the digital video signal DV2 from the A / D conversion section 14 is supplied, the digital video signal DV2 is supplied to both the field memory section 17 and the field memory section 18. Then, the write timing signal WF1 from the timing signal forming unit 22 is stored in the field memory unit 17.
And the read timing signal RF1 from the timing signal forming unit 21.

As a result, in the field memory unit 17, one of the two field periods forming each frame period in the digital video signal DV2 is included in a plurality of plural field periods included in it in accordance with the write timing signal WF1. Each line period is sequentially written, and each written line period is approximately 1 / th of the video signal SV1 according to the read timing signal RF1.
The time axis is compressed and read with a read time corresponding to two line periods. Further, in the field memory unit 18, the other of the two field periods forming each frame period in the digital video signal DV2 is divided into a plurality of line periods included therein in accordance with the write timing signal WF2. The lines are sequentially written, and each written line period is approximately 1 in the video signal SV1 according to the read timing signal RF2.
The time axis is compressed and read with a read time corresponding to a / 2 line period. That is, the field memory unit 17
In 18 and 18, time-axis compression reading is performed for each line period included in each of two field periods forming each frame period in the digital video signal DV2.

At this time, the interlaced state identifying section 23
When the identification signal CM from has positive polarity, that is,
When the video signal SV1 is supplied to the video signal input terminal 10 and the video signal SV2 is supplied to the video signal input terminal 11, the field memory unit 17 is operated according to the read timing signal RF1.
From the digital video signal DV2 from the video signal SV1 to the time-axis compression reading for each line period included in one of the two field periods forming the frame period. It is performed in the half line period and included in the other of the two field periods forming each frame period in the digital video signal DV2 from the field memory unit 18 which is performed in response to the read timing signal RF2. The time-axis compression reading for each line period is performed in the latter half of the line period of the video signal SV1 in the approximately 1/2 line period.

When the identification signal CM from the interlaced state identifying section 23 has a negative polarity, that is, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal is input to the video signal input terminal 11. When the SV1 is being supplied, one of the two field periods forming each frame period of the digital video signal DV2 from the field memory unit 17, which is performed according to the read timing signal RF1, is used. The time-axis compression reading for each included line period is approximately 1/2 of the first half of each line period in the video signal SV1.
Each line included in the other of the two field periods forming each frame period in the digital video signal DV2 from the field memory unit 18 performed in the line period and in response to the read timing signal RF2. The time-axis compression reading for the period is performed in approximately the first half line period of each line period in the video signal SV1.

As a result, from the field memory unit 17,
The line period included in one of the two field periods forming each frame period in the digital video signal DV2 is equivalent to the time of the digital video signal within the time corresponding to approximately 1/2 line period in the video signal SV1. The 1/2 line period digital video signal DX2O to be formed by axial compression is sequentially obtained intermittently, and the two fields forming from the field memory unit 18 each frame period of the digital video signal DV2. A line period included in the other of the period is a 1/2 line period which is time-axis-compressed and formed into a digital video signal within a time corresponding to approximately 1/2 line period in the video signal SV1. The digital video signal DX2E is sequentially and intermittently obtained.

The 1/2 line period digital video signal DX1 obtained from the line memory unit 15 is supplied to the digital video signal selection control unit 24, and the field memory unit 17 and the field memory unit 18 forming the frame memory unit 16 are also provided. The 1/2 line period digital video signal DX2O and the 1/2 line period digital video signal DX2E respectively obtained from the digital video signal selection control unit 2 as the 1/2 line period digital video signal DX2.
4 is supplied. Then, the selection control signal SS from the timing signal forming unit 21 is supplied to the digital video signal selection control unit 24.

When the selection control signal SS from the timing signal forming section 21 takes a low level, the digital video signal selection control section 24, therefore, recognizes the interlaced state identifying section 2 accordingly.
When the identification signal CM from 3 has a positive polarity and the video signal SV1 is supplied to the video signal input terminal 10 and the video signal SV2 is supplied to the video signal input terminal 11, the line 1/2 from memory unit 15
The signal selection unit 2 outputs the digital video signal DX1 during the line period.
No. 5 selection contact 25A, and a 1/2 line period digital video signal D from the frame memory unit 16
X2 is supplied to the selection contact 25C of the signal selection unit 25, and the selection control signal SS from the timing signal formation unit 21 is supplied.
Is high, therefore, the identification signal CM from the interlaced state identifying unit 23 has a negative polarity, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal is input to the video signal input terminal 11. When the signal SV1 is being supplied, the 1/2 line period digital video signal DX1 from the line memory unit 15 is supplied to the selection contact 25C of the signal selecting unit 25 and at the same time 1 / from the frame memory unit 16 is supplied. The operation of supplying the digital video signal DX2 to the selection contact 25A of the signal selection unit 25 during the 2-line period is performed. Then, the digital image mute signal DM from the image mute signal generation unit 26 is supplied to the selection contact 25B provided between the selection contact 25A and the selection contact 25C in the signal selection unit 25.

The signal selecting section 25 is controlled by both the selection control signal SM and the selection control signal SN from the timing signal forming section 21. The identification signal CM from the interlaced state identifying section 23 has a positive polarity, and the video signal SV1 is supplied to the video signal input terminal 10 and the video signal SV2 is supplied to the video signal input terminal 11. When in the state, the timing signal forming unit 2
The selection control signal SM from 1 is supplied to the signal selection unit 25. In the signal selection section 25 to which the selection control signal SM is supplied, the movable contact 25 is provided only for approximately 1/2 line period in the video signal SV1 in the periods corresponding to the odd field period and the even field period of the video signal SV1.
D is connected to the selection contact 25A, then the movable contact 25D is connected to the selection contact 25B for an extremely short time, and further, the movable contact 25D is connected to the selection contact 25C for about 1/2 line period in the video signal SV1. The condition is repeated.

As a result, in the signal selection section 25,
Corresponding to each odd field period in the video signal SV1, the 1/2 line period digital video signal DX1 supplied to the selection contact 25A is taken out to the movable contact 25D for about 1/2 line period, and subsequently, the selection contact. 25B
After the image mute signal DM supplied to the movable contact 25D is taken for an extremely short time, the 1/2 line period digital video signal DX2 from the field memory unit 17 in the frame memory unit 16 is supplied to the selection contact 25C.
The state in which O is taken out to the movable contact 25D is repeated only for about 1/2 line period. Thereby, the signal selection unit 25
A digital video signal for an odd field period can be obtained at the movable contact 25D at.

Further, 1 is supplied to the selection contact 25A corresponding to each even field period in the video signal SV1.
/ 2 line period digital video signal DX1 is taken out to the movable contact 25D only for about 1/2 line period, and subsequently the image mute signal DM is supplied to the selection contact 25B.
After being taken out to the movable contact 25D for an extremely short period of time, the 1/2 line period digital video signal DX2E from the field memory unit 18 in the frame memory unit 16 supplied to the selection contact 25C is moved only for about 1/2 line period. The state of being taken out to 25D is repeated. As a result, the movable contact 25D in the signal selection unit 25 can obtain a digital video signal for an even field period.

On the other hand, the identification signal CM from the interlaced state identifying section 23 has a negative polarity, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal is input to the video signal input terminal 11. When the SV1 is being supplied, the timing signal forming unit 21
To supply the selection control signal SN to the signal selection unit 25.
In the signal selection section 25 to which the selection control signal SN is supplied, the video signal S in the period corresponding to each of the odd field period and the even field period of the video signal SV1.
The movable contact 25D is connected to the selection contact 25A only for about 1/2 line period in V1, and thereafter, the movable contact 25D is connected to the selection contact 25B for an extremely short time.
The state in which the movable contact 25D is connected to the selection contact 25C is repeated only for about 1/2 line period in the video signal SV1.

As a result, in the signal selection section 25,
The frame memory unit 16 supplied to the selection contact 25A corresponding to each odd field period in the video signal SV1.
The half-line period digital video signal DX2O from the field memory unit 17 is taken out to the movable contact 25D for about a half-line period, and subsequently, the image mute signal DM supplied to the selection contact 25B is extremely short. After being taken out to the movable contact 25D, the selection contact 25C
1/2 line period digital video signal DX supplied to
The state in which 1 is taken out to the movable contact 25D is repeated only for about 1/2 line period. Thereby, the signal selection unit 25
A digital video signal for an odd field period can be obtained at the movable contact 25D at.

Further, the 1/2 line period digital video signal DX2E from the field memory unit 18 in the frame memory unit 16 supplied to the selection contact 25A is approximately 1/2 corresponding to each even field period in the video signal SV1. 1/2 line which is taken out to the movable contact 25D only for a line period, and subsequently, the image mute signal DM supplied to the selected contact 25B is taken out to the movable contact 25D for an extremely short time and then supplied to the selected contact 25C. The state in which the period digital video signal DX1 is taken out to the movable contact 25D is repeated only for about 1/2 line period. Thereby, the movable contact 25 in the signal selection unit 25
At D, a digital video signal for an even field period is obtained.

In this way, the identification signal CM from the interlaced state identifying section 23 has a positive polarity, the video signal SV1 is supplied to the video signal input terminal 10, and the video signal is input to the video signal input terminal 11. When the SV2 is being supplied and the identification signal CM from the interlaced state identifying section 23 has a negative polarity, the video signal SV2 is supplied to the video signal input terminal 10 and the video signal input is made. When the video signal SV1 is supplied to the terminal 11, the digital video signal for the odd field period and the digital video signal for the even field period, which are derived to the movable contact 25D of the signal selection unit 25, are generated. , Is supplied to the digital / analog converter (D / A converter) 27 for analogization, and a two-screen image display is performed. It is a video signal SZ.

The video signal SZ for dual-screen image display obtained from the D / A converter 27 is a low pass filter (LPF) 2
After the noise component is removed through 8, the image is supplied to the dual-screen image display unit 29. The two-screen image display unit 29 has an image display surface on which line scanning and field scanning are performed, and on the image display surface, a screen of an image represented by the video signal SV1 and a screen of an image represented by the video signal SV2. And are formed to be arranged adjacent to each other in the left-right direction across the image mute portion based on the digital image mute signal DM, which forms a boundary line extending in the vertical direction. That is, the two-screen image display unit 29 performs the two-screen image display based on the two-screen image display video signal SZ, and the identification signal CM from the interlaced state identification unit 23.
Has a positive polarity, the video signal SV1 is supplied to the video signal input terminal 10, and the video signal input terminal 1
When the video signal SV2 is being supplied to the first video signal SV1, the video signal SV1 is displayed on the left side of the two screens divided by the vertical line image mute section ZM based on the digital image mute signal DM, as shown in FIG. The image I represented is displayed, and the image N represented by the video signal SV2 is displayed on the right side of the two screens.
Further, the identification signal C from the interlaced state identification unit 23
When M has a negative polarity and the video signal SV2 is supplied to the video signal input terminal 10 and the video signal SV1 is supplied to the video signal input terminal 11, as shown in FIG. , The image N represented by the video signal SV2 is displayed on the left side of the two screens divided by the vertical line image mute section ZM based on the digital image mute signal DM, and the video signal SV1 is displayed on the right side of the two screens. The image I shown is displayed.

Therefore, in the dual-screen image displayed on the dual-screen image display unit 29 in this way, the image I represented by the video signal SV1 which is the interlaced signal is divided into the odd field period and the odd field period which form each frame period. It is avoided that it is based on only one of the even field periods, and it is always based on both the odd field period and the even field period forming each frame period thereof. As a result, each of the two images forming the two-screen image can be properly obtained without the movement being unnatural. The dual-screen image displayed on the dual-screen image display unit 29 is always arranged on the left side of the image represented by the video signal SV1 or SV2 supplied to the video signal input terminal 10, and at the video signal input terminal 11. The image represented by the supplied video signal SV2 or SV1 is arranged on the right side, and the situation in which the user of the apparatus is confused can be avoided.

Under the circumstances, the video signal selection control unit 12,
The portion including the timing signal forming unit 21, the interlaced state identifying unit 23, and the like outputs the video signal SV1 that is the interlaced signal of the video signals SV1 and SV2 supplied to the video signal input terminals 10 and 11. ,
A signal transmission control unit that controls the transmission state of the video signals SV1 and SV2 is configured so that the first video signal is always supplied to the A / D conversion unit 13.

[0055]

As is apparent from the above description, in the image display device according to the present invention, a plurality of line periods included in each frame period of the first video signal are stored in the line memory section. A first time-axis compressed signal is obtained by performing time-axis compression using the plurality of line periods included in each frame period of the second video signal, and the first video is output using the frame memory unit. By performing time-axis compression at a timing synchronized with the synchronization signal of the signal, obtaining a second time-axis compression signal synchronized with the first time-axis compression signal, and combining the first and second time-axis compression signals In obtaining the two-screen image display video signal, when one of the two video signals to be the first and second video signals is a non-interlaced signal and the other is an interlaced signal, two video signals are always provided. Those ones of who is an interlaced signal to be the first video signal, the transmission control for the two video signals is carried out. As a result, the obtained two-screen image display video signal is formed with the interlace signal of the two video signals as the first and second video signals being the reference. .

Therefore, in the two-screen image displayed by the two-screen image display section according to such a two-screen image display video signal, the image represented by the first video signal which is the interlaced signal is It is avoided that the situation is based on only one of the odd field period and the even field period forming each frame period, and the odd field period and the even number forming each frame period are always avoided. Based on both of the field period, the two images forming the two-screen image can be properly obtained without the movement being unnatural.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an example of an image display device according to the present invention.

FIG. 2 is a time chart used for explaining the operation of the example shown in FIG.

FIG. 3 is a time chart used for explaining the operation of the example shown in FIG.

FIG. 4 is a conceptual diagram showing a dual-screen image display state provided for explaining the operation of the example shown in FIG.

FIG. 5 is a conceptual diagram showing a dual-screen image display state provided for explaining the operation of the example shown in FIG.

FIG. 6 is a time chart used for explaining time-axis compression of a video signal using a line memory.

FIG. 7 is a time chart provided for explaining time-axis compression of a video signal using a frame memory.

[Explanation of symbols]

 10, 11 Video signal input terminal 12 Video signal selection control unit 13, 14 A / D conversion unit 15 Line memory unit 16 Frame memory unit 17, 18 Field memory unit 19, 20 Sync signal separation unit 21, 22 Timing signal forming unit 23 Interlaced state identification unit 24 Digital video signal selection control unit 25 Signal selection unit 26 Image mute signal generation unit 27 D / A conversion unit 28 LPF 29 Dual screen image display unit

Claims (6)

[Claims] 1. A first and second video signal input terminal to which two video signals, which are a first video signal and a second video signal, are supplied, and the first video signal is sequentially provided for one line period. While being written, each line period of the written first video signal is read and formed within a time period corresponding to a half line period of the first video signal.
A line memory unit in which video signals for two line periods are sequentially obtained, and a state in which the second video signal is sequentially written for each one frame period consisting of an odd field period and an even field period are continuous. At the same time, the line period included in each frame period of the written second video signal is read out intermittently within a time period corresponding to approximately 1/2 line period of the first video signal. The second 1 /
A frame memory unit that sequentially obtains video signals for two line periods, and a first 1/2 line obtained from the line memory unit for each period corresponding to each line period of the first video signal. A video signal for a period and a video signal for a second 1/2 line period obtained from the frame memory section to selectively extract a video signal for display; and a signal selecting section from the signal selecting section A two-screen image display unit that displays two-screen images corresponding to the image based on the first video signal and the image based on the second video signal according to the obtained display video signal; When one of the two video signals supplied to the second video signal input end is a non-interlaced signal and the other is an interlaced signal, one of the two video signals which is an interlaced signal To form a constantly said first video signal, the image display device configured and a signal transmission control unit for controlling the transmission status of the two video signals. 2. The signal transmission control unit is a non-interlaced signal or an interlaced signal for each of the video signal supplied to the first video signal input end and the video signal supplied to the second video signal input end. An interlace state identifying section for identifying whether the signal is a signal and issuing an identification output signal indicating an identification result, and supplying to the first video signal input end section in accordance with the identification output signal obtained from the interlace state identifying section. Characterized in that a selected video signal is a first video signal and a video signal supplied to the second video signal input end is a first video signal. The image display device according to claim 1. 3. A signal transmission control section supplies, to a line memory section, one of the two video signals supplied to the first and second video signal input terminals, which is an interlaced signal. 7. A video signal selection control unit for performing selection control for the two video signals in order to supply one of the two video signals which is a non-interlaced signal to the frame memory unit. 1. The image display device according to 1. 4. The signal transmission control unit is a non-interlaced signal or an interlaced signal for each of the video signal supplied to the first video signal input end and the video signal supplied to the second video signal input end. The video signal selection control unit includes an interlace state identification unit that identifies whether the signal is a signal and outputs an identification output signal that represents an identification result, and the video signal selection control unit determines the first and the second output signals according to the identification output signal obtained from the interlace state identification unit. 4. The image display device according to claim 3, wherein selection control is performed for two video signals supplied to the second video signal input terminal. 5. The signal selection unit displays the video signal for display, and an image based on the video signal supplied to the first video signal input end is one of the two-screen images displayed by the two-screen image display unit. The image display device according to claim 1, wherein the image display device is formed so as to be obtained as one of the arrangement positions specified. 6. A period corresponding to each line period of the first video signal when the video signal supplied to the first video signal input end is the first video signal. Each time, a video signal for the first 1/2 line period obtained from the line memory unit and a video signal for the second 1/2 line period obtained from the frame memory unit are sequentially taken out, and When the video signal supplied to the second video signal input terminal is the first video signal, the second video signal is supplied for each period corresponding to each line period of the first video signal.
6. The image display device according to claim 5, wherein the image signal for the 1/2 line period and the image signal for the first 1/2 line period are sequentially taken out.