JPH0965660A - Method for controlling system interconnection inverter - Google Patents
Method for controlling system interconnection inverterInfo
- Publication number
- JPH0965660A JPH0965660A JP7213549A JP21354995A JPH0965660A JP H0965660 A JPH0965660 A JP H0965660A JP 7213549 A JP7213549 A JP 7213549A JP 21354995 A JP21354995 A JP 21354995A JP H0965660 A JPH0965660 A JP H0965660A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- voltage
- signal
- phase
- active power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 6
- 230000007704 transition Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
- Inverter Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、自励式無効電力補
償装置やアクティブフィルタ、分散電源等に使用される
系統連系インバータの制御方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for a grid-connected inverter used in a self-excited reactive power compensator, an active filter, a distributed power source, etc.
【0002】[0002]
【従来の技術】電力系統の負荷変動に伴う電圧変動を抑
制する自励式無効電力補償装置に使用される系統連系イ
ンバータの主回路例を、図2に基づき説明すると、系統
連系インバータ4はその直流側にインバータ直流電源部
5を備える。インバータ直流電源部5は、初期充電用整
流回路や太陽電池の分散電源回路であり、図2では補機
電源9の交流電圧を開閉器8の閉成時だけ整流して直流
コンデンサ6を定格のインバータ直流電圧ED に充電す
る初期充電用整流回路7が示される。インバータ4は、
系統電源1を有する電力系統に連系用遮断器3を介して
次のように連系される。2. Description of the Related Art An example of a main circuit of a grid-connected inverter used in a self-excited reactive power compensator for suppressing voltage fluctuations due to load fluctuations of a power system will be described with reference to FIG. An inverter DC power supply unit 5 is provided on the DC side. The inverter DC power supply unit 5 is a rectification circuit for initial charging and a distributed power supply circuit for solar cells. In FIG. 2, the AC voltage of the auxiliary power supply 9 is rectified only when the switch 8 is closed, and the DC capacitor 6 is rated. An initial charging rectifier circuit 7 is shown which charges the inverter DC voltage E D. The inverter 4 is
The power system having the system power supply 1 is interconnected via the interconnection breaker 3 as follows.
【0003】遮断器3を開放して開閉器8を閉じ、整流
回路7で直流コンデンサ6を充電して定格のインバータ
直流電圧ED が確立されると、インバータ4を起動さ
せ、そのインバータ出力電圧VI が系統電圧VS と同
相、同振幅になった時点で、遮断器3を投入して連系が
行われる。この連系後、開閉器8が開放され、インバー
タ出力電圧VI とインバータ電流Iで定まる有効電力P
がインバータ4に流入してインバータ直流電圧ED が定
格に制御され、インバータ内部損失電力が補充される。When the circuit breaker 3 is opened and the switch 8 is closed, the DC capacitor 6 is charged by the rectifier circuit 7 and the rated inverter DC voltage E D is established, the inverter 4 is started and the inverter output voltage When V I has the same phase and the same amplitude as the system voltage V S , the circuit breaker 3 is closed to establish interconnection. After this interconnection, the switch 8 is opened, and the active power P determined by the inverter output voltage V I and the inverter current I
Flows into the inverter 4, the inverter DC voltage E D is controlled to the rated value, and the inverter internal power loss is replenished.
【0004】即ち、電力系統の系統インピーダンス2
(抵抗分Rとリアクタンス分jX)においては、R≪j
Xである関係で、系統電圧VS に対して90゜位相差の
電圧△Vをインバータ出力電圧VI にて調整することに
より、インバータ4に流入する有効電力Pが制御され、
インバータ直流電圧ED が定格に調整される。ここで系
統電圧VS とインバータ出力電圧VI の位相差をθとす
ると、I∝P∝θ∝△Vなる関係が維持されて、有効電
力Pは位相調整で制御され、この位相調整でインバータ
直流電圧ED が調整される。That is, the system impedance 2 of the power system
(Resistance R and reactance jX), R << j
In relation to X, the active power P flowing into the inverter 4 is controlled by adjusting the voltage ΔV having a 90 ° phase difference with respect to the system voltage V S by the inverter output voltage V I.
The inverter DC voltage E D is adjusted to the rating. Here, if the phase difference between the system voltage V S and the inverter output voltage V I is θ, the relationship of I∝P∝θ∝ΔV is maintained, and the active power P is controlled by the phase adjustment. The DC voltage E D is adjusted.
【0005】インバータ直流電圧ED の調整を行う図3
の制御ブロックを説明すると、同図の制御系は、遮断器
3が投入されてインバータ4が系統連系されてから、イ
ンバータ直流電圧ED の制御を開始する。インバータ直
流電圧ED とその直流電圧指令信号ED REFの誤差信号を
減算器10で求め、この誤差信号を直流電圧制御回路1
1に入力する。直流電圧制御回路11は、入力された誤
差信号が小さくなるように制御して、入力に対応した振
幅調整用出力信号gE を乗算器12に出力する。一方、
系統電圧VS の位相を90゜位相器13で90゜遅らせ
た位相信号VS'を乗算器12に入力して、これを振幅調
整用出力信号gE で振幅調整したインバータ有効電力制
御信号VE [VE =gE VS']を得る。このインバータ
有効電力制御信号VE は、上記位相差θを調整する電圧
△Vに相当する。FIG. 3 for adjusting the inverter DC voltage E D
The control system of FIG. 1 starts controlling the inverter DC voltage E D after the circuit breaker 3 is turned on and the inverter 4 is system-interconnected. The error signal between the inverter DC voltage E D and its DC voltage command signal E D REF is obtained by the subtractor 10, and this error signal is calculated by the DC voltage control circuit 1
Enter 1 The DC voltage control circuit 11 controls so that the input error signal becomes small, and outputs the amplitude adjustment output signal g E corresponding to the input to the multiplier 12. on the other hand,
The phase signal V S ′ obtained by delaying the phase of the system voltage V S by 90 ° by the 90 ° phase shifter 13 is input to the multiplier 12, and the inverter active power control signal V whose amplitude is adjusted by the amplitude adjustment output signal g E. We obtain E [V E = g E V S ']. The inverter active power control signal V E corresponds to the voltage ΔV for adjusting the phase difference θ.
【0006】而して、インバータ有効電力制御信号VE
と系統電圧VS とインバータ出力電流を得るための電圧
信号VC とを加算器15で加算して、インバータ出力電
圧指令信号VI REFを得る。電圧信号VC は、インバータ
電流指令信号IREF を電圧信号変換回路14で電圧変換
したVC =(R+jX)IREF なる信号である。加算器
15からのインバータ出力電圧指令信号VI REFが図示し
ないPWM回路(パルス幅変調回路)に出力されて、イ
ンバータ4が起動する。Thus, the inverter active power control signal V E
And the system voltage V S and the voltage signal V C for obtaining the inverter output current are added by the adder 15 to obtain the inverter output voltage command signal V I REF . The voltage signal V C is a signal of V C = (R + jX) I REF obtained by converting the inverter current command signal I REF into voltage by the voltage signal conversion circuit 14. The inverter output voltage command signal V I REF from the adder 15 is output to a PWM circuit (pulse width modulation circuit) not shown, and the inverter 4 is activated.
【0007】上記インバータ制御において、インバータ
直流電圧ED が定格より下がって直流電圧指令信号ED
REFとの誤差が大きくなると、その誤差に応じてインバ
ータ有効電力制御信号VE が増大し、インバータ4に流
入する有効電力Pが増大する。その結果が直流電圧ED
の増加に反映され、最終的にED =ED REFとなるように
フィードバック制御される。In the above inverter control, the inverter DC voltage E D falls below the rated value and the DC voltage command signal E D
When the error with REF increases, the inverter active power control signal V E increases in accordance with the error, and the active power P flowing into the inverter 4 increases. The result is DC voltage E D
Is reflected in the increase of ED and is finally feedback-controlled so that E D = E D REF .
【0008】[0008]
【発明が解決しようとする課題】遮断器3を投入してイ
ンバータ4を系統連系させるとき、インバータ出力電圧
VI と系統電圧VS の位相を一致させているが、インバ
ータ主回路やPWM回路のスイッチング素子のオンオフ
動作ズレ等の影響でインバータ出力電圧VI とインバー
タ出力電圧指令信号VI REFが一致せず、インバータ出力
電圧VI の位相が系統電圧VS の位相より若干遅れるこ
とがある。このような位相誤差が有る段階でインバータ
4を系統連系させると、直流電圧制御回路11が定常状
態になってED =ED REFのフィードバック制御が働くま
での過渡期に、インバータ出力電圧VI と系統電圧VS
の位相差による有効電力がインバータ4に流入して、イ
ンバータ4の直流側を過電圧状態にする不具合が発生す
ることがあった。When the circuit breaker 3 is turned on to connect the inverter 4 to the system, the inverter output voltage V I and the system voltage V S are in phase with each other. The inverter output voltage V I and the inverter output voltage command signal V I REF do not match due to the on / off operation shift of the switching element of the above, and the phase of the inverter output voltage V I may be slightly behind the phase of the system voltage V S. . If the inverter 4 is grid-connected at the stage where there is such a phase error, the inverter output voltage V will be changed during the transition period until the DC voltage control circuit 11 enters the steady state and the feedback control of E D = E D REF works. I and system voltage V S
The active power due to the phase difference of 1 may flow into the inverter 4, causing a problem that the DC side of the inverter 4 is brought into an overvoltage state.
【0009】即ち、連系時の過渡期にインバータ4に有
効電力が流入すると、流入した有効電力は整流回路7で
遮断された形となって直流コンデンサ6をチャージアッ
プし、その結果、インバータ直流電圧ED が異常に上昇
する直流過電圧状態となり、このような場合、過電圧保
護リレーが動作して無効電力補償装置等の装置故障が生
じる可能性があって、系統連系時での信頼性に問題があ
った。That is, when active power flows into the inverter 4 during the transition period during interconnection, the active power that has flowed in is cut off by the rectifier circuit 7 to charge up the DC capacitor 6, resulting in inverter DC. The DC overvoltage state in which the voltage E D rises abnormally causes the overvoltage protection relay to operate, which may cause a device failure such as a reactive power compensator. There was a problem.
【0010】それ故に、本発明の目的とするところは、
系統連系インバータを常に安定させて連系させる制御方
法を提供することにある。Therefore, the object of the present invention is to
It is an object of the present invention to provide a control method for always stabilizing and interconnecting a grid interconnection inverter.
【0011】[0011]
【課題を解決するための手段】本発明は、初期充電用整
流回路等のインバータ直流電源部で与えられる定格のイ
ンバータ直流電圧を交流変換する系統連系インバータに
おいて、連系時のインバータ出力電圧位相が系統電圧位
相に遅れないようにするため、インバータ直流電圧を一
定に制御する直流電圧制御回路の出力信号に、連系前に
インバータ出力電圧位相を系統電圧より進めるマニュア
ル調整可能な位相バイアス信号を加算し、この加算信号
と系統電圧を90゜位相遅らせた信号を乗じた交流信号
をインバータ有効電力制御信号とすることで、連系時に
インバータ直流電源部の容量範囲で有効電力を流出する
モードになるようにしたことを特徴とする。SUMMARY OF THE INVENTION The present invention relates to a grid-connected inverter for AC-converting a rated inverter DC voltage provided by an inverter DC power supply unit such as an initial charging rectifier circuit. In order to prevent the delay in the system voltage phase, a manually adjustable phase bias signal that advances the inverter output voltage phase from the system voltage before the interconnection is added to the output signal of the DC voltage control circuit that constantly controls the inverter DC voltage. By adding this signal and multiplying this added signal by a signal that is 90 ° phase delayed from the system voltage, and using it as an inverter active power control signal, the mode in which active power flows out within the capacity range of the inverter DC power supply during interconnection is set. It is characterized in that
【0012】ここで、上記の位相バイアス信号は、連系
前にインバータ出力電圧とその指令信号の位相誤差を計
測する等して必要に応じて直流電圧制御回路の出力信号
に加算され、この加算でもって連系時のインバータ出力
電圧が系統電圧に対して進んだ位相状態となり、連系時
に有効電力を流出するモードが設定される。Here, the above phase bias signal is added to the output signal of the DC voltage control circuit as needed by measuring the phase error between the inverter output voltage and its command signal before interconnection, and this addition is performed. Therefore, the inverter output voltage at the time of interconnection becomes a phase state advanced with respect to the system voltage, and a mode is set in which active power flows out at the time of interconnection.
【0013】[0013]
【発明の実施の形態】図1に本発明方法による系統連系
インバータ4の制御ブロックを示すと、これは基本的に
図3の制御ブロックと同様でよい。本発明においては、
直流電圧制御回路11と乗算器12の間に加算器17を
追加設置し、この加算器17で直流電圧制御回路11の
出力信号gE にマニュアル調整可能な位相バイアス信号
gC を必要に応じて加算することを特徴とする。直流電
圧制御回路11の出力信号gEと位相バイアス信号gC
の加算信号gE'[gE 、又は、(gE +gC )]と、系
統電圧VS の位相を90゜位相器13で90゜遅らせた
位相信号VS'が乗算器12で乗算されて振幅調整された
インバータ有効電力制御信号VE が得られる。FIG. 1 shows a control block of a grid interconnection inverter 4 according to the method of the present invention, which may be basically the same as the control block of FIG. In the present invention,
An adder 17 is additionally installed between the DC voltage control circuit 11 and the multiplier 12, and a manually adjustable phase bias signal g C is added to the output signal g E of the DC voltage control circuit 11 by the adder 17 as required. It is characterized by adding. The output signal g E of the DC voltage control circuit 11 and the phase bias signal g C
The addition signal g E '[g E or (g E + g C )] is multiplied by the phase signal V S ′ obtained by delaying the phase of the system voltage V S by 90 ° by the 90 ° phase shifter 13 by the multiplier 12. And the amplitude-adjusted inverter active power control signal V E is obtained.
【0014】位相バイアス信号gC は、インバータ4の
系統連系時のインバータ出力電圧V I の位相が系統電圧
VS の位相に遅れないようにする位相調整信号で、仮に
連系時にインバータ出力電圧VI が系統電圧より位相遅
れの状態にあると、位相バイアス信号gC の加算でイン
バータ出力電圧VI の位相が系統電圧VS の位相に一致
するように進められる。直流電圧制御回路11の出力信
号gE への位相バイアス信号gC の加算は、インバータ
製造後で例えばインバータ出荷時に製造メーカによって
必要に応じ行われる。Phase bias signal gC Of the inverter 4
Inverter output voltage V during grid connection I Is the system voltage
VS It is a phase adjustment signal that does not delay the phase of
Inverter output voltage V during interconnectionI Is later in phase than the system voltage
In this state, the phase bias signal gC Add in
Barter output voltage VI Is the system voltage VS Match the phase of
To proceed. Output signal of DC voltage control circuit 11
No. gE Phase bias signal g toC Addition of the inverter
After manufacturing, for example, when the inverter is shipped,
It is done as needed.
【0015】即ち、インバータ出荷の段階でインバータ
出力電圧VI とインバータ出力電圧指令信号VI REFの位
相ズレの有無を実測して調べる。そして、この調査で系
統連系時にインバータ出力電圧VI の位相が系統電圧V
S と一致すると判断されると、位相バイアス信号gC の
加算は必要無いと判断されて加算することなく出荷され
る。また、上記調査で系統連系時にインバータ出力電圧
VI の位相が系統電圧VS より遅れると判断されると、
位相バイアス信号gC の加算が手動で行われ、位相バイ
アス信号gC を加算したまま出荷される。That is, at the stage of shipping the inverter, the presence / absence of a phase shift between the inverter output voltage V I and the inverter output voltage command signal V I REF is measured and checked. In this investigation, the phase of the inverter output voltage V I during grid connection is the system voltage V I.
If it is determined that the value of S coincides with S , it is determined that the addition of the phase bias signal g C is unnecessary, and the product is shipped without addition. Further, if it is determined in the above survey that the phase of the inverter output voltage V I is delayed from the system voltage V S during system interconnection,
The phase bias signal g C is added manually, and the phase bias signal g C is added and shipped.
【0016】位相バイアス信号gC の加算により、イン
バータ4は連系時においてインバータ出力電圧VI の位
相が系統電圧VS に対して常に進んだ状態から動作す
る。そのため、インバータ4はその連系時の過渡期に有
効電力を流出するモードとなって、連系過渡期における
有効電力流入を抑制し、インバータ直流過電圧発生が回
避される。位相バイアス信号gC の加算により連系過渡
期にインバータ4から出力される有効電力は、インバー
タ直流電源部5の容量の範囲内にマニュアル設定され
る。The addition of the phase bias signal g C causes the inverter 4 to operate from the state in which the phase of the inverter output voltage V I is always advanced with respect to the system voltage V S during interconnection. Therefore, the inverter 4 is in a mode in which active power flows out during the transition period of the interconnection, so that the inflow of active power during the interconnection transition period is suppressed and the generation of the inverter DC overvoltage is avoided. The active power output from the inverter 4 during the interconnection transition period by adding the phase bias signal g C is manually set within the capacity of the inverter DC power supply unit 5.
【0017】[0017]
【発明の効果】本発明によれば、既存の直流電圧制御回
路とは別に、マニュアル調整可能な位相バイアス信号の
マニュアル調整でインバータ出力電圧の位相調整が可能
となるため、電力系統への連系時のインバータ出力電圧
位相を系統電圧に対して所望量だけ進めて、連系の過渡
期にインバータから有効電力を出力するモードに設定す
ることにより、連系過渡期に有効電力流入による直流過
電圧が防止できて、常に安定した系統連系が実行できる
ようになる。According to the present invention, in addition to the existing DC voltage control circuit, the phase of the inverter output voltage can be adjusted by manual adjustment of the manually adjustable phase bias signal. By advancing the inverter output voltage phase at the desired time by a desired amount with respect to the system voltage and setting the mode to output active power from the inverter during the transition period of interconnection, DC overvoltage due to active power inflow during the transition period of interconnection is set. It is possible to prevent it, and to always realize stable grid interconnection.
【0018】また、既設のインバータ装置の一部にマニ
ュアルによる位相バイアス信号を加算する簡単な加算回
路を追加設置するだけで実施できるので、既存設備への
適用が容易であり、設備投資的に有利に実施できる。Further, since it can be implemented only by additionally installing a simple adder circuit for adding the phase bias signal by manual to a part of the existing inverter device, it can be easily applied to the existing equipment and is advantageous in terms of equipment investment. Can be carried out.
【図1】本発明制御方法における制御ブロック図。FIG. 1 is a control block diagram in the control method of the present invention.
【図2】系統連系インバータの主回路図。FIG. 2 is a main circuit diagram of a grid interconnection inverter.
【図3】従来の系統連系インバータの制御方法の制御ブ
ロック図。FIG. 3 is a control block diagram of a conventional method for controlling a grid interconnection inverter.
4 系統連系インバータ 5 インバータ直流電源部 11 直流電圧制御回路 4 system interconnection inverter 5 inverter DC power supply unit 11 DC voltage control circuit
Claims (1)
のインバータ直流電圧を交流変換する系統連系インバー
タにおいて、インバータ直流電圧を一定に制御する直流
電圧制御回路の出力信号に、連系前にインバータ出力電
圧位相を系統電圧より進めるマニュアル調整可能な位相
バイアス信号を加算し、この加算信号と系統電圧を90
゜位相遅らせた信号を乗じた交流信号をインバータ有効
電力制御信号とすることで、連系時にインバータ直流電
源部の容量範囲で有効電力を流出するモードとなるよう
にしたことを特徴とする系統連系インバータの制御方
法。1. In a system interconnection inverter for converting an inverter DC voltage of a rating given by an inverter DC power supply unit into an AC, the output signal of a DC voltage control circuit for controlling the inverter DC voltage at a constant level is output to the inverter output before interconnection. Add a manually adjustable phase bias signal that advances the voltage phase from the system voltage, and add this added signal and the system voltage to 90
° The AC active signal that is multiplied by the phase-delayed signal is used as the inverter active power control signal so that the active power can be discharged in the capacity range of the inverter DC power supply during interconnection. System inverter control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7213549A JPH0965660A (en) | 1995-08-22 | 1995-08-22 | Method for controlling system interconnection inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7213549A JPH0965660A (en) | 1995-08-22 | 1995-08-22 | Method for controlling system interconnection inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0965660A true JPH0965660A (en) | 1997-03-07 |
Family
ID=16641047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7213549A Withdrawn JPH0965660A (en) | 1995-08-22 | 1995-08-22 | Method for controlling system interconnection inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0965660A (en) |
-
1995
- 1995-08-22 JP JP7213549A patent/JPH0965660A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20021105 |