JPH0969580A - Bi-cmos semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the parasitic MOS capacity of a bipolar transistor used for Bi-CMOS. SOLUTION: A low-concentration n-type collector region 107a is provided on the surface of an n well 104B between a field oxide film 102 and a p-type external base region 111 and a base electrode 109C which is connected to the p-type external base region 111 is provided on the low-concentration n-type collector region 107a via a gate oxide film 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Bi-CMOS semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In a Bi-CMOS semiconductor device in which a bipolar transistor which operates at high speed and has a high load current driving capability and a CMOS transistor which has low power consumption and high integration degree are formed on the same semiconductor substrate, higher speed is achieved. There is a demand for a structure that enables various operations and a simplified manufacturing method for realizing this structure. As an example thereof, there is a Bi-CMOS semiconductor device obtained by a manufacturing method using a self-alignment technique such as forming an emitter electrode and a base electrode of a bipolar transistor in a self-aligned manner using a polycrystalline silicon film. Referring to FIG. 9, which is a schematic sectional view of the Bi-CMOS semiconductor device, the structure of such a Bi-CMOS semiconductor device is as follows.

On the surface of the p-type silicon substrate 201, the depth is about 0.7 to 1.0 μm and the impurity concentration is 8 × 10 ¹⁶ to.
4 × 10 ¹⁷ cm ^-3 of about p-well 203, each impurity concentration of 8 × 10 ¹⁶ ~4 × 10 ¹⁷ In each about 0.7~1.0μm junction depth cm ^-3 of about n-well 20
4A and 204B are provided. A first element formation region is provided on the surface of the p well 203, a second element formation region is provided on the surface of the n well 204A, and third and fourth element formation regions are provided on the surface of the n well 204B. The formation region is surrounded by the field oxide film 202 having a film thickness of about 300 to 400 nm.

An nMOS transistor is provided in the first element formation region of the p well 203. These n
In the MOS transistor, the first element formation region is self-aligned with the gate electrode 209A that crosses the surface of the p-well 203 through the gate oxide film 206 having a thickness of about 5 to 10 nm, and the field oxide film 202 and the gate electrode 209A. High-concentration n-type source / drain region 2 provided on the surface
It consists of 12. The gate electrode 209A is made of a high-concentration n-type polycrystalline silicon film, has a gate length of about 0.4 μm and a gate width of about 5 to 10 μm. The side surface and the upper surface of the gate electrode 209A are covered with an insulating film spacer 208 and an insulating film 217, respectively. The junction depth of the n-type source / drain region 212 is about 0.15 μm. The surface impurity concentration of the p-well 203 is such that the threshold voltage (V _TN ) of these nMOS transistors is 0.
It is adjusted to be about 5 to 0.8V.

A pMOS transistor is provided in the second element formation region of the n well 204A. These p
The MOS transistor has a gate electrode 209B which crosses over the surface of the n-well 204A via a gate oxide film 206,
The high-concentration p-type source / drain regions 213 are provided on the surface of the second element formation region in a self-aligned manner with the field oxide film 202 and the gate electrode 209B. The gate electrode 209B is made of a high-concentration p-type polycrystalline silicon film, has a gate length of about 0.5 μm, and a gate width of 5 to 5.
It is about 10 μm. Also on the side surface and the upper surface of the gate electrode 209B, the insulating film spacer 208 and the insulating film 2 are formed, respectively.
Covered by 17. p-type source / drain region 2
The junction depth of 13 is about 0.2 μm. n-well 2
The surface impurity concentration of 04A (and the n-well 204B) depends on the threshold voltage (V
_TP ) is adjusted to be about -0.5 to -0.8V.

The n-well 204B includes the n-well 204B.
A vertical npn-type bipolar transistor having itself as a collector region is provided. A high-concentration n-type collector extraction region 205 is provided in the third element formation region of the n-well 204B. A base region and an emitter region are provided in the fourth element formation region of the n-well 204B, and the opening width of the fourth element formation region is, for example, about 1.6 μm. A base opening from which the gate oxide film 206 has been removed is provided on the surface of the n-well 204B in the fourth element formation region. The opening width (Wa) of the base opening portion is, for example, about 1.2 μm, and at this time, for example, 0.2 mm from the edge of the fourth element formation region.
The gate oxide film 206 is left with a width of about μm. On the surface of the n-well 204B in the fourth element formation region, a part of the base opening and the gate oxide film left there are covered with a base electrode 209C made of a high-concentration p-type polycrystalline silicon film. There is. The base electrode 209C extends up to the field oxide film 202 around the fourth element formation region, and the insulating film spacer 208 is formed on the side surface of the base electrode 209C on the field oxide film 202.
Is provided. The upper surface of the base electrode 209C is covered with the insulating film 217.

The base electrode 209C is provided with an emitter opening, and the opening width (Wc) of the emitter opening is provided.
Is, for example, about 0.6 μm. Therefore, the base electrode 209C is approximately (Wa-Wc) / 2 (for example, 0.3 μm).
(about m) and is in direct contact with the n-well 204B, and a high-concentration p-type external base region 211 (in self-alignment with the base electrode 209C) is formed on the surface of the n-well 204B in this direct contact. It is provided. The junction depth of the p-type external base region 211 is, for example, about 0.2 μm. The p-type external base region 211 is not in direct contact with the field oxide film 202. A p-type base region 215 self-aligned with the emitter opening is provided on the surface of the n-well 204B in the fourth element formation region. p
The junction depth of the mold base region 215 is, for example, 0.15 μm.
The p-type base region 215 is directly connected to the p-type external base region 211. Further, in the n-well 204B of the fourth element formation region, a high-concentration n-type SIC region 214 (SIC is Selective-Ion Implanted-Co) self-aligned with the emitter opening.
(abbreviation of collector) is provided. This high concentration n
The type SIC region 214 is at least the p-type base region 214.
Is in direct contact with the bottom surface of the high concentration n-type SIC region 2
The depth of 16 is, for example, about 0.6 to 0.7 μm.

Base electrode 20 forming the emitter opening
The side surface of 9C is covered with an insulating film spacer 218 having a width of, for example, about 0.1 μm. This insulating film spacer 2
Base electrode 209C covering the insulating film 217 through the insulating film 217.
And in the emitter opening, the surface of the n-well 204B in the fourth element formation region (p-type base region 215
An emitter electrode 221 is provided which is in direct contact with the The emitter electrode 221 is made of a high-concentration n-type polycrystalline silicon film. On the surface of the p-type base region 215, a high-concentration n-type emitter region 222 self-aligned with the emitter electrode 221 is provided. The junction depth of the n-type emitter region 222 is, for example, about 500 to 600 nm, and the n-type emitter region 222 is not in direct contact with the p-type external base region 211.

Referring to FIGS. 10 and 11 which are schematic sectional views of the manufacturing process of the Bi-CMOS semiconductor device, and FIG. 9 together, the Bi-CMOS semiconductor device is formed as follows.

First, in the element isolation region on the surface of the p-type silicon substrate 201, a film thickness of 300 to 4 is formed by, for example, a selective oxidation method.
A field oxide film 202 having a thickness of about 00 nm is formed. P-well 203 and n-wells 204A, 204 are formed in required regions by ion implantation with high acceleration energy.
Form B. The first element forming region is formed on the surface of the p well 203, the second element forming region is formed on the surface of the n well 204A, and the third and fourth element forming regions are formed on the surface of the n well 204B. It is formed by being surrounded by. N-well 204A including surface impurity concentration
And the n-well 204B have the same impurity concentration distribution,
The impurity concentration distributions of the n-wells 204A and 204B are set so as to match the V _TP of the pMOS transistor formed in the n-well 204A. This is because the manufacturing process is simplified and the performance of the pMOS transistor is given the highest priority (because the performance of the pMOS transistor is inferior to that of the bipolar transistor and the nMOS transistor).

Subsequently, a high-concentration n-type collector lead-out region 205 is formed on the surface of the n-well 204B in the third device-forming region by, for example, selectively implanting high-concentration phosphorus ions into the third device-forming region. To form. By the thermal oxidation method,
Gate oxide films 206 are formed on the surfaces of the second, third and fourth element formation regions, respectively. First, second and fourth
Oxide film 206 formed on the surface of the element formation region of
Is about 5 to 10 nm, but the gate oxide film formed on the surface of the third element formation region is thick (because it is formed on the surface of the n-type collector extraction region 205 of high concentration). Has become. 20-50 nm on the entire surface
A non-doped (first) polycrystalline silicon film 229 having a film thickness of about 3 nm is formed. Using the photoresist film 236 as a mask, the polycrystalline silicon film 22 on the fourth element formation region is formed.
9. The gate oxide film 206 is sequentially anisotropically etched,
A base opening having an opening width Wa is formed [FIG.
(A)]. The polycrystalline silicon film 229 is formed when the gate oxide film 206 is formed when the base opening is formed.
This is to prevent the contamination of.

Next, the photoresist film 236 is removed. A non-doped polycrystalline silicon film having a film thickness of about 100 to 300 nm is deposited on the entire surface, and as a result, a polycrystalline silicon film 239 in which this polycrystalline silicon film and the polycrystalline silicon film 229 are laminated is formed [FIG. b)]. Subsequently, this polycrystalline silicon film 239 is patterned to form polycrystalline silicon film patterns 239A, 239B, 2
39C is formed. Polycrystalline silicon film pattern 239A
Has a width of about 0.4 μm and is formed on the p-well 203 so as to cross the first element formation region. The polycrystalline silicon film pattern 239B has a width of about 0.5 μm, and the n-well 2 is formed so as to cross the second element formation region.
Formed on 04A. Polycrystalline silicon film pattern 23
9C is formed on the n-well 204B so as to cover the fourth element formation region including the base opening [FIG.
(C)].

Next, an insulating film (silicon oxide film or silicon nitride film) having a required thickness is formed on the entire surface, and the insulating film is etched back to form a polycrystalline silicon film pattern 239.
Insulating film spacers 208 are formed on the side surfaces of A, 239B, and 239C, respectively. A photoresist film 252 having an opening is formed in the p well 203. Using this photoresist film 252 as a mask, high concentration arsenic ion implantation is performed, and the arsenic ion implantation layer 2 is formed on the surface of the p well 203.
42 is formed. At this time, high-concentration arsenic is also implanted into the non-doped polycrystalline silicon film pattern 239A, which becomes the polycrystalline silicon film pattern 259A [FIG.
(D)].

After removing the photoresist film 252,
Photoresist film 25 covering the p-well 203 and the third element formation region (n-type collector lead-out region 205)
3 is formed. Ions of high concentration boron difluoride (BF ₂ ) are implanted using this photoresist film 253 as a mask to form a boron ion implantation layer 243 on the surface of the n-well 204A. At this time, high-concentration BF ₂ is also injected into the polycrystalline silicon film patterns 239B and 239C, respectively, and the polycrystalline silicon film patterns 259B and
It becomes 259C [FIG. 11 (a)].

After removing the photoresist film 253,
An insulating film 217 (silicon oxide film or silicon nitride film) having a film thickness of about 100 to 200 nm is formed on the entire surface by a low temperature vapor phase growth method. This insulating film 217 is intended to insulate and separate a base electrode and an emitter electrode which will be formed in a later step. The reason why the insulating film 217 is grown at a low temperature is to suppress the thermal diffusion of boron from the polycrystalline silicon film pattern 259C to the n well 204B at this stage. Next, a photoresist film 254 having an opening in the area where the emitter opening is to be formed is formed. Using the photoresist film 254 as a mask, the insulating film 217 and the polycrystalline silicon film pattern 259C are sequentially anisotropically etched to form an emitter opening having an opening width Wc. Then, using the photoresist film 254 as a mask, 200 to 400 keV,
Ion implantation of phosphorus of 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² is performed to form a phosphorus ion implantation layer 244 in the n well 204B immediately below the emitter opening. Furthermore, using the photoresist film 254 as a mask, 5 to 20 keV, 1 × 10 ¹³
Boron ions of ˜5 × 10 ¹³ cm ⁻² are implanted to form a boron ion implantation layer 245 on the surface of the n-well 204B immediately below the emitter opening [FIG. 11 (b)].

After removing the photoresist film 254,
An insulating film (silicon oxide film or silicon nitride film) having a film thickness of about 100 nm is formed on the entire surface by low temperature vapor phase epitaxy,
This insulating film is etched back to form a polycrystalline silicon film pattern 259C (and insulating film 217) in the emitter opening.
An insulating film spacer 218 is formed on the side surface. Subsequently, a non-doped third polycrystalline silicon film is formed on the entire surface, high-concentration arsenic is introduced into the third polycrystalline silicon film, and the third polycrystalline silicon film is patterned. afterwards,
A heat treatment is performed to activate phosphorus, boron and arsenic in the polycrystalline silicon film pattern and boron, phosphorus and the like in various ion-implanted layers. As a result, the polycrystalline silicon film pattern 259A becomes the gate electrode 209A (made of a high concentration n-type polycrystalline silicon film), and the polycrystalline silicon film pattern 259B (made of a high concentration p-type polycrystalline silicon film). The gate electrode 209B becomes, and the remaining polycrystalline silicon film pattern 259C becomes the base electrode 209C (made of a high-concentration p-type polycrystalline silicon film),
The pattern made of the third polycrystalline silicon film is an emitter electrode 2 (made of a high concentration n-type polycrystalline silicon film).
21. In addition, the arsenic ion-implanted layer 242 becomes the (high-concentration) n-type source / drain region 212, and boron.
The ion-implanted layer 243 becomes a (high-concentration) p-type source / drain region 213, and the phosphorus ion-implanted layer 244 has a high-concentration n.
The type SIC region 214 becomes the boron ion implantation layer 24.
5 is a p-type base region 215. Further, boron is diffused from the base electrode 209C, and a high concentration p-type external base region 211 is formed on the surface of the n well 204B.
Furthermore, arsenic is diffused from the emitter electrode, and a high concentration n-type emitter region 222 is formed on the surface of the p-type base region 215 in a self-aligned manner with the insulating film spacer 218 [FIG. 9].

The purpose of providing the high-concentration n-type SIC region 214 is to suppress the Kirk effect by adjusting the impurity concentration of the n-type collector region (n-well 204B) immediately below the n-type emitter region 222 in the npn-type bipolar transistor. This is to achieve (higher fT). In this bipolar transistor, the field oxide film 202 and n
It is separated from the mold emitter region 222 by, for example, about 0.6 μm. Therefore, the n-type emitter region 222 and the p-type base region 21 due to the stress caused by the field oxide film 202 are formed.
The effect on the junction of 5 is relaxed (a space of 0.4 μm or more is required), and the n-type emitter region 222 and the p-type base region 2 are
The characteristic abnormality of the base current with respect to the potential difference from 15 is avoided. Further, in this bipolar transistor, the p-type external base region 115 is separated from the edge of the field oxide film 202. This has two purposes. The first purpose is to reduce the junction capacitance between the p-type external base region 115 and the n-type collector region (n-well 204B).
The second purpose is n-type collector region (n-well 204B).
It is to prevent the breakdown voltage between the p-type external base region 115 and the p-type external base region 115. The p-type external base region 115 is the field oxide film 2.
If it is in contact with (or included in) the edge of 02, when the n-type collector region (n-well 204B) and the p-type external base region 115 are reverse biased,
A depletion layer extending from the junction between the n-type collector region (n-well 204B) and the p-type external base region 115 to the p-type external base region 115 side (the depletion layer extends to the n-type collector region (n-well 204B) side). Is larger than that of the above) reaches the edge of the field oxide film 202 with many crystal defects, and the base leak current increases, and as a result, the breakdown voltage is likely to deteriorate.

[0018]

However, when the p-type external base region 115 is separated from the edge of the field oxide film 202, the required width from the edge of the field oxide film 202 in the fourth element formation region is provided. Gate oxide film 2
Since 06 is left, a (p-type) parasitic MOS capacitance having the base electrode 209C as a gate electrode exists. The impurity surface concentration of the n-well 204A is set so that the V _{TP of the} pMOS transistor formed in the n-well 204A is −0.4 to −0.7V.
Since it is set equal to the impurity surface concentration of A,
When the base voltage V _B (applied to the base electrode 219C) is equal to the collector voltage V _C (applied to the n-well 204B), the energy band of this parasitic MOS capacitance becomes as shown in FIG. The high frequency CV characteristic of the parasitic MOS capacitance having such an energy band is as shown in FIG.

That is, the potential of the base electrode 219C is -0.4 with respect to the n well 204B (n type collector region).
When the voltage reaches to -0.7V, an inversion layer is formed on the surface of the n-well 204B. When the inversion layer is formed, the width of the depletion layer formed in the n-well 204B no longer extends (reaches the maximum depletion layer width W _m ) and the parasitic MOS capacitance becomes the lowest state (C _m ). On the other hand, when the potential of the base electrode 219C is higher than that of the n-well 204B (n-type collector region) to some extent, an accumulation layer is formed in the n-well 204B, and the parasitic MOS capacitance depends only on the thickness of the gate oxide film 206. It becomes the determined value C _o .

Here, the maximum depletion layer width W _m , the threshold voltage V _TP , the maximum depletion layer capacitance C _o, and the minimum depletion layer capacitance C _m are calculated with the impurity concentration of the n well 204B as N _A.

W _m is expressed by the following calculation formula.

[0022]

The value of C _o is per unit area

[0024]

[0025] The value of C _m is

[0026]

[0027] The threshold voltage V _TP is

[0028]

It becomes Here, N _A = 3 × 10 ¹⁷ c
If m ^-3 and d = 10 nm,

[0030]

## EQU1 ##

The width (Wc) and length of the emitter opening are 0.6 μm and 2.0 μm, and the width (Wc) of the base opening is
a) and 1.2 μm and 2.6 μm in length, and the width and length of the fourth element forming region are 1.6 μm and 3.0 μm.
When μm, C _o = 3.45 × 10 ⁻⁷ F / cm ² , so the maximum value of this parasitic MOS capacitance is about 5.8.
It becomes fF. Further, since the junction capacitance of the bipolar transistor of this size is about 4 fF, the total capacitance between the collector and the base becomes an extremely large value of about 9.8 fF.

Therefore, an object of the Bi-CMOS semiconductor device of the present invention is to suppress the Kirk effect and the deterioration of the breakdown voltage between the collector and the base, reduce the parasitic MOS effect, and easily reduce the parasitic capacitance. CMOS
It is to provide a semiconductor device. In addition, Bi of the present invention
An object of a method for manufacturing a CMOS semiconductor device is to provide a method for forming a Bi-CMOS semiconductor device having the above structure without increasing the number of photolithography steps as compared with the related art.

[0034]

Bi-CMOS of the present invention
The semiconductor device includes a p-well provided on the surface of a p-type silicon substrate, a first n-well, a second n-well having the same concentration distribution as the first n-well, and a first n-well provided on the surface of the p-well. Provided on the surface of the p-type silicon substrate surrounding the element formation region, the second element formation region provided on the surface of the first n-well, and the third and fourth element formation regions provided on the surface of the second n-well. A first gate electrode provided on the surface of the p well via the gate oxide film and the n-type source / drain region and provided in the first element formation region. nMOS
A transistor and a pMOS transistor provided in the second element forming region including a second gate electrode provided on the surface of the first n-well and a p-type source / drain region via a gate oxide film. N provided on the surface of the second n-well in the third element formation region
A type collector extraction region, a gate oxide film having a base opening provided on the surface of the second n-well in the fourth element formation region, and an emitter opening reaching the surface of the second n-well. , A base electrode which covers the base opening and is covered with an insulating film on the surface excluding the emitter opening extending over the gate oxide film and the field oxide film, and the second n electrode in a self-aligned manner with the emitter opening. A p-type base region provided on the well surface, a p-type external base region provided on the second n-well surface between the base opening and the emitter opening in a self-aligned manner with the base electrode, and at least a p-type base A high-concentration n-type selective ion implantation collector region (high-concentration n-type S) provided in the second n-well in contact with the bottom of the region.
IC region) and at least the low concentration n provided on the surface of the second n-well immediately below the gate oxide film in at least the fourth element formation region.
A type collector region, an insulating film spacer that covers the side surface of the emitter opening, an emitter electrode that covers the emitter opening and is in direct contact with the second n-well surface, and a p-type base region self-aligned with the emitter electrode. A bipolar transistor provided in a second n-well formed of an n-type emitter region provided on the surface.

Preferably, the low-concentration n-type collector region extends from the surface of the second n-well directly under the gate oxide film in the fourth element formation region to the second n-well directly under the p-type external base region. The high concentration n-type SIC region extending therein is provided only in the second n-well directly below the p-type base region. Alternatively, the low-concentration n-type collector region is provided only on the surface of the second n-well directly below the gate oxide film in the fourth element forming region, and the high-concentration n-type SIC region is the p-type external base region. It is provided directly below and in the second n-well directly below the p-type base region.

A first aspect of the method for manufacturing a Bi-CMOS device according to the present invention is that a field oxide film is formed in a region surrounding the first, second, third and fourth element forming regions on the surface of a p-type silicon substrate. Forming a p-well on the surface of the p-type silicon substrate including the first element formation region, and including the surface of the p-type silicon substrate including the second element formation region and the third and fourth element formation regions Forming a first n-well and a second n-well on the surface of the p-type silicon substrate, and forming an n-type collector lead-out region in the third element formation region in a self-aligned manner. A gate oxide film is formed on the surfaces of the first, second, third and fourth element formation regions, and a non-doped first polycrystalline silicon film and PS are formed on the entire surface.
A step of sequentially forming a G film and an opening narrower than the fourth element formation region on the fourth element formation region,
Forming a first photoresist film covering the gate oxide film on the surface of the fourth element formation region from the end of the field oxide film with a required width; and using the first photoresist film as a mask Then, the step of anisotropically etching the PSG film and the first polycrystalline silicon film sequentially, and the isotropic etching using the first photoresist film as a mask are performed on the surface of the fourth element formation region. Forming a base opening in the gate oxide film and undercutting at least the PSG film on the gate oxide film; removing the first photoresist film;
Forming a first p-type ion-implanted layer on at least the second n-well surface of the surface of the fourth element formation region by ion implantation using the SG film as a mask;
A step of removing the film and activating the first p-type ion implantation layer by heat treatment to form a low-concentration n-type collector region on at least the second n-well surface of the fourth element formation region surface. A step of forming a non-doped second polycrystalline silicon film on the entire surface, patterning of the second polycrystalline silicon film and the first polycrystalline silicon film, and the step of forming the non-doped second polycrystalline silicon film through the gate oxide film. A first polycrystalline silicon film pattern that traverses the first element formation region,
A second polycrystalline silicon film pattern that traverses the second element formation region via the gate oxide film and the fourth element formation region surface in the base opening are in direct contact with each other to form a fourth element. Forming a third polycrystalline silicon film pattern covering the gate oxide film left on the surface of the formation region and further extending onto the field oxide film around the fourth element formation region; A second photoresist film having an opening is formed on the p-well, and p-type ions are implanted into the first polycrystalline silicon film pattern by ion implantation using the second photoresist film as a mask. , A step of forming a first n-type ion implantation layer on the surface of the first element formation region, removing the second photoresist film, and activating the first n-type ion implantation layer by heat treatment. Above forming an n-type source / drain region on the surface of the p-well and converting the first polycrystalline silicon film pattern into a first gate electrode; and a third step of covering the p-well and the n-type collector lead-out region. Forming a photoresist film, and implanting p-type ions into the second and third polycrystalline silicon film patterns by ion implantation using the third photoresist film as a mask to form the second element forming region. A step of forming a second p-type ion implantation layer on the surface, a step of forming an insulating film on the entire surface by a low temperature vapor phase epitaxy method, and a fourth photo. A resist film is formed, and the insulating film and the third polycrystalline silicon film pattern are sequentially etched by anisotropic etching using the fourth photoresist film as a mask to form an emitter opening. Then, a second n-type ion implantation layer is formed on the surface of the low-concentration n-type collector region by ion implantation using the fourth photoresist film as a mask. Concentration n
A step of forming a third p-type ion implantation layer on the surface of the type collector region, a step of removing the fourth photoresist film, and a heat treatment to activate the second p-type ion implantation layer. A p-type source / drain region is formed on the surface of the first n-well, the third p-type ion-implanted layer is activated, and the low concentration n is self-aligned with the emitter opening.
A p-type base region is formed on the surface of the p-type collector region, the second n-type ion implantation layer is activated, and the high-concentration n-type S is formed just below the bottom surface of the p-type base region in a self-aligned manner with the emitter opening.
An IC region is formed, the second polycrystalline silicon film pattern is converted into a second gate electrode, the third polycrystalline silicon film pattern is converted into a base electrode, and a p-type self-aligned with the base electrode is formed. A step of forming a mold external base region on the surface of the low-concentration n-type collector region,
Is formed, and the second insulating film is etched back to form an insulating film spacer made of the second insulating film on the side surface of the emitter opening, and the n-type third polycrystalline silicon is formed on the entire surface. A step of forming a film, patterning the third polycrystalline silicon film to form an emitter electrode, and performing a heat treatment on the surface of the low concentration n-type collector region in a self-aligned manner with the insulating film spacer and the emitter electrode. forming an n-type emitter region.

Preferably, the second polycrystalline silicon film is formed by the low pressure vapor deposition method. More preferably, the p-type source / drain region, the p-type base region,
Heat treatment for forming a high-concentration n-type SIC region, a second gate electrode, a base electrode, and a p-type external base region,
The heat treatment for forming the n-type emitter region is the same heat treatment.

A second aspect of the method for manufacturing a Bi-CMOS semiconductor device of the present invention is that a field oxide film is formed in the region surrounding the first, second, third and fourth element forming regions on the surface of the p-type silicon substrate. Forming a p-well on the surface of the p-type silicon substrate including the first element formation region, and including the surface of the p-type silicon substrate including the second element formation region and the third and fourth element formation regions Forming a first n-well and a second n-well on the surface of the p-type silicon substrate, and forming an n-type collector lead-out region in the third element formation region in a self-aligned manner. A gate oxide film is formed on the surfaces of the first, second, third and fourth element formation regions, and a non-doped first polycrystalline silicon film and PS are formed on the entire surface.
A step of sequentially forming a G film and an opening narrower than the fourth element formation region on the fourth element formation region,
Forming a first photoresist film covering the gate oxide film on the surface of the fourth element formation region from the end of the field oxide film with a required width; and using the first photoresist film as a mask Then, the step of anisotropically etching the PSG film and the first polycrystalline silicon film sequentially, and ion implantation using the first photoresist film as a mask are performed to form the fourth portion immediately below the region where the base opening is to be formed. The step of forming a first n-type ion implantation layer on the surface of the element formation region, and isotropic etching using the first photoresist film as a mask, the gate oxidation on the surface of the fourth element formation region. Forming a base opening in the film, undercutting at least the PSG film on the gate oxide film, removing the first photoresist film, and removing the PSG film. By ion implantation using the disk, forming a first p-type ion implanted layer to the second n-well surface of the fourth element forming region surface, the PSG
The step of removing the film and the heat treatment activate the first p-type ion-implanted layer to form a low-concentration n-type collector region at least on the surface of the second n-well directly under the gate oxide film. 1 to activate the n-type ion-implanted layer to form a high-concentration n-type SIC region on the surface of the second n-well in a self-aligned manner with the base opening, and a non-doped second polycrystalline silicon film on the entire surface. A step of forming a film, patterning the second polycrystalline silicon film and the first polycrystalline silicon film, and forming a first polycrystalline film across the first element formation region through the gate oxide film. The crystalline silicon film pattern, the second polycrystalline silicon film pattern that crosses the second element formation region via the gate oxide film, and the base opening directly contact the surface of the fourth element formation region. A third polycrystalline silicon film pattern covering the gate oxide film left on the surface of the fourth element formation region and further extending onto the field oxide film around the fourth element formation region. A step of forming
A second photoresist film having an opening is formed on the p-well, and p-type ions are implanted into the first polycrystalline silicon film pattern by ion implantation using the second photoresist film as a mask. A step of forming a second n-type ion implantation layer on the surface of the first element formation region,
After removing the photoresist film of the
The n-type ion implantation layer of
Type source / drain regions and converting the first polycrystalline silicon film pattern into a first gate electrode, and a third photoresist film covering the p well and the n type collector extraction region. Is formed, p-type ions are implanted into the second and third polycrystalline silicon film patterns by ion implantation using the third photoresist film as a mask, and second p-type ions are formed on the surface of the second element formation region. By the step of forming the p-type ion implantation layer and the low temperature vapor phase growth method,
The step of forming an insulating film on the entire surface, the formation of a fourth photoresist film having an opening in a region where an emitter opening is to be formed, and the anisotropic insulation using the fourth photoresist film as a mask The film and the third polysilicon film pattern are sequentially etched to form an emitter opening, and a third photoresist is formed on the surface of the high-concentration n-type SIC region by ion implantation using the photoresist film as a mask.
Forming a p-type ion-implanted layer, removing the fourth photoresist film, and performing heat treatment to activate the second p-type ion-implanted layer to form a surface on the first n-well. forming p-type source / drain regions,
The p-type ion implantation layer is activated to form a p-type base region on the surface of the high-concentration n-type SIC region in a self-aligned manner with the emitter opening, and the second polycrystalline silicon film pattern is formed into a second pattern. Converting to a gate electrode, converting the third polycrystalline silicon film pattern into a base electrode, and forming a p-type external base region self-aligned with the base electrode on the surface of the high-concentration n-type SIC region; A second insulating film is formed on the entire surface, and the second insulating film is etched back to form an insulating film spacer made of the second insulating film on the side surface of the emitter opening. Forming a polycrystal silicon film, patterning the third polycrystal silicon film to form an emitter electrode, and performing a heat treatment on the insulating film spacer and the emitter electrode in a self-aligned manner with the high-concentration n-type S film. And a step of forming a n-type emitter region on the surface of the C region.

Preferably, the second polycrystalline silicon film is formed by the low pressure vapor deposition method. More preferably, the p-type source / drain region, the p-type base region,
Heat treatment for forming a high-concentration n-type SIC region, a second gate electrode, a base electrode, and a p-type external base region,
The heat treatment for forming the n-type emitter region is the same heat treatment.

[0040]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a schematic cross-sectional view of a Bi-CMOS semiconductor device, B of the first embodiment of the present invention is described.
The structure of the i-CMOS device is as follows.

On the surface of the p-type silicon substrate 101, the depth is about 0.7 to 1.0 μm and the impurity concentration is 8 × 10 ¹⁶ to.
4 × 10 ¹⁷ cm ^-3 of about p-well 103, n-well 10 dopant concentration of about ^{8 × 10 16 ~4 × 10 17} cm -3 , respectively the depth of the junction respectively about 0.7~1.0μm
4A and 104B are provided. A first element forming region is provided on the surface of the p well 103, a second element forming region is provided on the surface of the n well 104A, and third and fourth element forming regions are provided on the surface of the n well 104B. The formation region is surrounded by the field oxide film 102 having a film thickness of about 300 to 400 nm.

An nMOS transistor is provided in the first element formation region of the p well 103. These n
In the MOS transistor, the first element is formed in a self-aligned manner with the gate electrode 109A provided on the surface of the p well 103 via the gate oxide film 106 having a thickness of about 5 to 10 nm, the field oxide film 102 and the gate electrode 109A. The n-type source / drain region 112 (high concentration) provided on the surface of the region. The gate electrode 109A is made of a high-concentration n-type polycrystalline silicon film and has a gate length of 0.4 μm.
The gate width is about 5 to 10 μm. The side surface and the upper surface of the gate electrode 109A are covered with the insulating film spacer 108 and the insulating film 117, respectively. n
The junction depth of the source / drain regions 112 is 0.15
It is about μm. The surface impurity concentration of the p-well 103 is
Threshold voltage (V _TN ) of these nMOS transistors
Is adjusted to about 0.5 to 0.8V.

A pMOS transistor is provided in the second element formation region of the n-well 104A. These p
The MOS transistor is a gate electrode 109B provided on the surface of the n-well 104A via the gate oxide film 106.
And field oxide film 102 and gate electrode 109B
And a (high concentration) p-type source / drain region 113 provided on the surface of the second element formation region in a self-aligned manner. The gate electrode 109B is made of a high-concentration p-type polycrystalline silicon film and has a gate length of about 0.5 μm and a gate width of about 5 to 10 μm. The side surface and the upper surface of the gate electrode 109B are also covered with the insulating film spacer 108 and the insulating film 117, respectively. The junction depth of the p-type source / drain region 113 is about 0.2 μm.
The surface impurity concentration of the n-well 104A (and the n-well 104B) is adjusted so that the threshold voltage (V _TP ) of these pMOS transistors is about -0.5 to -0.8V.

The n-well 104B includes the n-well 104B.
A vertical npn-type bipolar transistor is provided with itself as an n-type collector region. n-well 104
In the B third element formation region, a high-concentration n-type collector lead-out region 105 is provided. n-well 104B
In the fourth element formation region, a base region and an emitter region are provided, and the width and length of the opening of the fourth element formation region are, for example, about 1.6 μm and 3.0 μm.
It is a degree. A base opening from which the gate oxide film 106 is removed is provided on the surface of the n-well 104B in the fourth element formation region. The opening width of this base opening (W
a) is, for example, about 1.2 μm, and the length is, for example, 2.6 μm
At this time, the gate oxide film 106 is left with a width of, for example, about 0.2 μm from the edge of the fourth element formation region. On the surface of the n-well 104B in the fourth element formation region, a part of the base opening and the gate oxide film left there are covered with a base electrode 109C made of a high-concentration p-type polycrystalline silicon film. There is. The base electrode 109C extends up to the field oxide film 102 around the fourth element formation region, and an insulating film spacer 108 is provided on the side surface of the base electrode 109C on the field oxide film 102. Base electrode 10
The upper surface of 9C is covered with an insulating film 117.

The base electrode 109C is provided with an emitter opening, and the opening width (Wc) of this emitter opening is provided.
Is, for example, about 0.6 μm, and the length is, for example, 2.0 μm. Therefore, the base electrode 109C is approximately (Wa-W
c) / 2 with a width of, for example, about 0.3 μm, n-well 10
4B directly, and a high-concentration p-type external base region 111 is provided (in self-alignment with the base electrode 109C) on the surface of the n-well 104B in the direct contact portion. The junction depth of the p-type external base region 111 is, for example, about 0.2 μm. This p-type external base region 1
11 is not in direct contact with the field oxide film 102. On the surface of the n-well 104B in the fourth element formation region, a p-type base region 11 self-aligned with the emitter opening is formed.
5 are provided. The junction depth of the p-type base region 115 is, for example, about 0.15 μm, and the p-type base region 115 is directly connected to the p-type external base region 111. Further, the n-well 104B in the fourth element formation region
High concentration n-type SI self-aligned with the emitter opening
A C region 114a is provided. This high concentration n-type SI
The C region 214 is in direct contact with at least the bottom surface of the p-type base region 114a, and has a high concentration n-type SIC region 114.
The depth of a is, for example, about 0.6 to 0.7 μm.

In addition, the n-well 10 in the fourth element formation region
A low concentration n-type collector region 107a, which is a feature of this embodiment, is provided on the surface of 4B. The low-concentration n-type collector region 107a is in direct contact with the gate oxide film 106 left in the fourth element formation region and the side and bottom surfaces of the p-type external base region 115, and the high-concentration n-type SIC region 114a is formed. It has a form in which it is directly connected to at least the side surface. The impurity concentration of the low-concentration n-type collector region 107a is the n-well 104B (and the n-well 104A).
Lower than the impurity concentration of, for example, 5 × 10 ¹⁵ to 2 × 10 ¹⁶
It is about cm ^-3 . The low concentration n-type collector region 107a has a depth of, for example, about 0.5 to 0.8 μm.

Base electrode 10 forming the emitter opening
The side surface of 9C is covered with an insulating film spacer 118 having a width of, for example, about 100 nm. This insulating film spacer 1
18 and the base electrode 109C through the insulating film 117.
The surface of the n-well 104B in the fourth element formation region (p-type base region 115) in the emitter opening.
An emitter electrode 121 is provided that is in direct contact with the surface of the emitter. The emitter electrode 121 is made of a high-concentration n-type polycrystalline silicon film. On the surface of the p-type base region 115, a high-concentration n-type emitter region 122 self-aligned with the emitter electrode 121 is provided. The junction depth of the n-type emitter region 122 is, for example, about 500 to 600 nm, and the n-type emitter region 122 is not in direct contact with the p-type external base region 111.

In the Bi-CMOS semiconductor device of the first embodiment, the high concentration n is formed on the bottom surface of the p-type base region 115.
Since the p-type extrinsic base region 111 and the field oxide film 102 are not in direct contact with each other, the SIC region 114a is in direct contact with the SIC region 114a. It is possible to suppress the breakdown voltage between the bases.

In the Bi-CMOS semiconductor device having the conventional structure, the occupation area of the p-type external base region is reduced for the purpose of reducing the junction capacitance between the collector and the base. As a result, the reduction of the junction capacitance itself was realized, but the value of the parasitic MOS capacitance newly generated by this was large enough to offset the reduction in the junction capacitance. On the other hand, in the Bi-CMOS semiconductor device of the present embodiment, the low concentration n-type collector region 107a is provided immediately below the gate oxide film 106 left in the fourth element formation region. As a result, by adopting this embodiment, it becomes easy to set the value of the parasitic MOS capacitance to 1/10 of the value of the junction capacitance. The reduction of the value of the parasitic MOS capacitance will be described below.

Regarding the impurity surface concentration of the n-well 104A, the V _{TP of the} pMOS transistor formed here is -0.4.
Set to ~ -0.7V, and n-well 1
The impurity surface concentration of 04B is also set equal to the impurity surface concentration of the n-well 104A, but in the present embodiment,
A low concentration n-type collector region 107a having an impurity concentration lower than that of the n well 104B itself is provided.
For example, the film thickness d of the gate oxide film 106 is 10 nm, and the impurity concentration of the low concentration n-type collector region 107a is 1 × 10 ^16.
If cm ^- 3,

[0052]

It becomes At this time, (the base electrode 119C
When the base voltage V _B (applied to V) is equal to the collector voltage V _C (applied to the lightly doped n-type collector region 107a), the energy band of this parasitic MOS capacitance is
become that way. The high frequency CV characteristic of the parasitic MOS capacitor having such an energy band is as shown in FIG. 5, and this parasitic MOS is of depletion type. If the dimensions of the fourth element forming region, the base opening and the emitter opening of the Bi-CMOS semiconductor device of this embodiment are the same as those of the conventional Bi-CMOS semiconductor device, the parasitic of this embodiment will be described. MOS capacitance is about 0.53
It becomes fF. Therefore, in this case, the total capacitance between the collector and the base in this embodiment is about 4.53 fF, which is much lower than the total capacitance between the collector and the base of the Bi-CMOS semiconductor device having the conventional structure.

Referring to FIG. 2 and FIG. 3 which are schematic sectional views of the manufacturing process of the Bi-CMOS semiconductor device and FIG. 1 together, the Bi-CMOS semiconductor device of the first embodiment is as follows. It is formed.

First, in the element isolation region on the surface of the p-type silicon substrate 101, a film thickness of 300 to 4 is formed by, for example, a selective oxidation method.
A field oxide film 102 of about 00 nm is formed. P-well 103, n-wells 104A, 104 are formed in required regions by ion implantation with high acceleration energy.
Form B. The first element formation region is formed on the surface of the p well 103, the second element formation region is formed on the surface of the n well 104A, and the third and fourth element formation regions are formed on the surface of the n well 104B. It is formed by being surrounded by. N-well 104A including surface impurity concentration
And the n-well 104B have the same impurity concentration distribution,
The impurity concentration distributions of the n-wells 104A and 104B are set so as to match the V _TP of the pMOS transistor formed in the n-well 104A. This is because the manufacturing process is simplified and the performance of the pMOS transistor is given the highest priority (because the performance of the pMOS transistor is inferior to that of the bipolar transistor and the nMOS transistor).

Subsequently, a high-concentration n-type collector extraction region 105 is formed on the surface of the n-well 104B in the third element formation region by, for example, selective ion implantation of high-concentration phosphorus into the third element formation region. To form. By the thermal oxidation method,
Gate oxide films 106 are formed on the surfaces of the second, third and fourth element formation regions, respectively. First, second and fourth
Oxide film 106 formed on the surface of the element formation region of
Is about 5 to 10 nm, but the gate oxide film formed on the surface of the third element formation region is thick (because it is formed on the surface of the high-concentration n-type collector extraction region 105). Has become. 20-50 nm on the entire surface
Non-doped first polycrystalline silicon film 12 having a thickness of about 10 nm
9 is formed, and a PSG film having a film thickness of, for example, about 300 to 500 nm is further formed on the entire surface. On this PSG film, a (first) photoresist film 136 having an opening in a region where a base opening is to be formed in the fourth element formation region is formed.
Using this photoresist film 136 as a mask, PSG
The film and the polycrystalline silicon film 129 are sequentially anisotropically etched. The opening width at this time is Wa. Again using this photoresist film 136 as a mask, the gate oxide film 1
Isotropic etching with buffered hydrofluoric acid is performed on 06 to complete the base opening. At this time, the width of the gate oxide film 106 left in the fourth element formation region is
For example, it is about 0.2 μm. Further, during this isotropic etching (wet etching), the PSG film is undercut and the PSG film 131A is left. If the thickness of the gate oxide film 106 is about 10 nm, the opening width Wb of this PSG film is 0.3 to more than Wa.
The width becomes 0.4 μm or more, which is wider than the width of the fourth element formation region [FIG. 2 (a)]. The polycrystalline silicon film 12
9 is formed to prevent the PSG film from directly contacting the gate oxide film 106.

After removing the photoresist film 136,
30 to 50 keV, 5 using the PSG film 131A as a mask
Ion implantation of boron is performed under the condition of × 10 ^{11 to} 5 × 10 ¹² cm ^-2 , and further 60 to 100 keV, 5 × 10 ¹¹ ~.
Boron ion implantation is performed again under the condition of 5 × 10 ¹² cm ⁻² . As a result, the n well 10 in the fourth element formation region is formed.
A boron ion implantation layer 137a is formed in 4B [FIG. 2 (b)].

Next, the PSG film 131A is selectively removed by etching with diluted hydrofluoric acid. The boron / ion-implanted layer 137a is activated by heat treatment, and the low-concentration n-type collector region 107 is formed on the surface of the n-well 104B in the fourth element formation region.
a is formed. A non-doped second polycrystalline silicon film having a film thickness of about 100 to 300 nm is deposited on the entire surface, and as a result, this polycrystalline silicon film and the polycrystalline silicon film 129 are deposited.
A non-doped polycrystalline silicon film 139 in which is laminated is formed [FIG. 2 (c)]. The second polycrystalline silicon film is preferably formed by low pressure vapor deposition (LPCVD). This is isotropic etching with buffered hydrofluoric acid for forming the base opening and the PS
This is because it is impossible to completely prevent the undercut of the gate oxide film 106 in the vicinity of the base opening during the etching with diluted hydrofluoric acid for removing the G film 131A. The heat treatment for activating the boron / ion implantation layer 137a may be performed after the second polycrystalline silicon film is formed.

Subsequently, this polycrystalline silicon film 139 is patterned to form a polycrystalline silicon film pattern 139A,
139B and 139C are formed. The polycrystalline silicon film pattern 139A has a width of about 0.4 μm and is formed on the p well 103 so as to cross the first element formation region. The polycrystalline silicon film pattern 139B has a thickness of 0.5 μm.
It has a width of about m and is formed on the n well 104A so as to cross the second element formation region. The polycrystalline silicon film pattern 139C is formed on the n well 104B so as to cover the fourth element formation region (low concentration n-type collector region 107a) including the base opening [FIG. 2 (d)].

Next, a polycrystalline silicon film pattern 139A, 1 is formed by forming an insulating film (silicon oxide film or silicon nitride film) on the entire surface and etching back the insulating film.
Insulating film spacers 10 are provided on the side surfaces of 39B and 139C, respectively.
8 is formed. A photoresist film 152 having an opening is formed in the p well 103. Using this photoresist film 152 as a mask, high-concentration arsenic ion implantation is performed to form an arsenic ion-implanted layer 142 on the surface of the p-well 103. At this time, high-concentration arsenic is also implanted into the non-doped polycrystalline silicon film pattern 139A, which becomes the polycrystalline silicon film pattern 159A [FIG.
(A)].

After removing the photoresist film 152,
The arsenic ion implantation layer 142 is activated by heat treatment to form the n-type source / drain regions 112. By this heat treatment, the polycrystalline silicon film pattern 159A is formed on the gate electrode 109 (made of a high concentration n-type polycrystalline silicon film).
Become A. The heat treatment is performed at this stage because the diffusion coefficient of arsenic is small and it is not preferable to form the n-type source / drain regions 112 by the heat treatment for forming the n-type emitter region and the like. p-well 103 and third
A photoresist film 153 covering the element formation region (n-type collector lead-out region 105) is formed. Using this photoresist film 153 as a mask, high concentration BF ₂ ions are implanted to form a boron ion implantation layer 143 on the surface of the n-well 104A. At this time, high-concentration BF ₂ is also injected into the polycrystalline silicon film patterns 139B and 139C, respectively, to become polycrystalline silicon film patterns 159B and 159C, respectively (FIG. 3B).

After removing the photoresist film 153,
A (first) insulating film 117 (a silicon oxide film or a silicon nitride film) having a film thickness of about 100 to 200 nm is formed on the entire surface by a low temperature (preferably 700 ° C. or lower) vapor phase growth method. This insulating film 117 is intended to insulate and separate a base electrode and an emitter electrode which will be formed in a later step. Further, the reason why the method of growing the insulating film 117 is low temperature is that the polycrystalline silicon film pattern 159C to the n-well 104B (low-concentration n-type collector region 107) is formed at this stage.
This is to suppress the thermal diffusion of boron in a). When the insulating film 117 is a silicon nitride film, it is formed at 600 to 700 ° C. by LPCVD using ammonia (NH ₃ ) and dichlorosilane (SiCl ₂ H ₂ ). Further, as a film forming method when the insulating film 117 is a silicon oxide film, TEOS (Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) are used at atmospheric pressure vapor phase growth method at about 450 ° C. ( APCVD) or LPCVD at 650 to 700 ° C. using TEOS and oxygen (O ₂ ).

Next, a photoresist film 154 having an opening in the emitter opening forming region is formed. The photoresist film 154 is used as a mask to form the insulating film 11.
7. Polycrystalline silicon film pattern 159C is sequentially anisotropically etched to form an emitter opening having an opening width Wc. Then, the photoresist film 154
As a mask, 200 to 400 keV, 1 × 10 ¹² to
Phosphorus ion implantation of 5 × 10 ¹² cm ^-2 is performed to form a phosphorus ion implantation layer 144a in the n well 104B (low concentration n-type collector region 107a) immediately below the emitter opening.
Further, using the photoresist film 154 as a mask, 5
Boron ion implantation of ˜20 keV, 1 × 10 ^{13 to} 5 × 10 ¹³ cm ⁻² is performed to form a boron / ion implantation layer 145 on the surface of the n-well 104B (low concentration n-type collector region 107a) immediately below the emitter opening. (FIG. 3 (c)).

After removing the photoresist film 154,
A (second) insulating film (a silicon oxide film or a silicon nitride film) having a film thickness of about 100 nm is formed on the entire surface by, for example, a low temperature vapor phase growth method, and the insulating film is etched back to form a polycrystal in the emitter opening. An insulating film spacer 118 is formed on the side surface of the silicon film pattern 159C (and the insulating film 117). Subsequently, a non-doped third polycrystalline silicon film is formed on the entire surface, high-concentration arsenic is introduced into the third polycrystalline silicon film, and the third polycrystalline silicon film is patterned. Thereafter, heat treatment is performed to activate boron and arsenic in the respective polycrystalline silicon film patterns and boron and phosphorus in various ion-implanted layers. As a result, the polycrystalline silicon film pattern 159B becomes a gate electrode 109B (made of a high-concentration p-type polycrystalline silicon film).
And the remaining polycrystalline silicon film pattern 159C
Becomes a base electrode 109C (made of a high-concentration p-type polycrystalline silicon film), and the pattern made of the third polycrystalline silicon film becomes an emitter electrode 121 (made of a high-concentration n-type polycrystalline silicon film). Become. Further, the boron / ion implantation layer 143 becomes the (high-concentration) p-type source / drain region 113, the phosphorus ion implantation layer 144a becomes the high-concentration n-type SIC region 114a, and the boron / ion implantation layer 14 is formed.
5 becomes the p-type base region 115. Further, boron is diffused from the base electrode 109C, and a high-concentration p-type external base region 111 is formed on the surface of the n-well 104B (low-concentration n-type collector region 107a). Furthermore, arsenic is diffused from the emitter electrode 121, and the insulating film spacer 11
A high-concentration n-type emitter region 122 is formed on the surface of the p-type base region 115 in a self-aligned manner (FIG. 1).

The method of forming the (second) insulating film forming the insulating film spacer 118 is not limited to the low temperature vapor phase growth method, but may be the high temperature vapor phase growth method.
For example, when this insulating film is an HTO film, it is an LPCV using monosilane and nitrous oxide (N ₂ O).
Formed by D. In this case, the gate electrode 109B and the base electrode 109 are formed together with the formation of the third insulating film.
C, p-type external base region 111, p-type source / drain region 113, high-concentration n-type SIC region 114a and p-type base region 115 are formed. In this way,
It becomes easy to control the junction depth of the n-type emitter region 122. Further, the method of forming the emitter electrode 121 is not limited to the above method. There are also methods such as doping an undoped amorphous silicon film with arsenic or phosphorus and patterning it, or patterning an arsenic or phosphorus-doped amorphous silicon film or a polycrystalline silicon film. It suffices if it becomes an n-type polycrystalline silicon film at the step.

Bi-CMO according to the first embodiment
In the method for manufacturing the S semiconductor device, the number of photolithography steps is the same as the conventional number, as described above. According to the present embodiment, by devising the photolithography process for forming the base opening, the target Bi-CMOS semiconductor device can be manufactured. That is, this photolithography process is as follows. A gate oxide film 106 is formed, a non-doped polycrystalline silicon film 129 is formed, and a PSG film is further formed. Then, a photoresist film 136 is formed.
Is used as a mask to anisotropically etch the PSG film and the polycrystalline silicon film 129, and the gate oxide film 106 is etched with buffered hydrofluoric acid to form a base opening having an opening width Wa. -Cut to leave the PSG film 131A. After this photolithography process (removing the photo resist film 136), the boron ion implantation layer 137a and the low concentration n-type collector region 107a are formed without adding a new photolithography process.

Referring to FIG. 6 which is a schematic sectional view of the Bi-CMOS semiconductor device, the second embodiment B of the present invention will be described.
The i-CMOS semiconductor device is the same as the B-type semiconductor device of the first embodiment.
Compared with the i-CMOS device, the structure of the high concentration n-type SIC region 114b for suppressing the Kirk effect is characteristic. That is, the high concentration n-type SIC region 114b is
Not only the bottom surface of the p-type base region 115 but also the bottom surface of the p-type external base region 111 is directly contacted.

Although the junction capacitance between the collector and the base is slightly increased in the present embodiment as compared with the first embodiment, this embodiment has the following effects as compared with the first embodiment. . In the high current region, n-type emitter region 1
An emitter crowding effect is known in which the current density at the end 22 is increased. Therefore, as in the present embodiment, the high-concentration n-type SIC region 114b is made wider than the region directly under the n-type emitter region 122 to suppress the decrease in f _T in the high current region. It will be easier. Since the bipolar transistor in the Bi-CMOS semiconductor device operates in the high current region, such a structure is more advantageous.

Further, in the present embodiment, similarly to the first embodiment, the low concentration n-type collector region 107b is provided in the n well 104B immediately below the base electrode 109C via the gate oxide film 106. There is. Therefore, in the present embodiment as well, similarly to the first embodiment, it is easy to suppress the breakdown voltage between the collector and the base and reduce the parasitic MOS capacitance.

Referring to FIGS. 7 and 8 and FIG. 6, which are schematic cross-sectional views of the manufacturing process of the Bi-CMOS semiconductor device, the Bi-CMOS semiconductor device of the second embodiment is as follows. It is formed.

First, the field oxide film 102 is formed in the element isolation region on the surface of the p-type silicon substrate 101, and the p well 103 and the n well 104A, 1 are formed in the required regions, respectively.
04B is formed. The first element formation region is formed on the surface of the p well 103, the second element formation region is formed on the surface of the n well 104A, and the third and fourth element formation regions are formed on the surface of the n well 104B. It is formed by being surrounded by. Further, a high-concentration n-type collector extraction region 105 is formed on the surface of the n-well 104B in the third element formation region, and a gate oxide film is formed on the surfaces of the first, second, third, and fourth element formation regions, respectively. Forming 106,
Non-doped first polycrystalline silicon film 129, P on the entire surface
The SG film 131 is formed. On this PSG film 131, a (first) photoresist film 136 having an opening in a region where a base opening is to be formed in the fourth element formation region is formed.
Using this photoresist film 136 as a mask, PSG
The film and the polycrystalline silicon film 129 are sequentially anisotropically etched. The opening width at this time is Wa. The steps up to this step are the same as those in the first embodiment. Then, using the photoresist film 136 as a mask, 200 to 400
KeV, 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² of phosphorus is ion-implanted to form a phosphorus ion-implanted layer 144b in the n-well 104B immediately below the region where the base opening is to be formed [FIG. 7].
(A)].

Again using this photoresist film 136 as a mask, the gate oxide film 106 is isotropically etched with buffered hydrofluoric acid to complete the base opening. At this time, the width of the gate oxide film 106 left in the fourth element formation region is, for example, about 0.2 μm. Further, during this isotropic etching (wet etching), the PSG film 131 is under-cut, and the opening width of the PSG film becomes Wb.
1A remains (FIG. 7B).

After removing the photoresist film 136,
30 to 50 keV, 5 using the PSG film 131A as a mask
Ion implantation of boron is performed under the condition of × 10 ^{11 to} 5 × 10 ¹² cm ^-2 , and further 60 to 100 keV, 5 × 10 ¹¹ ~.
Boron ion implantation is performed again under the condition of 5 × 10 ¹² cm ⁻² . As a result, the n well 10 in the fourth element formation region is formed.
A boron ion implantation layer 137b is formed in 4B [FIG. 7 (c)].

Next, the PSG film 131A is selectively removed by etching with diluted hydrofluoric acid. The heat treatment activates the phosphorus ion implantation layer 144b and the boron ion implantation layer 137a, so that the high concentration n-type SIC region 114b and the low concentration n
The mold collector region 107b is formed. A non-doped second polycrystalline silicon film is deposited on the entire surface, and as a result, a non-doped polycrystalline silicon film 139 in which this polycrystalline silicon film and the polycrystalline silicon film 129 are laminated is formed [FIG. 7 (d)]. ]. Also in this embodiment, it is preferable that the second polycrystalline silicon film is formed by LPCVD.

Then, as in the first embodiment,
This polycrystalline silicon film 139 is patterned to form polycrystalline silicon film patterns 139A, 139B, 139C. The polycrystalline silicon film pattern 139A has a thickness of 0.
It has a width of about 4 μm and is formed on the p well 103 so as to cross the first element formation region. The polycrystalline silicon film pattern 139B has a width of about 0.5 μm and is formed on the n well 104A so as to cross the second element formation region. The polycrystalline silicon film pattern 139C is
The fourth element formation region including the base opening (high concentration n-type SIC region 114b and low concentration n-type collector region 10)
7b) is formed on the n-well 104B [FIG. 8 (a)].

Next, by forming an insulating film (silicon oxide film or silicon nitride film) and etching back the insulating film, polycrystalline silicon film patterns 139A and 139 are formed.
Insulating film spacers 108 are formed on the side surfaces of B and 139C, respectively. A photoresist film 152 having an opening is formed in the p well 103. This photoresist film 1
High concentration arsenic ion implantation is performed using 52 as a mask to form an arsenic ion implantation layer 142 on the surface of the p well 103. At this time, high-concentration arsenic is also implanted into the non-doped polycrystalline silicon film pattern 139A, which becomes the polycrystalline silicon film pattern 159A [FIG. 8 (b)].

After removing the photoresist film 152,
The arsenic ion implantation layer 142 is activated by heat treatment to form the n-type source / drain regions 112. By this heat treatment, the polycrystalline silicon film pattern 159A is formed on the gate electrode 109 (made of a high concentration n-type polycrystalline silicon film).
Become A. A photoresist film 153 is formed to cover the p well 103 and the third element formation region (n-type collector extraction region 105). This photoresist film 1
Ion implantation of high-concentration BF ₂ is performed using 53 as a mask, and the boron ion implantation layer 14 is formed on the surface of the n-well 104A.
3 is formed. At this time, the polycrystalline silicon film pattern 1
High-concentration BF ₂ is also injected into 39B and 139C, respectively, and polycrystalline silicon film patterns 159B and
It becomes 9C [FIG.8 (c)].

After removing the photoresist film 153,
A (first) insulating film 117 (a silicon oxide film or a silicon nitride film) is formed on the entire surface by a low temperature (preferably 700 ° C. or lower) vapor phase epitaxy by the same method as in the first embodiment. A photoresist film 154 having an opening is formed in the area where the emitter opening is to be formed. The photoresist film 154 is used as a mask to form the insulating film 11.
7. Polycrystalline silicon film pattern 159C is sequentially anisotropically etched to form an emitter opening having an opening width Wc. Then, the photoresist film 154
As a mask, 5 to 20 keV, 1 × 10 ^{13 to} 5 × 1
Boron ion implantation of 0 ¹³ cm ^-2 was performed, and the n well 104B (high concentration n-type SIC region 1) immediately below the emitter opening was formed.
14b) A boron ion-implanted layer 145 is formed on the surface [FIG. 8 (d)].

After removing the photoresist film 154,
A (second) insulating film (a silicon oxide film or a silicon nitride film) having a film thickness of about 100 nm is formed on the entire surface by, for example, a low temperature vapor phase growth method, and the insulating film is etched back to form a polycrystal in the emitter opening. An insulating film spacer 118 is formed on the side surface of the silicon film pattern 159C (and the insulating film 117). Subsequently, a non-doped third polycrystalline silicon film is formed on the entire surface, high-concentration arsenic is introduced into the third polycrystalline silicon film, and the third polycrystalline silicon film is patterned. Thereafter, heat treatment is performed to activate boron and arsenic in the respective polycrystalline silicon film patterns and boron and phosphorus in various ion-implanted layers. As a result, the polycrystalline silicon film pattern 159B becomes a gate electrode 109B (made of a high-concentration p-type polycrystalline silicon film).
And the remaining polycrystalline silicon film pattern 159C
Becomes a base electrode 109C (made of a high-concentration p-type polycrystalline silicon film), and the pattern made of the third polycrystalline silicon film becomes an emitter electrode 121 (made of a high-concentration n-type polycrystalline silicon film). Become. Further, the boron / ion implantation layer 143 becomes the (high-concentration) p-type source / drain region 113, and the boron / ion implantation layer 145 becomes the p-type base region 115. Further, boron is diffused from the base electrode 109C, and the n-well 104B (high-concentration n-type S
A high concentration p-type external base region 111 is formed on the surface of the IC region 114b). Furthermore, the emitter electrode 121
As a result, arsenic is diffused, and a high concentration n-type emitter region 122 is formed on the surface of the p-type base region 115 in a self-aligned manner with the insulating film spacer 118 [FIG. 6].

Bi-CMO according to the second embodiment
Similarly to the manufacturing method according to the first embodiment, the S semiconductor device manufacturing method can also manufacture the target Bi-CMOS semiconductor device without increasing the number of photolithography steps. Further, in the present embodiment, the high-concentration n-type SIC region 114b having a deep depth is formed in the initial stage in relation to the photolithography process for forming the base opening. Therefore, in the manufacturing method according to the present embodiment, as compared with the manufacturing method according to the first embodiment, the diffusion layer (n-type source / drain region 112, p-type source / drain region 113, p-type base region 115, p-type external base region 1
11 and the n-type emitter region 122, etc.) is easy to control.

[0081]

As described above, the Bi-CM of the present invention is used.
In an OS semiconductor device, a base electrode and an emitter electrode are configured in a self-aligned manner, and a gate oxide film exists on the outer periphery of a p-type external base region provided on the surface of an n-well connected to the base electrode. In the transistor, a low-concentration n-type collector region having an impurity concentration lower than that of the n-well is provided on the surface of the n-well directly below the base electrode via the gate oxide film. Therefore, in the Bi-CMOS semiconductor device of the present invention, it becomes easy to suppress the Kirk effect, suppress the breakdown voltage between the collector and the base, and suppress the parasitic capacitance between the collector and the base.

Further, according to the method of manufacturing the Bi-CMOS semiconductor device of the present invention, the low concentration n-type collector is formed in the photolithography process for forming the base opening without providing a special photolithography process. It becomes possible to form a region.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the first embodiment.

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the first embodiment.

FIG. 4 is a diagram for explaining the effect of the first embodiment and an energy band diagram for explaining a parasitic MOS effect.

FIG. 5 is a diagram for explaining the effect of the first embodiment, and is a graph of the CV characteristic of the parasitic MOS.

FIG. 6 is a schematic cross-sectional view of a second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of the manufacturing process of the second embodiment.

FIG. 8 is a schematic cross-sectional view of the manufacturing process of the second embodiment.

FIG. 9 is a schematic sectional view of a conventional Bi-CMOS device.

FIG. 10 is a schematic sectional view of a manufacturing process of the conventional Bi-CMOS device.

FIG. 11 is a schematic sectional view of a manufacturing process of the conventional Bi-CMOS device.

FIG. 12 is a diagram for explaining a problem of the conventional Bi-CMOS device, and an energy band diagram for explaining a parasitic MOS effect.

FIG. 13 is a diagram for explaining the problem of the conventional Bi-CMOS device, and is a graph of the CV characteristic of the parasitic MOS.

[Explanation of symbols]

101, 201 p-type silicon substrate 102, 202 field oxide film 103, 203 p-well 104A, 104B, 204A, 204B n-well 105, 205 n-type collector extraction region 106, 206 gate oxide film 107a, 107b low concentration n-type collector region 108, 118, 208, 228 Insulating film spacer 109A, 109B, 209A, 209B Gate electrode 109C, 209C Base electrode 111, 211 p-type external base region 112, 212 n-type source / drain region 113, 213 p-type source / drain region 114a, 114b, 214 High-concentration n-type SIC region 115, 215 p-type base region 117, 217 insulating film 121, 221 emitter electrode 122, 222 n-type emitter region 129, 139, 229, 239 Crystalline silicon film 131, 131A PSG film 136, 152, 153, 154, 236, 252, 2
53,254 Photoresist film 137a, 137b, 143, 145, 243, 245
Boron ion implantation layer 139A, 139B, 139C, 159A, 159B,
159C, 239A, 239B, 239C, 259A,
259B, 259C Polycrystalline silicon film pattern 142,242 Arsenic ion implantation layer 144a, 144b, 244 Phosphorus ion implantation layer Wa, Wb, Wc Opening width

Claims (9)

[Claims] 1. A p-well provided on the surface of a p-type silicon substrate, a first n-well, a second n-well having the same concentration distribution as the first n-well, and a surface provided on the p-well. The first element formation region, the second element formation region provided on the surface of the first n-well, and the third and fourth element formation regions provided on the surface of the second n-well are surrounded by the p Element having a field oxide film provided on the surface of a p-type silicon substrate, and comprising a first gate electrode and an n-type source / drain region provided on the surface of the p-well via a gate oxide film. An nMOS transistor provided in the formation region, a second gate electrode provided on the surface of the first n-well via a gate oxide film, and a second element formation region including a p-type source / drain region. Provided a pMOS transistor, an n-type collector lead-out region provided on the surface of the second n-well of the third device forming region, and a fourth opening of the fourth device forming region having a base opening. A gate oxide film provided on the surface of the second n-well and an emitter opening reaching the surface of the second n-well, covering the base opening;
A base electrode having a surface excluding the emitter opening, which extends over the gate oxide film and the field oxide film, is covered with an insulating film, and a surface of the second n-well self-aligned with the emitter opening. A p-type base region provided, a p-type external base region provided on the surface of the second n-well between the base opening and the emitter opening in a self-aligned manner with the base electrode, and at least the p-type base region. A high-concentration n-type selective ion implantation collector region (high-concentration n-type SIC region) provided in the second n-well in contact with the bottom surface of the type base region;
At least the low-concentration n-type collector region provided on the surface of the second n-well directly below the gate oxide film in the fourth element formation region, an insulating film spacer covering the side surface of the emitter opening, and the emitter opening The second n-type emitter region which covers the portion and is in direct contact with the surface of the second n-well, and an n-type emitter region provided on the surface of the p-type base region in self-alignment with the emitter electrode. A Bi-CMOS semiconductor device having a bipolar transistor provided in an n-well. 2. The low-concentration n-type collector region is the fourth
Of the second n-well directly below the p-type external base region from the surface of the second n-well directly below the gate oxide film in the element forming region, and the high-concentration n-type SIC region is the p-type. The Bi-C according to claim 1, wherein the Bi-C is provided only in the second n-well just below the base region.
MOS semiconductor device. 3. The low-concentration n-type collector region is the fourth
Of the high-concentration n-type SI provided only on the surface of the second n-well directly below the gate oxide film in the element formation region of
2. The Bi-CMOS device according to claim 1, wherein a C region is provided directly below the p-type external base region and in the second n-well directly below the p-type base region. 4. A field oxide film is formed in a region surrounding the first, second, third and fourth element formation regions on the surface of a p-type silicon substrate, and the p type including the first element formation region is formed. A p-well is formed on the surface of the silicon substrate, and a p-well is formed on the surface of the p-type silicon substrate including the second element formation region and on the surface of the p-type silicon substrate including the third and fourth element formation regions. Forming a first n-well and a second n-well, forming an n-type collector lead-out region in the third element formation region in a self-aligned manner, the first, second, third and Forming a gate oxide film on the surface of the fourth element formation region and sequentially forming a non-doped first polycrystalline silicon film and a PSG film on the entire surface; and forming a gate oxide film on the entire surface of the fourth element formation region on the fourth element formation region. Having a narrower opening than the element formation region of A step of forming a first photoresist film covering the gate oxide film on the surface of the child formation region from an end portion of the field oxide film with a required width; and using the first photoresist film as a mask, P
The step of anisotropically etching the SG film and the first polycrystalline silicon film sequentially, and the isotropic etching using the first photoresist film as a mask, the gate oxidation on the surface of the fourth element formation region is performed. A step of forming a base opening in the film, undercutting at least the PSG film on the gate oxide film, and removing the first photoresist film, and performing ion implantation using the PSG film as a mask. At least the fourth
Forming a first p-type ion-implanted layer on the surface of the second n-well on the surface of the element forming region, removing the PSG film, and activating the first p-type ion-implanted layer by heat treatment. Of the second element on the surface of at least the fourth element formation region.
Forming a low concentration n-type collector region on the surface of the n-well, forming a non-doped second polycrystalline silicon film on the entire surface, and forming the second polycrystalline silicon film and the first polycrystalline silicon. A film is patterned to form a first polycrystalline silicon film pattern that traverses the first element formation region through the gate oxide film and the second polycrystalline silicon film pattern through the gate oxide film.
Second polycrystalline silicon film pattern crossing the element formation region of the gate and the gate left in direct contact with the surface of the fourth element formation region at the base opening and left on the surface of the fourth element formation region. Forming a third polycrystalline silicon film pattern covering the oxide film and extending on the field oxide film around the fourth element formation region; and forming an opening on the p-well. Forming a second photoresist film having the same, and implanting p-type ions into the first polycrystalline silicon film pattern by ion implantation using the second photoresist film as a mask to form the first element. Forming a first n-type ion-implanted layer on the surface of the region, removing the second photoresist film, and activating the first n-type ion-implanted layer by heat treatment to form an n-type on the p-well surface. Type saw Forming a drain region and converting the first polycrystalline silicon film pattern into a first gate electrode; and forming a third photoresist film covering the p well and the n-type collector lead-out region. Then, p-type ions are implanted into the second and third polycrystalline silicon film patterns by ion implantation using the third photoresist film as a mask, and second p-type ions are implanted on the surface of the second element formation region. Forming an ion-implanted layer, forming an insulating film on the entire surface by low temperature vapor phase epitaxy, and forming a fourth photoresist film having an opening in a region where an emitter opening is to be formed, The insulating film and the third polycrystalline silicon film pattern are sequentially etched by anisotropic etching using the fourth photoresist film as a mask to form an emitter opening, and the fourth photoresist film is formed. The low concentration n is obtained by ion implantation using the photo resist film as a mask.
A second n-type ion implantation layer is formed on the surface of the type collector region, and a third p-type ion implantation layer is formed on the surface of the low-concentration n-type collector region shallower than the second n-type ion implantation layer. A step of removing the fourth photoresist film, and a heat treatment to activate the second p-type ion implantation layer to form a p-type source / drain region on the surface of the first n-well. Activating the third p-type ion implantation layer to form a p-type base region on the surface of the low-concentration n-type collector region in a self-aligned manner with the emitter opening,
Of the high-concentration n-type SIC just below the bottom surface of the p-type base region in a self-aligned manner by activating the ion-implanted layer to self-align with the emitter opening.
A region is formed, the second polycrystalline silicon film pattern is converted into a second gate electrode, the third polycrystalline silicon film pattern is converted into a base electrode, and a p-type self-aligned with the base electrode is formed. A step of forming a mold external base region on the surface of the low-concentration n-type collector region; An insulating film spacer made of the second insulating film is formed, and an n-type third film is formed on the entire surface.
Forming a polycrystalline silicon film, patterning the third polycrystalline silicon film to form an emitter electrode, and heat treating the insulating film spacer and the emitter electrode in a self-aligned manner with the low concentration n-type A step of forming an n-type emitter region on the surface of the collector region, the method for manufacturing a Bi-CMOS semiconductor device. 5. The method for manufacturing a Bi-CMOS device according to claim 4, wherein the second polycrystalline silicon film is formed by a low pressure vapor phase epitaxy method. 6. The p-type source / drain region, the p-type base region, the high-concentration n-type SIC region, the second gate electrode,
6. The Bi-CMOS according to claim 4 or 5, wherein the heat treatment for forming the base electrode and the p-type external base region and the heat treatment for forming the n-type emitter region are the same. Manufacturing method of semiconductor device. 7. A field oxide film is formed in a region surrounding the first, second, third and fourth element forming regions on the surface of a p-type silicon substrate, and the p-type including the first element forming region is formed. A p-well is formed on the surface of the silicon substrate, and a p-well is formed on the surface of the p-type silicon substrate including the second element formation region and on the surface of the p-type silicon substrate including the third and fourth element formation regions. Forming a first n-well and a second n-well, forming an n-type collector lead-out region in the third element formation region in a self-aligned manner, the first, second, third and Forming a gate oxide film on the surface of the fourth element formation region and sequentially forming a non-doped first polycrystalline silicon film and a PSG film on the entire surface; Having a narrower opening than the element formation region of A step of forming a first photoresist film covering the gate oxide film on the surface of the child formation region from an end portion of the field oxide film with a required width; and using the first photoresist film as a mask, P
The step of anisotropically etching the SG film and the first polycrystalline silicon film sequentially, and the ion implantation using the first photoresist film as a mask to form the fourth element immediately below the region where the base opening is to be formed A step of forming a first n-type ion implantation layer on the surface of the region, and isotropic etching using the first photoresist film as a mask to form a base on the gate oxide film on the surface of the fourth element formation region. The step of forming an opening, undercutting at least the PSG film on the gate oxide film, removing the first photoresist film, and performing ion implantation using the PSG film as a mask, Forming a first p-type ion-implanted layer on the surface of the second n-well on the surface of the element formation region of the device, removing the PSG film, and performing heat treatment on the first p-type ion implantation layer. The ion implantation layer is activated to form a low concentration n-type collector region at least on the surface of the second n-well just below the gate oxide film, and the first n-type ion implantation layer is activated to form the base opening. High concentration n-type SIC on the surface of the second n-well in self-alignment with
Forming a region, forming a non-doped second polycrystalline silicon film over the entire surface, patterning the second polycrystalline silicon film and the first polycrystalline silicon film, and forming the gate oxide film A first polycrystalline silicon film pattern that traverses the first element formation region through the gate oxide film and the second polycrystalline silicon film pattern through the gate oxide film.
Second polycrystalline silicon film pattern crossing the element formation region of the gate and the gate left in direct contact with the surface of the fourth element formation region at the base opening and left on the surface of the fourth element formation region. Forming a third polycrystalline silicon film pattern covering the oxide film and extending on the field oxide film around the fourth element formation region; and forming an opening on the p-well. Forming a second photoresist film having the same, and implanting p-type ions into the first polycrystalline silicon film pattern by ion implantation using the second photoresist film as a mask to form the first element. Forming a second n-type ion-implanted layer on the surface of the region, removing the second photoresist film, activating the second n-type ion-implanted layer by heat treatment to form an n-type layer on the p-well surface. Type saw Forming a drain region and converting the first polycrystalline silicon film pattern into a first gate electrode; and forming a third photoresist film covering the p well and the n-type collector lead-out region. Then, p-type ions are implanted into the second and third polycrystalline silicon film patterns by ion implantation using the third photoresist film as a mask, and second p-type ions are implanted on the surface of the second element formation region. Forming an ion-implanted layer, forming an insulating film on the entire surface by low temperature vapor phase epitaxy, and forming a fourth photoresist film having an opening in a region where an emitter opening is to be formed, The insulating film and the third polycrystalline silicon film pattern are sequentially etched by anisotropic etching using the fourth photoresist film as a mask to form an emitter opening, and the fourth photoresist film is formed. The high concentration n is obtained by ion implantation using the photo resist film as a mask.
A step of forming a third p-type ion implantation layer on the surface of the type SIC region, a step of removing the fourth photoresist film, and a heat treatment to activate the second p-type ion implantation layer. A p-type source / drain region is formed on the surface of the first n-well, the third p-type ion implantation layer is activated, and the high-concentration n-type SIC is self-aligned with the emitter opening.
A p-type base region is formed on the surface of the region, the second polycrystalline silicon film pattern is converted into a second gate electrode, the third polycrystalline silicon film pattern is converted into a base electrode, and the base is formed. Forming a p-type external base region self-aligned with the electrode on the surface of the high-concentration n-type SIC region, forming a second insulating film on the entire surface, and etching back the second insulating film. An insulating film spacer made of the second insulating film is formed on a side surface of the emitter opening, and an n-type third spacer is formed on the entire surface.
Forming a polycrystal silicon film and patterning the third polycrystal silicon film to form an emitter electrode; A step of forming an n-type emitter region on the surface of the SIC region, the method for manufacturing a Bi-CMOS semiconductor device. 8. The method of manufacturing a Bi-CMOS device according to claim 7, wherein the second polycrystalline silicon film is formed by a low pressure vapor phase epitaxy method. 9. A heat treatment for forming the p-type source / drain region, the p-type base region, the second gate electrode, the base electrode and the p-type external base region, and forming the n-type emitter region. 9. The Bi according to claim 7, wherein the heat treatment is the same heat treatment.
-Method for manufacturing a CMOS semiconductor device.