JPH0974429A - Digital quadrature modulator - Google Patents

Abstract

(57) Abstract: A digital quadrature modulator obtains a modulated signal having a frequency of 1/4 of the maximum processing speed of a D / A converter. SOLUTION: Baseband I and Q signals 13 and 14 are bandlimited baseband I and Q signals 15 and 16 through prefilters 30 and 31 and digital bandpass filters 1 and 2, respectively. The signal is passed through the polarity inverters 32 and 33, and the P / S converter is combined with the baseband I and Q signals 38 and 39 whose polarities are inverted.
Entered in 34. The P / S converter 34 synthesizes the respective signals input in chronological order at the timing of the clock 17. The D / A converter 9 converts the digital modulation signal 23 into the analog modulation signal 24 at the timing of the clock 17, and the low pass filter 10
The unnecessary frequency component is removed by and the analog signal 25 is output.
The analog signal 25 is mixed with the local oscillation signal 26 by the image rejection mixer 35 and up-converted to output the analog signal 27. Further, the bandpass filter 12 removes unnecessary frequency components and outputs the modulated signal 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulator used in a wireless device used for digital mobile communication or the like.

[0002]

2. Description of the Related Art A conventional digital quadrature modulator is shown in FIG.
It is configured as shown in FIG. In FIG. 7, 1, 2
Is a digital band limiting filter for band limiting the baseband I and baseband Q signals respectively, 3 and 4 are multipliers for multiplying the baseband I and baseband Q signals by the carrier signal, and 5 is a COS waveform signal and a SIN waveform signal. A counter to call, 6 is a CO that outputs a COS waveform signal
S waveform signal ROM, 7 is SI for outputting SIN waveform signal
N waveform signal ROM, 8 is an adder for adding I and Q signals,
9 is a D / A converter for converting a digital modulation signal into an analog modulation signal, 10 is a low pass filter for removing unnecessary frequency components of the analog modulation signal, 11 is a low pass filter 10
Is an analog mixer that mixes the analog signal output by the local oscillation signal and up-converts it; and 12 is a band-pass filter that removes unnecessary frequency components of the up-converted analog signal output by the analog mixer 11.

In the digital quadrature modulator constructed as described above, first, the baseband I signal 13 and the baseband Q signal 14 are digital band limiting filters 1 and 1, respectively.
2 is input and the band is limited. Next, the band-limited baseband I signal 15 and the band-limited baseband Q
The signal 16 is input to the multipliers 3 and 4. Further, the sampling frequency clock 17 is input to the counter 5, and the control signal
18 is output. This control signal 18 is a COS waveform signal RO
M6 and SIN waveform signal ROM 7 are input, and COS waveform signal 19 and SIN waveform signal 20 of the carrier signal are output and input to multipliers 3 and 4, respectively. The band-limited baseband I signal 15 and the COS waveform signal 19 are multiplied by the multiplier 3 and an I signal 21 is output. Similarly, the band-limited baseband Q signal 16 and the SIN waveform signal 20 are also multiplied by the multiplier 4 to output a Q signal 22.

Next, the I signal 21 and the Q signal 22 are added by the adder 8 and the digital modulation signal 23 is output. The digital modulation signal 23 is input to the D / A converter 9, and the analog modulation signal 24 is obtained. An unnecessary frequency component is removed from the analog modulation signal 24 by the low pass filter 10, and an analog signal 25 is obtained. The analog signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 and up-converted to obtain an up-converted analog signal 27. Finally, the up-converted analog signal 27 is input to the bandpass filter 12 and the unnecessary frequency component is removed, whereby the modulated signal 28 is obtained.

[0005]

However, the modulated signal output from the quadrature modulator is generally mixed with the local oscillation signal in the subsequent stage to be up-converted, and the components other than the necessary signal components are removed by the filter. . However, as the frequency of the modulation signal becomes lower, a steep filter is required, and it becomes difficult to realize the filter. Therefore, it is necessary to increase the frequency of the modulation signal output from the quadrature modulator. However, the frequency of the modulated signal output by the quadrature modulator depends on the operating speed of the multiplier used. For example, if the number of operation bits is 10 bits, the maximum processing speed of the current general commercial 10-bit digital multiplier is 40 MHz.
z, and the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz. In the digital quadrature modulator having the above-mentioned configuration, when the number of samplings per cycle is 4, there is a problem that the frequency of the modulation signal is limited to 1/4 of the maximum operation speed of the multiplier.

The present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to provide a digital quadrature modulator capable of outputting a modulation signal having a frequency of 1/4 of the maximum processing speed of a D / A converter. And

[0007]

To achieve this object, the present invention provides a pre-filter for attenuating aliasing noise generated after converting a digital signal into an analog signal to a predetermined level and a baseband I, Q signal. A digital band-limited filter that limits the band, a polarity inverter that inverts the polarity of the output signal of the digital band-limited filter, and an output signal of the digital band-limited filter and an output signal of the polarity inverter are combined in time order to obtain a digital modulation signal. Get parallel / serial (Paralell-Serial) converter (P / S
Converter), a D / A converter for converting a digital modulation signal into an analog modulation signal, a low-pass filter for removing unnecessary frequency components of the converted analog modulation signal, and an output signal of the low-pass filter as a local oscillation signal. An image rejection mixer that mixes and up-converts, and a bandpass filter that removes unnecessary frequency components of the output signal from the image rejection mixer, and a modulated signal is obtained from the output of the bandpass filter. .

A polarity inverter for inverting the polarities of the baseband I and Q signals, and a P / S converter for synthesizing the baseband I and Q signals and the output signal of the polarity inverter in time order to obtain a digital modulation signal. A D / A converter for converting a digital modulation signal into an analog modulation signal; a low-pass filter for removing unnecessary frequency components of the converted analog modulation signal; and an output signal of the low-pass filter mixed with a local oscillation signal for up. The image rejection mixer for conversion and a band limiting filter for limiting the band of the output signal from the image rejection mixer are provided, and the modulation signal is obtained from the output of the band limiting filter.

A digital band limiting filter for band limiting the base band I and Q signals, and a polarity inverter for inverting the polarity of the output signal of the digital band limiting filter,
A P / S converter for synthesizing the output signal of the digital band limiting filter and the output signal of the polarity inverter in time order to obtain a digital modulation signal; and a D / A converter for converting the digital modulation signal into an analog modulation signal, A second bandpass filter that extracts high-order harmonic components from the converted analog modulated signal and removes unnecessary frequency components, and image rejection that mixes the output signal of the second bandpass filter with the local oscillation signal and up-converts it. It is characterized in that it comprises a mixer and a bandpass filter for removing unnecessary frequency components of an output signal from the image rejection mixer, and the modulated signal is obtained from the output of the bandpass filter.

Further, a digital band limiting filter for band limiting the base band I and Q signals, a polarity inverter for inverting the polarity of the output signal of the digital band limiting filter,
A P / S converter for synthesizing the output signal of the digital band limiting filter and the output signal of the polarity inverter in time order to obtain a digital modulation signal, and a second P / S converter for inverting the polarity of the digital modulation signal output by the P / S converter. D / A for converting the output signal of the polarity inverter and the second polarity inverter into an analog modulation signal
An image of a converter, a third band-pass filter for extracting a folding noise component from the converted analog modulated signal and removing an unnecessary frequency component, and an up-convert by mixing an output signal of the third band-pass filter with a local oscillation signal. It is composed of a rejection mixer and a bandpass filter for removing unnecessary frequency components of an output signal from the image rejection mixer, and is configured to obtain a modulated signal from the output of the bandpass filter.

[0011]

According to the above construction, the digital quadrature modulator is constructed without using each waveform signal ROM or multiplier, so that a modulated signal having a frequency of 1/4 of the maximum processing speed of the D / A converter is obtained. .

Further, a band limiting filter for limiting the band is provided in the rear stage part to reduce the number of operation bits processed by the D / A converter, speed up the processing speed, and increase the frequency of the modulated signal.

Further, by the second bandpass filter,
The high-order harmonic signal is taken out to remove unnecessary frequency components and used as a desired signal to increase the frequency of the modulated signal.

The second polarity inverter for inverting the polarity of the digital modulation signal output from the P / S converter and the third band pass filter extract the aliasing noise component and remove the unnecessary frequency component to obtain the desired signal. Is used to increase the frequency of the modulated signal.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital quadrature modulator according to the first embodiment of the present invention. Moreover, the same reference numerals are given to those having the same effects and advantages described in FIG. 7 of the conventional example, and the same applies to the following drawings. In FIG. 1, 1 and 2 are digital band limiting filters, 9 is a D / A converter, 10 is a low-pass filter, 12 is a band-pass filter, and 30 and 31 are folding noises generated after converting a digital signal into an analog signal. Pre-filter for attenuating only level, 32 and 33 are polarity inverters that invert the polarities of input signals, and 34 is a P / S converter that combines the signals input from four systems in time order and converts them into one system of signals , 35 are image rejection mixers for up-converting by mixing an analog signal output from the low-pass filter 10 with a local oscillation signal.

FIGS. 2 and 3 are timing charts showing the signals of the digital quadrature modulator in the first embodiment. In FIG. 2, A is a sampling frequency clock (corresponding to the clock 17 shown in FIG. 1), B is a clock obtained by dividing the clock A by 2, and C is a clock obtained by dividing the clock A by 4. Is band-limited baseband I
Signal (band-limited baseband I signal 15 shown in FIG.
, Dq is a band-limited baseband Q signal (corresponding to the band-limited baseband Q signal 16 shown in FIG. 1), Ei is a polarity-inverted baseband I signal obtained by inverting the polarity of the band-limited baseband I signal Di, Eq is the band-limited baseband Q
A polarity-inverted baseband Q signal obtained by inverting the polarity of the signal Dq,
Fi is a signal obtained by the logical product of the band-limited baseband I signal Di and the divide-by-four clock C, Gi is obtained by the logical product of the polarity-inverted baseband I-signal Ei and the polarity-inverted divide-by-4 clock C. Signal, Hi is a signal obtained by the logical sum of the signals Fi and Gi, Fq is a signal obtained by the band-limited baseband Q signal Dq and the logical product of the quarter clock C, and Gq is a polarity inversion baseband Hq is a signal obtained by the logical product of the Q signal Eq and the frequency-divided quarter clock C, and Hq is a signal obtained by the logical sum of the signal Fq and the signal Gq.

Further, in FIG. 3, Ji is a signal obtained by the logical product of the signal Hi and the frequency-divided clock B, and Jq is obtained by the logical product of the signal Hq and the frequency-divided clock B divided by two. The signal K is a digital modulation signal (corresponding to the digital modulation signal 23 shown in FIG. 1) obtained by the logical sum of the signals Ji and Jq.

The operation of the digital quadrature modulator of the first embodiment having the above configuration will be described.
First, the baseband I signal 13 and the baseband Q signal
14 is input to the pre-filters 30 and 31, respectively. The pre-filters 30 and 31 attenuate the frequency component closest to the modulation signal among the aliasing noises generated after conversion to the analog signal by a predetermined level.

The baseband I signal 36 and the baseband Q signal 37 output from the pre-filters 30 and 31 are band-limited by the digital band limiting filters 1 and 2, respectively, and the band-limited base band I signal 15 and
The band-limited baseband Q signal 16 (band-limited baseband I signal Di, band-limited baseband Q signal Dq) is obtained.

Further, the band-limited baseband I signal 15 and the band-limited baseband Q signal 16 are polarity-inverted by the polarity inverters 32 and 33, respectively, and the polarity-inverted baseband I signal 38 and polarity-inverted signal are respectively inverted. The obtained baseband Q signal 39 (polarity inversion baseband I signal Ei, polarity inversion baseband Q signal Eq) is obtained.

The band-limited baseband I signal 15, the band-limited baseband Q signal 16, the polarity-inverted baseband I signal 38, and the polarity-inverted baseband Q signal 39 are sent to the P / S converter 34. Is entered. These signals are P
The / S converter 34 synthesizes in time order at the timing of the clock cycle of the sampling frequency.

That is, as shown in the timing chart of FIG. 2, the signal Fi is obtained by the logical product of the band-limited baseband I signal Di and the quarter clock C, and the polarity is inverted with the polarity-inverted baseband I signal Ei. The signal Gi is obtained by the logical product with the divide-by-four clock C. The signal Hi (Si
(nT / 2)) is obtained.

[0023]

[Equation 1] However, n: 0,1,2, ..., k: 0,1,2, ..., T:
1 / modulation frequency.

Similarly, a signal Fq is obtained by the logical product of the band-limited baseband Q signal Dq and the divide-by-four clock C, and the logic of the polarity-inverted baseband Q-signal Eq and the inverted-quarter-divide clock C is obtained. The product gives the signal Gq. The signal Hq (Sq (nT / 2)) shown in (Equation 2) is obtained by the logical sum of the signal Fq and the signal Gq.

[0025]

[Equation 2] However, n: 0,1,2, ..., k: 0,1,2, ..., T:
1 / modulation frequency.

Next, as shown in the timing chart of FIG. 3, the signal Ji is obtained by the logical product of the signal Hi and the frequency-divided clock B, and the signal Jq is obtained by the logical product of the signal Hq and the frequency-divided clock B of 2. To be The digital modulation signal K (DATA (nT) shown in (Equation 3) is obtained by the logical sum of the signals Ji and Jq.
/ 4)) is obtained.

[0027]

(Equation 3) However, n: 0,1,2, ..., k: 0,1,2, ..., T:
1 / modulation frequency.

The D / A converter 9 converts the input digital modulation signal 23 (digital modulation signal K) into an analog signal at the timing of the sampling frequency of the clock 17 (clock A) and outputs the analog modulation signal 24. The low-pass filter 10 outputs an analog signal 25 from which unnecessary frequency components of the analog modulation signal 24 are removed, and the analog signal 25 is input to the image rejection mixer-35 and mixed with the local oscillation signal 26 to be up-converted analog. The signal 27 is output. Here, the image wave generated after the up-conversion can be attenuated by a predetermined level by using the image rejection mixer 35 as the analog mixer. Further, the up-converted analog signal 27 is input to the bandpass filter 12, the unnecessary frequency components are removed, and the modulated signal 28 is output.

As described above, by configuring the digital quadrature modulator without using the waveform signal ROM and the multiplier, the number of samplings per cycle is set to 4 D / A
It is possible to realize a digital quadrature modulator capable of obtaining a modulation signal having a frequency of 1/4 of the maximum processing speed of the converter 9.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. But the general market 1
Since the maximum processing speed of the 0-bit D / A converter is about 400 MHz, the modulation frequency can be set to about 100 MHz according to the configuration of the present invention, and a modulation signal having a frequency 10 times that of the conventional configuration can be obtained. be able to. Further, by using the image rejection mixer as the analog mixer, it is possible to easily realize the bandpass filter by attenuating the image wave generated after the up conversion by a predetermined level.

FIG. 4 is a block diagram showing the structure of a digital quadrature modulator according to the second embodiment of the present invention. In FIG. 4, 9 is a D / A converter, 10 is a low-pass filter, 32 and 33 are polarity inverters, 34 is a P / S converter, 35 is an image rejection mixer, 40 is an image rejection mixer 35. It is a band limiting filter that limits the band of the up-converted analog signal 27 output from.

The second embodiment differs from the first embodiment in that the baseband pre-filters 30, 31,
Except for the digital band limiting filters 1 and 2, the band limiting filter 40 for limiting the band of the up-converted analog signal 27 is provided. The baseband I, Q signals 13, 14 and the baseband I, Q signals 38, 39 which have passed through the polarity inverters 32, 33 and have their polarities inverted are input to the P / S converter 34. Since the process is the same as that of the first embodiment until the up-converted analog signal 27 is obtained after passing through the D / A converter 9, the low-pass filter 10 and the image rejection mixer 35, the description thereof will be omitted. When the bandwidth is limited in the baseband section, about 12 bits are required to obtain sufficient characteristics. If band limitation is performed by the band limiting filter 40 provided at the subsequent stage, the number of operation bits can be reduced to about 8 bits. In this way, the band limiting filter 40
Obtains a modulated signal 28 by band-limiting the input up-converted analog signal 27.

As described above, in the second embodiment, by providing the band limiting filter 40 for band limiting in the rear stage,
By reducing the number of operation bits processed by the D / A converter 9 and increasing the processing speed thereof to increase the speed of the digital quadrature modulator, the frequency of the modulated signal can be increased as compared with the first embodiment. it can.

FIG. 5 is a block diagram showing the structure of a digital quadrature modulator according to the third embodiment of the present invention. In FIG. 5, reference numerals 1 and 2 denote digital band limiting filters, and 9
Is a D / A converter, 12 is a bandpass filter, 32 and 33 are polarity invertors, 34 is a P / S converter, 35 is an image rejection mixer, and 41 is output from the D / A converter 9. It is a second band-pass filter that extracts high-order harmonic components of the analog modulation signal 24 as an output signal and removes unnecessary frequency components.

The third embodiment differs from the first embodiment in that the high-order harmonics of the analog modulation signal 24 output from the D / A converter 9 are removed except for the pre-filters 30 and 31 in the base band section. The configuration is provided with a second bandpass filter 41 that extracts a wave component as an output signal and removes an unnecessary frequency component. The baseband I and Q signals 13 and 14 pass through the digital band limiting filters 1 and 2 and the analog modulated signal 24 is obtained from the band limited baseband I and Q signals 15 and 16 as in the first embodiment. Since they are the same, the description thereof will be omitted. The second bandpass filter 41 is a high-order harmonic (for example, a second-order harmonic) of the input analog modulation signal 24.
An analog signal 25 is obtained by extracting the signal as a desired signal and removing unnecessary frequency components.

The image rejection mixer 35 mixes the input analog signal 25 with the local oscillation signal 26 and outputs an up-converted analog signal 27. here,
The image wave generated after up-conversion can be attenuated by a predetermined level by using the image rejection mixer-35. Further, the band pass filter 12 obtains a modulated signal 28 by removing unnecessary frequency components of the input up-converted analog signal 27.

As described above, in the third embodiment, by using the high-order harmonic signal as the desired signal, it is possible to further increase the frequency of the modulation signal as compared with the first embodiment. According to the sampling theorem, the frequency of the second-order harmonic component is five times the frequency of the fundamental wave component.
It is possible to obtain a modulation signal having a frequency five times as high as that of the embodiment.

FIG. 6 is a block diagram showing the arrangement of a digital quadrature modulator according to the fourth embodiment of the present invention. In FIG. 6, 1 and 2 are digital band limiting filters, and 9
Is a D / A converter, 12 is a bandpass filter, 32 and 33 are polarity invertors, 34 is a P / S converter, 35 is an image rejection mixer, and 42 is a second for inverting the polarity of the digital modulation signal 23. The polarity reversing device 43 is a third bandpass filter that extracts the aliasing noise component of the analog modulation signal 24 output from the D / A converter 9 as an output signal and removes unnecessary frequency components.

The difference between the fourth embodiment and the first embodiment is that the digital modulation signal 23 output from the P / S converter 34 is removed except for the pre-filters 30 and 31 in the base band section.
Second polarity invertor 42 for inverting the polarity of the signal and a third band-pass filter 43 for removing an aliasing noise component of the analog modulation signal 24 output from the D / A converter 9 as an output signal and removing an unnecessary frequency component. It has a configuration with. The baseband I and Q signals 13 and 14 pass through the digital bandpass filters 1 and 2 to be bandlimited baseband I and Q.
It is the first until the digital modulated signal 23 is obtained from the signals 15 and 16.
Since it is the same as the embodiment described above, the description thereof will be omitted. Since the aliasing noise component is a signal obtained by inverting the polarity of the fundamental modulation wave, the polarity inverter 42 outputs the digital signal 44 in which the polarity of the digital modulation signal 23 is inverted. A / D converter 9
Thus, the digital signal 44 is converted into an analog signal and the analog modulation signal 24 is obtained. Further analog modulated signal 24
Is input to the third bandpass filter 43, the aliasing noise component is extracted as a desired signal, and the unnecessary frequency component is removed to output the analog signal 25.

The image rejection mixer 35 mixes the input analog signal 25 with the local oscillation signal 26 and up-converts it to output an analog signal 27. Here, the image wave generated after up-conversion can be attenuated by a predetermined level by using the image rejection mixer 35. Further, the up-converted analog signal 27 is input to the bandpass filter 12 and the unnecessary frequency component is removed, whereby the modulation signal 28 is obtained.

As described above, in the fourth embodiment, by using the aliasing noise component as the desired signal, it is possible to further increase the frequency of the modulated signal as compared with the first embodiment. According to the sampling theorem, the frequency of the aliasing noise component is three times the frequency of the fundamental wave component, so that a modulated signal having a frequency three times that of the first embodiment can be obtained.

[0042]

As described above, according to the present invention,
By configuring the digital quadrature modulator without using each waveform signal ROM or multiplier and setting the number of samplings per period to 4, a modulation signal having a frequency of 1/4 of the maximum processing speed of the D / A converter is obtained. Can be obtained.

Further, by providing a band limiting filter for limiting the band in the subsequent stage, the number of operation bits processed by the D / A converter can be reduced, the processing speed can be increased, and the frequency of the modulated signal can be increased. You can

Further, by extracting and using the high-order harmonic signal as the desired signal by the second bandpass filter, the frequency of the second-order harmonic component is 5 times the fundamental wave component according to the sampling theorem. Further, the frequency of the modulated signal can be increased.

Further, by using the folding noise component as a desired signal by using the second polarity inverter and the third bandpass filter, the frequency of the folding noise component is three times that of the fundamental wave component according to the sampling theorem. For,
Further, there is an effect that the frequency of the modulated signal can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital quadrature modulator according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing each signal of the digital quadrature modulator in the first embodiment of the present invention.

FIG. 3 is a timing chart showing each signal of the digital quadrature modulator in the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a digital quadrature modulator according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a digital quadrature modulation device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a digital quadrature modulator according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional digital quadrature modulator.

[Explanation of symbols]

1, 2 ... Digital band limiting filter, 3, 4 ... Multiplier, 5 ... Counter, 6 ... COS waveform signal ROM, 7
... SIN waveform signal ROM, 8 ... adder, 9 ... D / A
Converter, 10 ... Low-pass filter, 11 ... Analog mixer, 12 ... Band pass filter, 30, 31 ... Pre-filter, 32, 33 ... Polarity inverter, 34 ... P / S (Paralell-
Serial) converter, 35 ... Image rejection mixer, 40 ... Band limiting filter, 41 ... Second bandpass filter, 42 ... Second polarity inverter, 43 ... Third bandpass filter.

Claims (4)

[Claims] 1. A prefilter for attenuating aliasing noise generated after converting a digital signal into an analog signal to a predetermined level, a digital band limiting filter for band limiting the baseband I and Q signals, and an output of the digital band limiting filter. A polarity inverter for inverting the polarity of the signal, a parallel / serial converter for synthesizing the output signal of the digital band limiting filter and the output signal of the polarity inverter in time order to obtain a digital modulation signal, and the digital modulation signal A D / A converter for converting into an analog modulation signal,
A low-pass filter for removing unnecessary frequency components of the converted analog modulated signal, an image rejection mixer for up-converting an output signal of the low-pass filter with a local oscillation signal, and an output from the image rejection mixer. A digital quadrature modulator comprising a bandpass filter for removing unnecessary frequency components of a signal, wherein a modulated signal is obtained from an output of the bandpass filter. 2. A polarity inverter for inverting the polarities of baseband I and Q signals, and a parallel / serial device for synthesizing the baseband I, Q signals and the output signal of the polarity inverter in time sequence to obtain a digital modulation signal. A converter, a D / A converter for converting the digital modulation signal into an analog modulation signal, a low-pass filter for removing unnecessary frequency components of the converted analog modulation signal, and an output signal of the low-pass filter for a local oscillation signal. An image rejection mixer that mixes with and up-converts, and a band-limiting filter that band-limits an output signal from the image-rejection mixer, and a modulated signal is obtained from an output of the band-limiting filter. And a digital quadrature modulator. 3. A digital band limiting filter for band limiting the baseband I and Q signals, a polarity inverter for inverting the polarity of the output signal of the digital band limiting filter, an output signal of the digital band limiting filter and the polarity. A parallel / serial converter for synthesizing the output signal of the inverter in time order to obtain a digital modulation signal; a D / A converter for converting the digital modulation signal into an analog modulation signal;
A second bandpass filter for extracting high-order harmonic components from the converted analog modulated signal and removing unnecessary frequency components, and an image of up-converting by mixing an output signal of the second bandpass filter with a local oscillation signal. A digital quadrature modulator comprising a rejection mixer and a bandpass filter for removing unnecessary frequency components of an output signal from the image rejection mixer, wherein a modulation signal is obtained from an output of the bandpass filter. . 4. A digital band limiting filter for band limiting the base band I and Q signals, a polarity inverter for inverting the polarity of the output signal of the digital band limiting filter, an output signal of the digital band limiting filter and the polarity. A parallel / serial converter for synthesizing the output signal of the inverter in time order to obtain a digital modulation signal; a second polarity inverter for inverting the polarity of the digital modulation signal output by the parallel / serial converter; A D / A converter for converting the output signal of the second polarity inverter into an analog modulation signal; a third bandpass filter for extracting a folding noise component from the converted analog modulation signal and removing an unnecessary frequency component; Image rejection mixer that mixes the output signal of the third bandpass filter with the local oscillation signal and up-converts the signal. And a bandpass filter for removing unnecessary frequency components of an output signal from the image rejection mixer, and a modulated signal is obtained from an output of the bandpass filter.