JPH098301A - Power semiconductor device - Google Patents

Abstract

(57) Abstract: A power semiconductor device having a buried insulated gate structure with less conduction loss is provided. A low resistance p-type emitter layer is formed on the back surface of a high resistance n-type base layer. A p-type base layer 3 is formed in the surface of the n-type base layer 1. In the p-type base layer 3 and the n-type base layer 1, penetrating the p-type base layer 3 and n
A plurality of trenches 1 having a depth reaching the middle of the mold base layer 1
7 is formed. An inter-trench region 10 made of a semiconductor is defined between the trenches 17. In the surface of the p-type base layer 3, a low-resistance n-type emitter layer 4 contacting the upper portion of the trench 17 is formed. The gate electrode 5 is formed in the trench 17 via the gate insulating film 6. The side surface of the inter-trench region 10 facing the gate electrode 5 is {10
0} plane.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device for controlling high power, and more particularly to a power semiconductor device having a buried insulated gate structure.

[0002]

2. Description of the Related Art As a semiconductor device for power control, a device having a buried insulated gate structure, for example, an IGBT (In
sulated Gate Bipolar Transistor) is known.
FIG. 24 is a sectional view showing a conventional semiconductor device (IGBT) having a buried insulated gate structure. FIG. 25 shows FIG.
It is a top view which shows the semiconductor substrate 92 used for manufacture of the illustrated semiconductor device. The semiconductor substrate 92 has a main surface composed of a {100} plane and an orientation flat 93 formed along the <110> direction.

In FIG. 24, a high resistance n-type base layer 8 is formed.
A p-type base layer 83 is formed in the surface of 1. In the p-type base layer 83 and the n-type base layer 81, a trench 97 is formed that penetrates the p-type base layer 83 and reaches a depth in the middle of the n-type base layer 81. The dominant sidewall surface of the trench 97 is the {110} plane. This is because the trench pattern formed in the semiconductor substrate 92 is formed parallel or perpendicular to the orientation flat 93.

A gate electrode 85 is buried in the trench 97 via a gate insulating film 86. A low resistance n-type emitter layer 84 is formed in the surface of the p-type base layer 83 so as to contact the upper portion of the trench 97.

A p-type base layer 83 and an n-type emitter layer 84
Cathode electrode 87 is arranged so as to contact both of them. The cathode electrode 87 is insulated from the gate electrode 85. On the other hand, on the back surface of the n-type base layer 81, p having a low resistance
The type emitter layer 82 is formed. An anode electrode 88 is provided on the p-type emitter layer 82.

The operation of the semiconductor device configured as described above is as follows. That is, at turn-on, a positive voltage (positive bias voltage) is applied to the gate electrode 85 with respect to the cathode. Due to this positive bias voltage, an n-type channel is formed in the p-type base layer 83 around the trench 97, and the n-type emitter layer 84 and the n-type base layer 81 are short-circuited. Further, this positive bias voltage causes the n-type base layer 8
Within 1, a storage layer (not shown) in which electrons are stored is formed around the trench 97.

As a result, an electron current Je flows through the n-type channel into the n-type base layer 81, and this electron current J
A number of holes corresponding to e are injected from the p-type emitter layer 82 into the n-type base layer 81. As a result, carriers are accumulated in the n-type base layer 81, conductivity modulation occurs in the n-type base layer 81, and the resistance of the n-type base layer 81 decreases. In this way, a current flows between the anode and the cathode.

On the other hand, when turned off, the gate electrode 85
A zero voltage or a negative voltage (negative bias voltage) is applied to the cathode. As a result, the n-type channel disappears, and no electrons are injected from the n-type emitter layer 84 to the n-type base layer 81. As a result, the n-type base layer 81 does not cause conductivity modulation, and the semiconductor device eventually becomes non-conductive.

However, this type of semiconductor device has the following problems. That is, although the electron current Jacc, which is a part of the electron current Je, passes through the storage layer, most of the electron current Jb flows away from the storage layer. In this case, the electrons separated from the storage layer are recombined with the holes supplied from the n-type base layer 81 in the inter-trench region 90 and disappear. Thus, when the electrons disappear by recombination of electrons and holes before reaching the region 89 directly below the trench 97, the region 89
The amount of carriers accumulated inside is small and conduction loss is large.

[0010]

As described above, in the conventional power semiconductor device having the buried insulated gate structure, the amount of carriers accumulated in the n-type base layer immediately below the trench is small and the conduction loss is low. Grows larger. Therefore, it is an object of the present invention to provide a power semiconductor device having a buried insulated gate structure, which has a smaller conduction loss than conventional ones.

[0011]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
In a power semiconductor device, a first conductivity type emitter layer,
A second conductivity type base layer formed on the first conductivity type emitter layer and causing conductivity modulation in an ON state of the device; and a first conductivity type base layer formed in a surface of the second conductivity type base layer. A plurality of trenches penetrating the first conductivity type base layer and reaching a depth in the middle of the second conductivity type base layer, the trenches being formed so as to define a plurality of current paths,
A gate electrode buried in a trench via a gate insulating film so as to face each current path, and a second conductivity type emitter formed in each current path and on the surface of the first conductivity type base layer. A layer, and a first main electrode connected to the second conductivity type emitter layer and the first conductivity type base layer,
A second main electrode connected to the first conductivity type emitter layer;
And a side surface of the current path facing the gate electrode is substantially a {100} plane, and in the ON state of the device, in the side surface of the current path and in the second conductivity type base layer. An accumulation layer of second conductivity type carriers is formed, and the second conductivity type carriers are injected through the accumulation layer into a region in the second conductivity type base layer below the trench.

A second aspect of the present invention is the power semiconductor device according to the first aspect, in which the depth of the trench in the second conductive type base layer is D and the width of the current path is 2 W.
s, when the distance between the adjacent current paths is 2 Wt, X defined by the formula X = (Wt + D) / Ws is X
It is characterized by satisfying ≧ 5.

A third aspect of the present invention is, in a power semiconductor device, a first conductivity type emitter layer and a second conductivity type which is formed on the first conductivity type emitter layer and causes conductivity modulation in an ON state of the device. -Type base layer, a second-conductivity-type emitter layer formed in the surface of the second-conductivity-type base layer, and a depth that penetrates the second-conductivity-type emitter layer and is in the middle of the second-conductivity-type base layer. A plurality of trenches formed to reach a plurality of current paths, a gate electrode buried in the trench via a gate insulating film so as to face each current path, and the second conductivity type A first main electrode connected to the emitter layer and a second main electrode connected to the first conductivity type emitter layer, and a side surface of the current path facing the gate electrode is substantially {100. }
And a storage layer of a second conductivity type carrier is formed in the side surface of the current path and in the second conductivity type base layer in the ON state of the device, and through the storage layer.
The second conductivity type carriers are injected into a region in the second conductivity type base layer below the trench.

A fourth aspect of the present invention is the power semiconductor device according to any one of the first to third aspects, wherein the impurity concentration of the second conductivity type base layer is 2 × 10 ¹⁴ cm ⁻³ or less. It is characterized by

A fifth aspect of the present invention is the power semiconductor device according to any one of the first to fourth aspects, wherein the power semiconductor device is provided between the first conductive type emitter layer and the second conductive type base layer. The second conductivity type buffer layer is further provided.

A sixth aspect of the present invention is the power semiconductor device according to any one of the first to fifth aspects, further comprising a low carrier lifetime layer formed in the second conductivity type base layer. It is characterized by

A seventh aspect of the present invention is the power semiconductor device according to any one of the first to sixth aspects, in which each trench is located between a plurality of trench portions and between the trench portions, and the surface is insulated. And a region between dummy trenches covered with a film.

An eighth aspect of the present invention is the power semiconductor device according to any one of the first to seventh aspects, which surrounds the trench and the current path and has substantially the same depth as the trench. The present invention further comprises a first conductivity type ring layer formed in the surface of the second conductivity type base layer.

A ninth aspect of the present invention is, in the power semiconductor device according to the eighth aspect, a gate leader connected to the gate electrode and disposed on the first conductivity type ring layer via an insulating film. It is characterized by further comprising an electrode and a low resistance electrode formed of a metal thin film provided on the extraction electrode.

According to the study by the present inventors, in the conventional power semiconductor device having the buried insulated gate structure shown in FIG. 24, the cause of most of the electron current flowing away from the storage layer is the trench. Do you get it.

That is, the sidewall surface of the conventional trench is {11
0} plane, in which case the resistance of the storage layer is high. As a result, the electrons move not in the high-resistance storage layer but in other portions of the low-resistance region in the inter-trench region, and disappear due to recombination of electrons and holes. Therefore, n just below the trench
The amount of carriers accumulated in the mold base layer is reduced,
The conduction loss increases.

On the other hand, the sidewall surface of the trench is {10
In the case of the 0 plane, the resistance of the storage layer is sufficiently low and most of the electrons move in the storage layer. That is, according to the present invention based on this knowledge, the resistance of the storage layer formed along the sidewall surface of the trench is sufficiently low. Therefore, the second main electrode side (cathode side) immediately below the second trench
The amount of carriers accumulated in the conductivity type base layer increases,
The conduction loss is reduced as compared with the conventional case.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is p-type and the second conductivity type is n-type. FIG. 1 is a sectional view showing a main part of a power semiconductor device according to an embodiment of the present invention. 2 is a plan view showing a semiconductor substrate 14 used for manufacturing the power semiconductor device shown in FIG.
The semiconductor substrate 14 has a main surface composed of {100} planes and <1
Orientation flat 15 formed along the 00> direction.

In FIG. 1, a low resistance p-type emitter layer 2 is formed on the back surface of a high resistance n-type base layer 1. A p-type base layer 3 is formed in the surface of the n-type base layer 1. n
The impurity concentration of the mold base layer 1 is preferably 2 × 10 ¹⁴ cm ⁻³ or less.

In the p-type base layer 3 and the n-type base layer 1, a plurality of trenches 17 are formed which penetrate the p-type base layer 3 and reach the middle of the n-type base layer 1. Therefore, the inter-trench region 10 made of semiconductor, that is, the current path is defined between the trenches 17. The gate electrode 5 is formed in the trench 17 via the gate insulating film 6.

The surface shape (planar shape) of the trench 17 is rectangular, and its short side is sufficiently smaller than its long side. The same long side is formed so as to be parallel or perpendicular to the orientation flat 15. Therefore, the interface between the trench 17 and the inter-trench region 10 corresponding to the same long side is {10
Spread along the 0} plane. The surface shape (planar shape) of the trench 17 is not limited to the rectangular shape. The point is that the ratio of the {100} plane to the side surface of the inter-trench region 10 facing the gate electrode 5 should be sufficiently high.

A trench 17 is formed in the surface of the p-type base layer 3.
A low resistance n-type emitter layer 4 is formed in contact with the upper part of the. A cathode electrode 7 is arranged so as to contact both the p-type base layer 3 and the n-type emitter layer 4. The cathode electrode 7 is insulated from the gate electrode 5. On the other hand, the anode electrode 8 is arranged so as to contact the p-type emitter layer 2.

The operation of the power semiconductor device having the above structure is as follows. That is, at turn-on,
With the voltage (forward bias voltage) applied between the anode and the cathode so that the anode becomes positive, the gate electrode 5
A positive voltage (positive bias voltage) is applied to the cathode. Due to this positive bias voltage, the n-type channel 21 is formed in the p-type base layer 3 around the trench 17, and the n-type emitter layer 4 and the n-type base layer 1 are short-circuited. Further, due to this positive bias voltage, in the n-type base layer 1, the accumulation layer 22 in which electrons are accumulated is formed around the trench 17.

As a result, an electron current Je flows through the n-type channel 21 into the n-type base layer 1, and this electron current Je
The amount of positive holes is injected from the p-type emitter layer 2 into the n-type base layer 1. As a result, carriers are accumulated in the n-type base layer 1, conductivity modulation occurs in the n-type base layer 1, and the resistance of the n-type base layer 1 decreases. In this way, a current flows between the anode and the cathode.

In the semiconductor device shown in FIG. 1, since the {100} plane is dominant on the side surface of the inter-trench region 10 facing the gate electrode 5, the {110} plane is present on the side surface of the inter-trench region 90. , The resistance of the storage layer 22 is sufficiently small,
Specifically, it is reduced to about two thirds. Therefore, the electron current Jb flowing away from the storage layer 22 is sufficiently reduced.

That is, in the semiconductor device shown in FIG.
Since the ratio of the electrons moving in the storage layer 22 is increased as compared with the conventional device, the electrons efficiently reach the region 9 directly below the trench 17 without disappearing due to recombination with holes. Therefore, the amount of carriers accumulated in the region 9 is larger than that in the conventional device, and the conduction loss is small.

As a result of the experiment, the voltage between the anode and the cathode in the conducting state of the semiconductor device shown in FIG. 1 is about 10% lower than that of the conventional device in which the {110} plane is dominant on the side surface of the inter-trench region. I confirmed. Also,
When the turn-off time is adjusted by irradiating the electron beam,
It was confirmed that the voltage between the anode and the cathode of the semiconductor device shown in the figure was about 15% lower than that of the conventional device.

When the semiconductor device shown in FIG. 1 is turned off, zero or a negative voltage (negative bias voltage) is applied to the gate electrode 5 with respect to the cathode. As a result, the above n
The type channel disappears, and electrons are no longer injected from the n-type emitter layer 4 to the n-type base layer 1. As a result, the n-type base layer 1 does not undergo conductivity modulation, and the semiconductor device eventually becomes non-conductive.

Although the semiconductor device shown in FIG. 1 operates in the IGBT mode, the IEGT (Injection-Injection-
It can also be operated in Enhanced Gate Transistor mode.

That is, the depth of the portion of the trench 17 in the n-type base layer 1 is D, the distance between adjacent trenches 17 (width of the current passage) is 2 Ws, and the distance between the adjacent p-type base layers 3 is 3. 2Wt (distance between adjacent current paths)
Then, X defined by the equation X = (Wt + D) / Ws is set so as to satisfy X ≧ 5.

FIG. 3 is a sectional view showing a main part of a power semiconductor device according to another embodiment of the present invention. In the following drawings, the same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

The semiconductor device of this embodiment differs from the semiconductor device shown in FIG. 1 in that a part of the n-type base layer 1 is connected to the anode electrode 8 through an n-type anode short layer 16 having a low resistance. To be there. That is, the semiconductor device of this embodiment employs the anode short structure.

According to the semiconductor device shown in FIG. 3, electrons on the anode side in the n-type base layer 1 are discharged to the anode electrode 8 through the n-type anode short layer 16. For this reason,
The amount of accumulated carriers on the anode side in the n-type base layer 1 is reduced, and the turn-off time is shortened.

As shown in FIG. 4, the low-resistance n-type anode short layer 16 may be present beyond the p-type emitter layer 2 and into the n-type base layer 1. By forming the n-type anode short layer 16 between the p-type emitter layer 2 and the n-type base layer 1, electrons and holes are recombined in the n-type anode short layer 16 and an electron-hole pair is formed. The rate of disappearance increases. Therefore, injection of holes from the p-type emitter layer 2 to the n-type base layer 1 can be suppressed, and the amount of carriers accumulated on the anode side in the n-type base layer 1 can be further reduced.

In the structure shown in FIG. 4, for example, after the n-type anode short layer 16 is diffused and formed in the back surface of the n-type base layer 1, p is selectively formed in the front surface of the n-type anode short layer 16.
It is obtained by diffusing the mold emitter layer 2.

FIG. 5 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention. The semiconductor device of this embodiment is different from the semiconductor device shown in FIG. 1 in that a low carrier lifetime layer 11 is inserted on the anode side of the n-type base layer 1.

According to the semiconductor device shown in FIG. 5, the low carrier lifetime layer 11 reduces the amount of carriers accumulated on the anode side in the n-type base layer 1, and like the semiconductor devices shown in FIGS. Turn-off time is reduced.

The low carrier lifetime layer 11 is obtained, for example, by irradiating positive ions of proton H ⁺ from the anode side as shown in FIG. Further, in FIG. 6, although the proton H ⁺ is irradiated after the device structure is completed, the low carrier lifetime layer 11 may be formed by irradiating the proton H ⁺ before the device structure is completed.

FIG. 7 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention. The power semiconductor device of this embodiment is different from the semiconductor device shown in FIG. 1 in that the cathode electrode 7 includes all the inter-trench regions 10.
To contact some of the inter-trench regions 10 periodically. More specifically, the inter-trench region 10a that contacts the cathode electrode 7 and functions as a current path and the dummy inter-trench region 10b that is covered with the insulating layer 25 and does not function as a current path are alternately arranged. The n-type emitter layer 4 is selectively formed in the inter-trench regions 10a and 10b. Therefore, the cathode electrode 7 contacts both the p-type base layer 3 and the n-type emitter layer 4.

According to the semiconductor device shown in FIG. 7, the dummy inter-trench region 10b which is not in contact with the cathode electrode 7 is formed.
Current does not flow into the dummy trench region 10b.
Substantially function as part of the trench. As a result,
The effective area of the p-type base layer 3 is reduced, and the resistance when the holes accumulated on the cathode side of the n-type base 1 are discharged to the cathode electrode 7 is increased. As a result, the carrier accumulation layer on the cathode side of the n-type base layer 1 is increased, and the conduction loss is further reduced.

To operate in the IEGT mode,
The depth of the portion of the trench 17 in the n-type base layer 1 is D
And the distance between the {100} side surfaces of the inter-trench region 10a (width of the current passage) is 2 Ws, and the distance between adjacent inter-trench regions 10a (distance between adjacent current passages).
Is set to 2 Wt, X defined by the equation X = (Wt + D) / Ws is set so as to satisfy X ≧ 5.

It should be noted that the n-type emitter layer 4 may be composed of a plurality of regions crossing between the adjacent trenches 17 in the p-type base layer 3. Also, as shown in FIG.
Even if the n-type emitter layer 4 is not formed in the dummy inter-trench region 10b but is formed only in the inter-trench region 10a, the same effect can be obtained.

FIG. 9 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention. The power semiconductor device of this embodiment is different from the semiconductor device shown in FIG. 1 in that a low resistance n-type buffer layer 19 is provided between the n-type base layer 1 and the p-type emitter layer 2. is there.

FIG. 10 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention. The power semiconductor device of this embodiment is different from the semiconductor device shown in FIG. 5 in that a low resistance n-type buffer layer 19 is provided between the low carrier lifetime layer 11 and the p-type emitter layer 2. It is in.

FIG. 11 is a sectional view showing a main part of a power semiconductor device (power diode) according to still another embodiment of the present invention. In FIG. 11, a low resistance p-type emitter layer 2 is formed on the back surface of the high resistance n-type base layer 1.
In the n-type base layer 1, a plurality of trenches 17 reaching a depth in the middle thereof are formed. Therefore, the inter-trench region 10 made of semiconductor, that is, the current path is defined between the trenches 17. The impurity concentration of the n-type base layer 1 is 2 × 1
It is preferably 0 ¹⁴ cm ^-3 or less.

The trench 1 is formed on the inner surface of the n-type base layer 1.
A low resistance n-type emitter layer 4 is formed in contact with 7. The gate electrode 5 is formed in the trench 17 via the gate insulating film 6.
Are embedded and formed. A cathode electrode 7 is provided so as to contact the n-type emitter layer 4 and be insulated from the gate electrode 5. An anode electrode 8 is arranged so as to contact the p-type emitter layer 2.

The power semiconductor device shown in FIG. 11 is also formed by using the semiconductor substrate shown in FIG. 2 similarly to the power semiconductor device shown in FIGS. 1 to 10. The surface shape (planar shape) of the trench 17 is rectangular, and its short side is sufficiently smaller than its long side. Orientation flat 1 on the same long side
It is formed so as to be parallel to or perpendicular to 5. Therefore, the interface between the trench 17 and the inter-trench region 10 corresponding to the same long side extends along the {100} plane. The surface shape (planar shape) of the trench 17 is not limited to the rectangular shape. The point is that the ratio of the {100} plane to the side surface of the inter-trench region 10 facing the gate electrode 5 should be sufficiently high.

The operation of the power semiconductor device configured as described above is as follows. That is, at turn-on,
A voltage (forward bias voltage) is applied between the anode and the cathode so that the anode becomes positive. Here, when the gate electrode 5 has the same potential as the cathode, holes and electrons are injected into the n-type base layer 1 from the p-type emitter layer 2 and the n-type emitter layer 4, respectively. As a result, carriers are accumulated in the n-type base layer 1 and the resistance of the n-type base layer 1 is reduced, and the semiconductor device becomes conductive.

When a positive bias voltage is applied to the gate electrode 5, a storage layer 22 in which electrons are stored is formed around the trench 17. Thereby, the n-type emitter layer 4
Electron injection from the n-type base layer 1 into the storage layer 22
Will be conducted through. On the other hand, the n-type base layer 1
The holes accumulated therein are discharged to the cathode through the narrow region between the trenches 17. Therefore, the hole discharge resistance is increased, and carriers are accumulated in the region directly below the trench 17 in the n-type base layer 1. Therefore, the conduction loss of the present semiconductor device becomes lower.

When the semiconductor device shown in FIG. 11 is turned off, zero or reverse bias voltage is applied between the anode and the cathode. This prevents holes and electrons from being injected into the n-type base layer 1 from the p-type emitter layer 2 and the n-type emitter layer 4, respectively. As a result, the n-type base layer 1 does not undergo conductivity modulation, and the semiconductor device eventually becomes non-conductive.

Even when the forward bias voltage is applied between the anode and the cathode, the present semiconductor device can be turned off by applying a negative voltage (negative bias voltage) to the gate electrode 5 with respect to the cathode. . In this case, the depletion layers extending from the sidewall surface of the trench 17 to the n-type base layer 1 are in contact with each other, and the injection of electrons from the n-type emitter layer 4 is pinched off, whereby the semiconductor device becomes non-conductive.

As a modification of the semiconductor device shown in FIG. 11, the gate electrode 5 having a buried structure can be arranged not on the cathode side but on the anode side. Further, the gate electrode 5 may be provided on both the cathode side and the anode side. In this case, the same effect can be obtained by applying a negative bias voltage to the gate electrode 5 with respect to the anode electrode 8.

Further, as shown in FIG. 12, a low resistance p-type short layer 18 may be formed in the n-type emitter layer 4 so as to be in contact with the cathode electrode 7 and the n-type base layer 1.
The p-type short layer 18 may be composed of a plurality of regions that cross between the adjacent trenches 17 in the n-type emitter layer 4.

Further, the n-type base layer 1 and the p-type emitter layer 2
A low-resistance n-type buffer layer 19 (see FIG. 9) may be disposed between and. FIG. 13 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention. FIG.
4, FIG. 15, FIG. 16 and FIG. 17 are respectively XIV in FIG.
FIG. 7 is a cross-sectional view taken along line -XIV, XV-XV line, XVI-XVI line and XVII-XVII line.

A low resistance p-type emitter layer 33 is formed on the back surface of the high resistance n-type base layer 31 with a low resistance n-type buffer layer 32 interposed therebetween. A p-type base layer 34 is diffused and formed in the surface of the n-type base layer 31. The impurity concentration of the n-type base layer 31 is preferably 2 × 10 ¹⁴ cm ⁻³ or less.

In the p-type base layer 34 and the n-type base layer 31, a plurality of trenches 35 are formed which penetrate the p-type base layer 34 and reach the middle of the n-type base layer 31. The trenches 35 are stripe-shaped and are arranged in parallel with each other at a minute interval. Therefore, an inter-trench region 45 made of a semiconductor, that is, a current path is defined between the trenches 35. A gate electrode 37 is embedded in the trench 35 via a gate insulating film 36.

The surface shape (planar shape) of the trench 35 is rectangular, and its short side is sufficiently smaller than its long side. The same long side is formed so as to be parallel or perpendicular to the orientation flat 15 (see FIG. 2). Therefore, the interface between the trench 35 and the inter-trench region 45 corresponding to the same long side extends along the {100} plane. In addition, trench 3
The surface shape (planar shape) of 5 is not limited to a rectangle. The point is that the ratio of the {100} plane to the side surface of the inter-trench region 45 facing the gate electrode 37 should be sufficiently high.

The surface of the p-type base layer 34 has a low resistance n.
The type emitter layer 38 is formed by diffusion. In the n-type base layer 31, a group of low-resistance p-type ring layers 39 having the same depth as the trench 35 (e.g., 500 to 2000) is formed.
It is formed so as to surround the (book) trench 35. p
A gate lead electrode 41 is provided on a region of the mold ring layer 39 that is perpendicular to the long side of the trench 35 with a thick insulating film 40 interposed therebetween. The gate extraction electrode 41 contacts the gate electrode 37 at the end of the trench 35.

P-type base layer 34 and n-type emitter layer 38
Cathode electrode 42 is arranged so as to contact both of them. The gate electrode 37 and the cathode electrode 42 are insulated by the thick insulating film 46. In addition, the gate extraction electrode 4
A low resistance electrode 43 is disposed on the electrode 41 so as to contact the electrode 1. The low resistance electrode 43 is made of a thin film of a metal such as Al. Cathode electrode 42 and low resistance electrode 43
And are arranged in different regions and insulated from each other. An anode electrode 44 is arranged so as to contact the p-type emitter layer 33.

The p-type ring layer 39 has a sufficiently high carrier concentration so as not to be depleted by the voltage applied between the anode and the cathode when the present semiconductor device is in the off state. Specifically, the p-type ring layer 39 is 1 × 10 ¹⁷ c
It is desirable to have an average carrier concentration of m ^-3 or more.

In the semiconductor device shown in FIGS. 13 to 17, the n-type emitter layer 38 is formed in the inter-trench region 45.
In the inside, it is formed in the entire surface of the p-type base layer 34, but as in the semiconductor device shown in FIG. 1, it may be partially formed along the long side of the trench 35 so as to be in contact therewith. . In this case, the p-type base layer 34 contacts the cathode electrode 42 between the n-type emitter layers 38.

The semiconductor device shown in FIGS. 13 to 17 is in the off state, that is, the cathode electrode 42 is grounded and the gate electrode 3
When a predetermined positive voltage is applied to the anode electrode 44 in a state where a voltage equal to or lower than the threshold voltage is applied to 7,
The potential distribution near the trench 35 in the n-type base layer 31 is as shown by the broken line in FIG. As shown in FIG. 14, p
By forming the mold ring layer 39, the equipotential lines become linear even at the corners of the bottom of the trench 35,
Electric field concentration is relieved. This makes it possible to prevent the breakdown voltage of the semiconductor device from deteriorating.

FIG. 18 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention. FIG.
20 and 20 are XIX-XIX line and XX-XX in FIG. 18, respectively.
It is sectional drawing along the line. In addition, cross sections taken along the line XV-XV and the line XVI-XVI in FIG. 18 are shown in FIGS. 15 and 16, respectively.
It is substantially the same as the cross section shown. In the following drawings, the same parts as those in FIGS. 13 to 17 are designated by the same reference numerals, and detailed description thereof will be omitted.

The power semiconductor device of this embodiment is shown in FIG.
3 to 17 is different from the semiconductor device shown in FIGS. 3 to 17 in that the cathode electrode 42 does not contact all the inter-trench regions 45 but periodically contacts a part of the inter-trench regions 45. More specifically, the inter-trench region 4 that contacts the cathode electrode 42 and functions as a current path.
5a and regions 45b between dummy trenches which are covered with the insulating layer 46 and do not function as current paths are alternately arranged.

According to the semiconductor device shown in FIGS. 18 to 20, since no current flows in the dummy inter-trench region 45b which is not in contact with the cathode electrode 42, the dummy inter-trench region 45b substantially functions as a part of the trench. To do. As a result, the effective area of the p-type base layer 43 is reduced, and the resistance when the holes accumulated on the cathode side of the n-type base 31 are discharged to the cathode electrode 42 is increased. As a result, the carrier accumulation layer on the cathode side of the n-type base layer 31 increases, and the conduction loss is further reduced.

FIG. 21 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention. FIG.
FIG. 22 is a sectional view taken along line XXII-XXII in FIG. 21. The power semiconductor device of this embodiment is different from the semiconductor devices shown in FIGS. 13 to 17 in that the trench 35 is formed after the p-type ring layer 39 is diffused and formed. Therefore, the p-type impurity diffuses laterally, and the p-type ring layer 39 spreads to the region where the trench 35 is formed.

In the case of such a structure, in order to increase the latch-up tolerance (latch-up start current), the inside of the inter-trench region 45 not separated from the pattern edge of the p-type ring layer 39 by the distance L1 longer than the lateral diffusion distance. Has n
The type emitter layer 38 is not formed.

In consideration of the lateral diffusion of p-type impurities, the pattern edge of the p-type ring layer 39 is located outside the side surface of the trench 35 by a distance L2 smaller than the width of the trench 35, as shown in FIG. You may arrange.

22 and 23 show potential distributions in the vicinity of the trench 35 in the n-type base layer 31 when a predetermined positive voltage is applied to the anode electrode 44 in the off state of the semiconductor device shown in FIGS. 22 and 23, respectively. 23 is indicated by a broken line.

[0075]

According to the power semiconductor device of the present invention, the dominant side surface orientation of the side surface of the current path facing the gate electrode disposed in the trench is the {100} plane. In this state, the amount of carriers accumulated in the base layer directly below the trench can be increased, and the conduction loss can be reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a power semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor substrate used for manufacturing the power semiconductor device shown in FIG.

FIG. 3 is a sectional view showing a main part of a power semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 5 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

6 is a diagram for explaining a method of forming a low carrier lifetime layer of the power semiconductor device shown in FIG.

FIG. 7 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 8 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 9 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 10 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 11 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 12 is a sectional view showing an essential part of a power semiconductor device according to still another embodiment of the present invention. Sectional drawing which shows the modification of the power semiconductor device of FIG.

FIG. 13 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

14 is a sectional view taken along line XIV-XIV in FIG.

FIG. 15 is a sectional view taken along line XV-XV in FIG.

16 is a sectional view taken along line XVI-XVI in FIG.

FIG. 17 is a sectional view taken along line XVII-XVII in FIG.

FIG. 18 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 19 is a sectional view taken along line XIX-XIX in FIG.

20 is a cross-sectional view taken along the line XX-XX in FIG.

FIG. 21 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

22 is a sectional view taken along line XXII-XXII in FIG. 21.

FIG. 23 is a sectional view showing an essential part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 24 is a cross-sectional view showing a main part of a conventional power semiconductor device.

25 is a plan view showing a semiconductor substrate used for manufacturing the power semiconductor device shown in FIG. 24. FIG.

[Explanation of symbols]

 1, 31 ... N-type base layer (second conductivity type base layer) 2, 33 ... P-type emitter layer (first conductivity type emitter layer) 3, 34 ... P-type base layer (first conductivity type base layer) 4, 38 ... N-type emitter layer (second conductivity type emitter layer) 5, 37 ... Gate electrode 6, 36 ... Gate insulating film 7, 42 ... Cathode electrode (first main electrode) 8, 44 ... Anode electrode (second electrode) Main electrode) 10, 45 ... Inter-trench region 11 ... Low carrier lifetime layer 16 ... N-type anode short layer 17, 35 ... Trench

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromichi Ohashi No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (9)

[Claims] 1. A first-conductivity-type emitter layer, a second-conductivity-type base layer formed on the first-conductivity-type emitter layer, and causing conductivity modulation in an ON state of the device; A first conductive type base layer formed in the surface, and a first conductive type base layer that penetrates the first conductive type base layer and reaches a midway depth of the second conductive type base layer to define a plurality of current paths. A plurality of formed trenches, a gate electrode embedded in the trench via a gate insulating film so as to face each current path, and formed in each current path and on the surface of the first conductivity type base layer. Second conductive type emitter layer, a first main electrode connected to the second conductive type emitter layer and the first conductive type base layer, and a second main electrode connected to the first conductive type emitter layer And, the gate electrode The side surface of the facing current path is substantially a {100} surface, and a storage layer of a second conductivity type carrier in the side surface of the current path and in the second conductivity type base layer when the device is in an on state. Is formed, and the second conductivity type carriers are injected into the region in the second conductivity type base layer below the trench through the storage layer. 2. When the depth of the trench in the second conductive type base layer is D, the width of the current passage is 2 Ws, and the distance between adjacent current passages is 2 Wt, X = (Wt + D ) / Ws X is X ≧ 5
The power semiconductor device according to claim 1, wherein 3. A first-conductivity-type emitter layer, a second-conductivity-type base layer formed on the first-conductivity-type emitter layer, and causing conductivity modulation when the device is in an on-state, and the second-conductivity-type base layer. A second conductive type emitter layer formed in the surface, and penetrating the second conductive type emitter layer and reaching an intermediate depth of the second conductive type base layer to define a plurality of current paths. A plurality of formed trenches, a gate electrode buried in the trench via a gate insulating film so as to face each current path, a first main electrode connected to the second conductivity type emitter layer, A second main electrode connected to the first conductivity type emitter layer, and a side surface of the current path facing the gate electrode is substantially a {100} surface, and the side surface of the current path is in the ON state of the device. Within said side of the current path A storage layer of second conductivity type carriers is formed in the second conductivity type base layer, and the second conductivity type carriers are formed through the storage layer to a region in the second conductivity type base layer below the trench. A semiconductor device for electric power, characterized in that is injected. 4. The impurity concentration of the second conductivity type base layer is 2
4. The power semiconductor device according to claim 1, wherein the power semiconductor device has a density of ^{x10 14} cm ^-3 or less. 5. The buffer layer according to claim 1, further comprising a second conductivity type buffer layer disposed between the first conductivity type emitter layer and the second conductivity type base layer. The semiconductor device for electric power as described in 1. 6. The power semiconductor device according to claim 1, further comprising a low carrier lifetime layer formed in the second conductivity type base layer. 7. Each of the trenches comprises a plurality of trench portions and a dummy inter-trench region located between the trench portions and having a surface covered with an insulating film. The semiconductor device for electric power as described in 1. 8. A first conductivity type ring layer formed in the surface of the second conductivity type base layer so as to surround the trench and the current path and to have a depth substantially the same as the trench. The power semiconductor device according to claim 1, wherein the power semiconductor device is provided. 9. A low resistance comprising a gate lead electrode connected to the gate electrode and provided on the first conductivity type ring layer via an insulating film, and a metal thin film provided on the lead electrode. 9. The power semiconductor device according to claim 8, further comprising: a charge conversion electrode.